From patchwork Tue May 1 08:59:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 134744 Delivered-To: patches@linaro.org Received: by 10.46.151.6 with SMTP id r6csp4727011lji; Tue, 1 May 2018 01:59:46 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrlG/pqhuYcgWoUYqTImXASor+GSh9FdrOGMs0ZvOlAPvBTz53I9BYL/wvkpyQceaqBSyOM X-Received: by 2002:a65:5088:: with SMTP id r8-v6mr7187765pgp.80.1525165186172; Tue, 01 May 2018 01:59:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525165186; cv=none; d=google.com; s=arc-20160816; b=ozWE2sxeQA6z+tt9yySmUWylOCN4c4iLzMKe1lC5BNEMExIN5rZs7GeyZ9UhF0fGa+ QiUey5N/J9++6VwyCki3YYe9MeTIkCfGreyF3y8GXVS8duln03tbXKr3lbRd5jARao82 HsWZv+ilYBzrCUmcK0rFlkO9V8awKavkCi6ESn0aOcHIzmh0bwjJzpMagHCWcYozYeba 2B9XJWjE9a/8CHnGXDWb89jsH7uXNeSjeLLbUBoa8M5q8VwfNabjI+juOm4OEqo9Lut0 +L2xTM0CyWGBMC0Yjm6IJUz0YwkNxFz6rfskVLq42kiW9eh3V+YvtALoi/qrycALHFKs s2DA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=FDmGTJyJ53+VLbqnVf/0PZihcU8CZKKDROugiG+bFvE=; b=jBdCdzioXxZNxLcDI9kd+gEa8dn1aQaNzwEpHRcixmMpEehlDGjnf5udZy34thpIRu 0EmR0/EDoLHHgrj4IThrsWeXnUYjXQK5uYcM7VRbeQilGRWAaWLh2aazMwKJPdUHFcRz FXvxJ1JRnLUHxEdrlRN6mlesKD/HgHiNbfGqWuS15luY+BPLibImnFwsb6skYUgf/V/U PiyFugVYQONTZDnEgik+B/sAqqeQYEGWlKV73vBeMOYpaDzmYBIF4xxbyFzVwpIVl0Il YU9KkRNzzE7NxTrWiHDd0sF2QV8qG/GfLWStgk1X8F+XyFUcU237I9LUf0/aNlJeMSL6 kJIQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id s1-v6si7606562pgb.281.2018.05.01.01.59.45 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 01 May 2018 01:59:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fDR8P-0007Ll-9E; Tue, 01 May 2018 09:59:41 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paolo Bonzini , Eric Auger Subject: [RFC PATCH v2 01/12] Make tb_invalidate_phys_addr() take a MemTxAttrs argument Date: Tue, 1 May 2018 09:59:28 +0100 Message-Id: <20180501085939.6201-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180501085939.6201-1-peter.maydell@linaro.org> References: <20180501085939.6201-1-peter.maydell@linaro.org> As part of plumbing MemTxAttrs down to the IOMMU translate method, add MemTxAttrs as an argument to tb_invalidate_phys_addr(). Its callers either have an attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED. Signed-off-by: Peter Maydell --- include/exec/exec-all.h | 5 +++-- accel/tcg/translate-all.c | 2 +- exec.c | 2 +- target/xtensa/op_helper.c | 3 ++- 4 files changed, 7 insertions(+), 5 deletions(-) -- 2.17.0 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index bd68328ed9..4d09eaba72 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -255,7 +255,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, void tlb_set_page(CPUState *cpu, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size); -void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr); +void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs); void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx, uintptr_t retaddr); #else @@ -303,7 +303,8 @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap) { } -static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr) +static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs) { } #endif diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index f409d42d54..f04a922ef7 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1672,7 +1672,7 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr) } #if !defined(CONFIG_USER_ONLY) -void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr) +void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs) { ram_addr_t ram_addr; MemoryRegion *mr; diff --git a/exec.c b/exec.c index c7fcefa851..df35e6dd85 100644 --- a/exec.c +++ b/exec.c @@ -863,7 +863,7 @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) if (phys != -1) { /* Locks grabbed by tb_invalidate_phys_addr */ tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as, - phys | (pc & ~TARGET_PAGE_MASK)); + phys | (pc & ~TARGET_PAGE_MASK), attrs); } } #endif diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index e3bcbe10d6..8a8c763c63 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -105,7 +105,8 @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr) int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0, &paddr, &page_size, &access); if (ret == 0) { - tb_invalidate_phys_addr(&address_space_memory, paddr); + tb_invalidate_phys_addr(&address_space_memory, paddr, + MEMTXATTRS_UNSPECIFIED); } }