From patchwork Tue May 1 08:59:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 134749 Delivered-To: patches@linaro.org Received: by 10.46.151.6 with SMTP id r6csp4727043lji; Tue, 1 May 2018 01:59:49 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqDRYeW9nERbLO7qy4ltLGn/goQD8xtjN2Mq2Z1HSy9C8DEnsQAYVBP7oGY/TOV3d6EpKKS X-Received: by 10.28.55.194 with SMTP id e185mr9096719wma.20.1525165189860; Tue, 01 May 2018 01:59:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525165189; cv=none; d=google.com; s=arc-20160816; b=Q1lcNVeujybrKkV5WBCdEymZK6mkcFRqNQG8CmlxpnUruDeZ+lpTHEg8JFxAxKR28M ErtfrTrd2sUpLlXmTbBzX3V+WHQRgvv+lIMoHvf3ZmK+lz5NZOdSHFqwNGB4k83TAYxM DJMHtkBg7IUl5tquS8GvJfBBgZ+vvML+REvBFvFnhS1g/IUK/WgNhU3ZAzu5H9zTvIUu XUlvINZcGHZ9TSLSJYEMrL5+yphGexw3xsmWe15saSGMMxYRLN44pHPq/RZNzYzGZHix 0GpQoWi5MK7WWc6GPke3mkg6BOi/EWkPjIJklKLfH0Cfw9bXMiNFvIUDBrphhX/8r3lU Hkag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=EROKIGZhiPUu4DVqbyEMYPMGDTGM3HpjXnNog6UCvbY=; b=eNtcCCBb5LY+2vfQoDqmbEX8UOS85bGNxFdiNX5nLlaCeo4DExSTSwkHyCegDLnRul HXr104P8b1Jm4+mFSkbw+iDXDmurFDMZsiMuHgtE8KhNGaPvs6+L9tW8mKBSfPhqnnaW jOcILDz18N3pGpZ548IF9AEYEbKZmEgKODTFYQGZTx748ZrDQiinb70mRNFJmhkhWSqk mLN9IIdsudxi4ui+seKOEQTMih91SCN9euULc4b6hcZvX2t5J15EUGeqVPitKNFHI+Lb 4dQssDCa6Zqe158HYCQrk1mlDYLLoz9/2TuN2Lt/KWI8hKNjX1w03PQwwyCaKhbB83gV Z/yQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id w19-v6si7833398wrb.286.2018.05.01.01.59.49 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 01 May 2018 01:59:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fDR8X-0007RI-BZ; Tue, 01 May 2018 09:59:49 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paolo Bonzini , Eric Auger Subject: [RFC PATCH v2 12/12] Add MemTxAttrs argument to IOMMU translate function Date: Tue, 1 May 2018 09:59:39 +0100 Message-Id: <20180501085939.6201-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180501085939.6201-1-peter.maydell@linaro.org> References: <20180501085939.6201-1-peter.maydell@linaro.org> Add a MemTxAttrs argument to the IOMMU translate function; this is necessary for IOMMU implementations that care about transaction attributes such as user/privileged or secure/nonsecure when deciding whether a transaction is permitted. Signed-off-by: Peter Maydell --- include/exec/memory.h | 3 ++- exec.c | 2 +- hw/alpha/typhoon.c | 3 ++- hw/dma/rc4030.c | 3 ++- hw/i386/amd_iommu.c | 3 ++- hw/i386/intel_iommu.c | 3 ++- hw/ppc/spapr_iommu.c | 3 ++- hw/s390x/s390-pci-bus.c | 3 ++- hw/sparc/sun4m_iommu.c | 3 ++- hw/sparc64/sun4u_iommu.c | 3 ++- memory.c | 3 ++- 11 files changed, 21 insertions(+), 11 deletions(-) -- 2.17.0 diff --git a/include/exec/memory.h b/include/exec/memory.h index 16a82d9722..2c7dd4b373 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -221,9 +221,10 @@ typedef struct IOMMUMemoryRegionClass { * @iommu: the IOMMUMemoryRegion * @hwaddr: address to be translated within the memory region * @flag: requested access permissions + * @attrs: memory transaction attributes */ IOMMUTLBEntry (*translate)(IOMMUMemoryRegion *iommu, hwaddr addr, - IOMMUAccessFlags flag); + IOMMUAccessFlags flag, MemTxAttrs attrs); /* Returns minimum supported page size in bytes. * If this method is not provided then the minimum is assumed to * be TARGET_PAGE_SIZE. diff --git a/exec.c b/exec.c index 9c6d9aae28..e346424172 100644 --- a/exec.c +++ b/exec.c @@ -513,7 +513,7 @@ static MemoryRegionSection flatview_do_translate(FlatView *fv, imrc = memory_region_get_iommu_class_nocheck(iommu_mr); iotlb = imrc->translate(iommu_mr, addr, is_write ? - IOMMU_WO : IOMMU_RO); + IOMMU_WO : IOMMU_RO, attrs); addr = ((iotlb.translated_addr & ~iotlb.addr_mask) | (addr & iotlb.addr_mask)); page_mask &= iotlb.addr_mask; diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index 6a40869488..49192ab24d 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -666,7 +666,8 @@ static bool window_translate(TyphoonWindow *win, hwaddr addr, Pchip and generate a machine check interrupt. */ static IOMMUTLBEntry typhoon_translate_iommu(IOMMUMemoryRegion *iommu, hwaddr addr, - IOMMUAccessFlags flag) + IOMMUAccessFlags flag, + MemTxAttrs attrs) { TyphoonPchip *pchip = container_of(iommu, TyphoonPchip, iommu); IOMMUTLBEntry ret; diff --git a/hw/dma/rc4030.c b/hw/dma/rc4030.c index 5d4833eeca..89686ae7dc 100644 --- a/hw/dma/rc4030.c +++ b/hw/dma/rc4030.c @@ -491,7 +491,8 @@ static const MemoryRegionOps jazzio_ops = { }; static IOMMUTLBEntry rc4030_dma_translate(IOMMUMemoryRegion *iommu, hwaddr addr, - IOMMUAccessFlags flag) + IOMMUAccessFlags flag, + MemTxAttrs attrs) { rc4030State *s = container_of(iommu, rc4030State, dma_mr); IOMMUTLBEntry ret = { diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 63d46ff6ee..5f530b5fe6 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -991,7 +991,8 @@ static inline bool amdvi_is_interrupt_addr(hwaddr addr) } static IOMMUTLBEntry amdvi_translate(IOMMUMemoryRegion *iommu, hwaddr addr, - IOMMUAccessFlags flag) + IOMMUAccessFlags flag, + MemTxAttrs attrs) { AMDVIAddressSpace *as = container_of(iommu, AMDVIAddressSpace, iommu); AMDVIState *s = as->iommu_state; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index fb31de9416..483ff305f8 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2282,7 +2282,8 @@ static void vtd_mem_write(void *opaque, hwaddr addr, } static IOMMUTLBEntry vtd_iommu_translate(IOMMUMemoryRegion *iommu, hwaddr addr, - IOMMUAccessFlags flag) + IOMMUAccessFlags flag, + MemTxAttrs attrs) { VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu); IntelIOMMUState *s = vtd_as->iommu_state; diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c index aaa6010d5c..199612095a 100644 --- a/hw/ppc/spapr_iommu.c +++ b/hw/ppc/spapr_iommu.c @@ -112,7 +112,8 @@ static void spapr_tce_free_table(uint64_t *table, int fd, uint32_t nb_table) /* Called from RCU critical section */ static IOMMUTLBEntry spapr_tce_translate_iommu(IOMMUMemoryRegion *iommu, hwaddr addr, - IOMMUAccessFlags flag) + IOMMUAccessFlags flag, + MemTxAttrs attrs) { sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu); uint64_t tce; diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c index 10da87458e..77588c2355 100644 --- a/hw/s390x/s390-pci-bus.c +++ b/hw/s390x/s390-pci-bus.c @@ -484,7 +484,8 @@ uint16_t s390_guest_io_table_walk(uint64_t g_iota, hwaddr addr, } static IOMMUTLBEntry s390_translate_iommu(IOMMUMemoryRegion *mr, hwaddr addr, - IOMMUAccessFlags flag) + IOMMUAccessFlags flag, + MemTxAttrs attrs) { S390PCIIOMMU *iommu = container_of(mr, S390PCIIOMMU, iommu_mr); S390IOTLBEntry *entry; diff --git a/hw/sparc/sun4m_iommu.c b/hw/sparc/sun4m_iommu.c index b677601fc6..f68bcade3c 100644 --- a/hw/sparc/sun4m_iommu.c +++ b/hw/sparc/sun4m_iommu.c @@ -282,7 +282,8 @@ static void iommu_bad_addr(IOMMUState *s, hwaddr addr, /* Called from RCU critical section */ static IOMMUTLBEntry sun4m_translate_iommu(IOMMUMemoryRegion *iommu, hwaddr addr, - IOMMUAccessFlags flags) + IOMMUAccessFlags flags, + MemTxAttrs attrs) { IOMMUState *is = container_of(iommu, IOMMUState, iommu); hwaddr page, pa; diff --git a/hw/sparc64/sun4u_iommu.c b/hw/sparc64/sun4u_iommu.c index eb3aaa87e6..7a5a588aed 100644 --- a/hw/sparc64/sun4u_iommu.c +++ b/hw/sparc64/sun4u_iommu.c @@ -73,7 +73,8 @@ /* Called from RCU critical section */ static IOMMUTLBEntry sun4u_translate_iommu(IOMMUMemoryRegion *iommu, hwaddr addr, - IOMMUAccessFlags flag) + IOMMUAccessFlags flag, + MemTxAttrs attrs) { IOMMUState *is = container_of(iommu, IOMMUState, iommu); hwaddr baseaddr, offset; diff --git a/memory.c b/memory.c index a729c29862..dbb9718bea 100644 --- a/memory.c +++ b/memory.c @@ -1832,7 +1832,8 @@ void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n) granularity = memory_region_iommu_get_min_page_size(iommu_mr); for (addr = 0; addr < memory_region_size(mr); addr += granularity) { - iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE); + iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, + MEMTXATTRS_UNSPECIFIED); if (iotlb.perm != IOMMU_NONE) { n->notify(n, &iotlb); }