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[209.132.180.67]) by mx.google.com with ESMTP id k75si14696835pfk.369.2018.05.03.23.03.02; Thu, 03 May 2018 23:03:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bhoIMWPn; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751913AbeEDGDB (ORCPT + 29 others); Fri, 4 May 2018 02:03:01 -0400 Received: from mail-wr0-f195.google.com ([209.85.128.195]:38980 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751404AbeEDGBW (ORCPT ); Fri, 4 May 2018 02:01:22 -0400 Received: by mail-wr0-f195.google.com with SMTP id q3-v6so19759162wrj.6 for ; Thu, 03 May 2018 23:01:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sh4YVFRw2/+o8lExuE/Ryw+Zqd/USN5S4QasrIDqD3s=; b=bhoIMWPnOV7Nkg44YE++r762e1O0wgV3iu4kZENl6y+GBzmST0RBEZ2QBT8pJ4mIIW wljIBdRp4+F6DHKBzWnAAqsAoy5w4v1c6Fvuhyhtg7PIPUFHu5UiNwPSg7fed/JyIoSn Nez620pBi+c3Crhp2UzcUgtjVa2WO5SDFgmiE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sh4YVFRw2/+o8lExuE/Ryw+Zqd/USN5S4QasrIDqD3s=; b=A9H1xwLJxbMxGtcj8O3Tx0qUrAHrV++nRtzduiwlDld9IPE8llX2XXLCy4GVJZkOsr pwAnu0yy89AnEBGgn+lAC5VE6BZ+Oc8QRZhPs/HowqARbEW+ciFzvy2LfbODefopDfYF w1nDyIbN+jU5B74+suSQueLb5e3afrovGASCv03ITD/TeTZk3GYpfz07Y3VKDumh4hDh AFoSXcetx2iJ8g2qzKGMvdpff7kxXCPG98SL5y5F2JoDxw0o/J3zgoHAaAZxO0RXqJQ5 JCb/JH1VsIUUZmg0ouZD1NWpOl5nauaIuWhoqobGG5wdpSSLYjgFbjDow5owPvS3cos7 FByw== X-Gm-Message-State: ALQs6tAl8dZuuObcO4oMPfIGN/b4gOo/HpLhUK9v7FMom0Azpu+OZnYV HMFYKdSBukfOsZraKJ4/xfrQeA== X-Received: by 2002:adf:b067:: with SMTP id g36-v6mr19984395wra.128.1525413680844; Thu, 03 May 2018 23:01:20 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:3995:5470:200:1aff:fe1b:b328]) by smtp.gmail.com with ESMTPSA id i30-v6sm32411863wra.38.2018.05.03.23.01.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 May 2018 23:01:20 -0700 (PDT) From: Ard Biesheuvel To: linux-efi@vger.kernel.org, Ingo Molnar , Thomas Gleixner Cc: Yazen Ghannam , Ard Biesheuvel , linux-kernel@vger.kernel.org Subject: [PATCH 10/17] efi: Decode IA32/X64 Context Info structure Date: Fri, 4 May 2018 07:59:56 +0200 Message-Id: <20180504060003.19618-11-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180504060003.19618-1-ard.biesheuvel@linaro.org> References: <20180504060003.19618-1-ard.biesheuvel@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Yazen Ghannam Print the fields of the IA32/X64 Context Information structure. Print the "Register Array" as raw values. Some context types are defined in the UEFI spec, so more detailed decoded may be added in the future. Based on UEFI 2.7 section N.2.4.2.2 IA32/X64 Processor Context Information Structure. Signed-off-by: Yazen Ghannam Signed-off-by: Ard Biesheuvel --- drivers/firmware/efi/cper-x86.c | 48 +++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) -- 2.17.0 diff --git a/drivers/firmware/efi/cper-x86.c b/drivers/firmware/efi/cper-x86.c index 356b8d326219..2531de49f56c 100644 --- a/drivers/firmware/efi/cper-x86.c +++ b/drivers/firmware/efi/cper-x86.c @@ -10,6 +10,7 @@ #define VALID_LAPIC_ID BIT_ULL(0) #define VALID_CPUID_INFO BIT_ULL(1) #define VALID_PROC_ERR_INFO_NUM(bits) (((bits) & GENMASK_ULL(7, 2)) >> 2) +#define VALID_PROC_CXT_INFO_NUM(bits) (((bits) & GENMASK_ULL(13, 8)) >> 8) #define INFO_ERR_STRUCT_TYPE_CACHE \ GUID_INIT(0xA55701F5, 0xE3EF, 0x43DE, 0xAC, 0x72, 0x24, 0x9B, \ @@ -71,6 +72,9 @@ #define CHECK_MS_RESTARTABLE_IP BIT_ULL(22) #define CHECK_MS_OVERFLOW BIT_ULL(23) +#define CTX_TYPE_MSR 1 +#define CTX_TYPE_MMREG 7 + enum err_types { ERR_TYPE_CACHE = 0, ERR_TYPE_TLB, @@ -134,6 +138,17 @@ static const char * const ia_check_ms_error_type_strs[] = { "Internal Unclassified", }; +static const char * const ia_reg_ctx_strs[] = { + "Unclassified Data", + "MSR Registers (Machine Check and other MSRs)", + "32-bit Mode Execution Context", + "64-bit Mode Execution Context", + "FXSAVE Context", + "32-bit Mode Debug Registers (DR0-DR7)", + "64-bit Mode Debug Registers (DR0-DR7)", + "Memory Mapped Registers", +}; + static inline void print_bool(char *str, const char *pfx, u64 check, u64 bit) { printk("%s%s: %s\n", pfx, str, (check & bit) ? "true" : "false"); @@ -242,6 +257,7 @@ void cper_print_proc_ia(const char *pfx, const struct cper_sec_proc_ia *proc) { int i; struct cper_ia_err_info *err_info; + struct cper_ia_proc_ctx *ctx_info; char newpfx[64], infopfx[64]; u8 err_type; @@ -305,4 +321,36 @@ void cper_print_proc_ia(const char *pfx, const struct cper_sec_proc_ia *proc) err_info++; } + + ctx_info = (struct cper_ia_proc_ctx *)err_info; + for (i = 0; i < VALID_PROC_CXT_INFO_NUM(proc->validation_bits); i++) { + int size = sizeof(*ctx_info) + ctx_info->reg_arr_size; + int groupsize = 4; + + printk("%sContext Information Structure %d:\n", pfx, i); + + printk("%sRegister Context Type: %s\n", newpfx, + ctx_info->reg_ctx_type < ARRAY_SIZE(ia_reg_ctx_strs) ? + ia_reg_ctx_strs[ctx_info->reg_ctx_type] : "unknown"); + + printk("%sRegister Array Size: 0x%04x\n", newpfx, + ctx_info->reg_arr_size); + + if (ctx_info->reg_ctx_type == CTX_TYPE_MSR) { + groupsize = 8; /* MSRs are 8 bytes wide. */ + printk("%sMSR Address: 0x%08x\n", newpfx, + ctx_info->msr_addr); + } + + if (ctx_info->reg_ctx_type == CTX_TYPE_MMREG) { + printk("%sMM Register Address: 0x%016llx\n", newpfx, + ctx_info->mm_reg_addr); + } + + printk("%sRegister Array:\n", newpfx); + print_hex_dump(newpfx, "", DUMP_PREFIX_OFFSET, 16, groupsize, + (ctx_info + 1), ctx_info->reg_arr_size, 0); + + ctx_info = (struct cper_ia_proc_ctx *)((long)ctx_info + size); + } }