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[209.132.180.67]) by mx.google.com with ESMTP id k7-v6si2186867pls.368.2018.05.10.19.04.22; Thu, 10 May 2018 19:04:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=O55ZvRBg; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750937AbeEKCEV (ORCPT + 6 others); Thu, 10 May 2018 22:04:21 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:34789 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750798AbeEKCEV (ORCPT ); Thu, 10 May 2018 22:04:21 -0400 Received: by mail-pf0-f195.google.com with SMTP id a14-v6so1955359pfi.1 for ; Thu, 10 May 2018 19:04:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=ZOe5xm/kAn1ifE+NyKuVnvTnIf3aOMXUUFkL1Xm4QrM=; b=O55ZvRBggwewY8KXlO3QctXQgwYJJJxGu9ZUg8n3bF4KdTOfvKVqlUI9IJ/bUoEMO/ xbDEbkt2N3bvFfWzshoWUudLhdZ2kZtHGteOGV1NkfRW9QxUACqU5hRioNqN1R6AAC1N 2LFdmjAV6dMpCZtQesVmAHDFfY4jX4+2teB7I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=ZOe5xm/kAn1ifE+NyKuVnvTnIf3aOMXUUFkL1Xm4QrM=; b=MzMQ6ZLI7IFvNwMHIj2YNwoetBPArHH9qeGpHasGTJFRi54354S+JLF8VpWU9O3fPF bPHmjGNFKlyH+83LkSSMFYAblXla27uEWSIjUbk5sRgrbXs/adLZjFk7YETIUgKT2Lad /XR5K9htIk8uiEofMp8iJ58SHrT7jLAZ2FmF+0hygYggZ7l1LY2tQ57pTEbgfPiNKhBn DKBNwcbiIH3xUYxXUy2aaU4HmeAKFtdh96oMRdxXFJvO+tCZ3xVw9esBMemjLSY7AvvE lpHP2nKPvuHodi38HVbotIUIccE3hZ/CHG/xFRTAipwd3Q0I3NIDlsUMWdyMdP6OnnkB L53A== X-Gm-Message-State: ALKqPwdUGyt4vXSbtDr38VNWO7vljwMlvXPJ2TBtQwoi+Qcalp8fJcqR bkOO6t3m/lkd38dZsOpLqiECPg== X-Received: by 2002:a65:4d0b:: with SMTP id i11-v6mr1192149pgt.51.1526004260298; Thu, 10 May 2018 19:04:20 -0700 (PDT) Received: from localhost.localdomain ([45.56.152.100]) by smtp.gmail.com with ESMTPSA id x5-v6sm2955254pgv.15.2018.05.10.19.04.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 10 May 2018 19:04:18 -0700 (PDT) From: Shawn Guo To: Wei Xu Cc: Jianguo Sun , Jiancheng Xue , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Shawn Guo Subject: [PATCH 1/3] arm64: dts: hi3798cv200: enable PCIe support for poplar board Date: Fri, 11 May 2018 10:03:38 +0800 Message-Id: <1526004220-17030-1-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It adds combophy devices under peripheral controller and enables PCIe support for Hi3798CV200 Poplar board. Signed-off-by: Shawn Guo --- .../boot/dts/hisilicon/hi3798cv200-poplar.dts | 15 ++++++ arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 63 ++++++++++++++++++++++ 2 files changed, 78 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts index 4d5d644abb12..c4382e1f3c92 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts @@ -61,6 +61,15 @@ default-state = "off"; }; }; + + reg_pcie: regulator-pcie { + compatible = "regulator-fixed"; + regulator-name = "3V3_PCIE0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio6 7 0>; + enable-active-high; + }; }; &gmac1 { @@ -146,6 +155,12 @@ status = "okay"; }; +&pcie { + reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; + vpcie-supply = <®_pcie>; + status = "okay"; +}; + &sd0 { bus-width = <4>; cap-sd-highspeed; diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index 962bd79139e4..5b73403551e6 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -8,7 +8,9 @@ */ #include +#include #include +#include #include / { @@ -106,6 +108,37 @@ #reset-cells = <2>; }; + perictrl: peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", + "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8a20000 0x1000>; + + combphy0: phy@850 { + compatible = "hisilicon,hi3798cv200-combphy"; + reg = <0x850 0x8>; + #phy-cells = <1>; + clocks = <&crg HISTB_COMBPHY0_CLK>; + resets = <&crg 0x188 4>; + assigned-clocks = <&crg HISTB_COMBPHY0_CLK>; + assigned-clock-rates = <100000000>; + hisilicon,fixed-mode = ; + }; + + combphy1: phy@858 { + compatible = "hisilicon,hi3798cv200-combphy"; + reg = <0x858 0x8>; + #phy-cells = <1>; + clocks = <&crg HISTB_COMBPHY1_CLK>; + resets = <&crg 0x188 12>; + assigned-clocks = <&crg HISTB_COMBPHY1_CLK>; + assigned-clock-rates = <100000000>; + hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>; + }; + }; + uart0: serial@8b00000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x8b00000 0x1000>; @@ -419,5 +452,35 @@ clocks = <&sysctrl HISTB_IR_CLK>; status = "disabled"; }; + + pcie: pcie@9860000 { + compatible = "hisilicon,hi3798cv200-pcie"; + reg = <0x9860000 0x1000>, + <0x0 0x2000>, + <0x2000000 0x01000000>; + reg-names = "control", "rc-dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0 15>; + num-lanes = <1>; + ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000 + 0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_PCIE_AUX_CLK>, + <&crg HISTB_PCIE_PIPE_CLK>, + <&crg HISTB_PCIE_SYS_CLK>, + <&crg HISTB_PCIE_BUS_CLK>; + clock-names = "aux", "pipe", "sys", "bus"; + resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>; + reset-names = "soft", "sys", "bus"; + phys = <&combphy1 PHY_TYPE_PCIE>; + phy-names = "phy"; + status = "disabled"; + }; }; };