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[203.254.224.24]) by mx.google.com with ESMTP id g1si4995405paw.129.2012.12.14.03.53.26; Fri, 14 Dec 2012 03:53:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) client-ip=203.254.224.24; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MF0000AHROVPE00@mailout1.samsung.com>; Fri, 14 Dec 2012 20:53:25 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.123]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 49.DD.12699.5331BC05; Fri, 14 Dec 2012 20:53:25 +0900 (KST) X-AuditID: cbfee61b-b7f616d00000319b-8a-50cb133580d0 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id C8.DD.12699.5331BC05; Fri, 14 Dec 2012 20:53:25 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MF000GYFRKI4870@mmp2.samsung.com>; Fri, 14 Dec 2012 20:53:25 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org Subject: [PATCH 04/16] EXYNOS5: FDT : Decode peripheral id Date: Fri, 14 Dec 2012 17:26:17 +0530 Message-id: <1355486189-432-4-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1355486189-432-1-git-send-email-rajeshwari.s@samsung.com> References: <1355486189-432-1-git-send-email-rajeshwari.s@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrELMWRmVeSWpSXmKPExsWyRsSkWtdU+HSAwfR9FhYP199ksZhy+AuL A5PHnWt72AIYo7hsUlJzMstSi/TtErgy1jTMYy34JlOx+9gn5gbG/+JdjJwcEgImEudvdjNB 2GISF+6tZ+ti5OIQEljKKDHvyDQWmKKlb9ewQCSmM0pMP7iLGcKZyCTRu2ERWDubgJHE1pPT GEFsEQEJiV/9V8FsZoEYidf7f7CB2MICVhJLF64Bm8oioCqx5dtsMJtXwE1i45tZ7BDbFCSO Tf3KCmJzCrhLnHxzjxnEFgKqWdGzjA2iV0Di2+RDQL0cQPWyEpsOgN0jIXCbTWLPjEdQ70hK HFxxg2UCo/ACRoZVjKKpBckFxUnpuUZ6xYm5xaV56XrJ+bmbGIEBefrfM+kdjKsaLA4xCnAw KvHwfhA6FSDEmlhWXJl7iFGCg1lJhFfyCFCINyWxsiq1KD++qDQntfgQow/QJROZpUST84HR klcSb2hsYm5qbGppZGRmaopDWEmct9kjJUBIID2xJDU7NbUgtQhmHBMHp1QDo0T3n7M7gq79 X+en7HnRMGr2zZWi06RYJ/PJPXumbv9y67+OAEFnhZCJxmZZm5on/X73wPi+/NXQRzt+tP2O 0O3/tn5GvtoWc9aZi7VmyT0MT834Y2Hqyvzj84nPFy++ikzjbeqNY10zr/nEklu60R6nexrk c9J+r7/43FrQcNb6HL8yLYmjnkosxRmJhlrMRcWJAOCJbS51AgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprIIsWRmVeSWpSXmKPExsVy+t9jQV1T4dMBBr9falk8XH+TxWLK4S8s Dkwed67tYQtgjGpgtMlITUxJLVJIzUvOT8nMS7dV8g6Od443NTMw1DW0tDBXUshLzE21VXLx CdB1y8wBmq2kUJaYUwoUCkgsLlbSt8M0ITTETdcCpjFC1zckCK7HyAANJKxhzFjTMI+14JtM xe5jn5gbGP+LdzFyckgImEgsfbuGBcIWk7hwbz1bFyMXh5DAdEaJ6Qd3MUM4E5kkejcsYgKp YhMwkth6chojiC0iICHxq/8qmM0sECPxev8PNhBbWMBKYulCiKksAqoSW77NBrN5BdwkNr6Z xQ6xTUHi2NSvrCA2p4C7xMk395hBbCGgmhU9y9gmMPIuYGRYxSiaWpBcUJyUnmukV5yYW1ya l66XnJ+7iREc7s+kdzCuarA4xCjAwajEw/tB6FSAEGtiWXFl7iFGCQ5mJRFeySNAId6UxMqq 1KL8+KLSnNTiQ4w+QFdNZJYSTc4HxmJeSbyhsYm5qbGppYmFiZklDmElcd5mj5QAIYH0xJLU 7NTUgtQimHFMHJxSDYyO+VLXbFk+tVQ3WW6/I8zOudWfffKfeTI/55ydUPLR7vHBYM3yTbxP f4SmOzd4zr3N3ub5PD2AwbYtZrbARZm/v+Pn3Wfq4Ate+i/uQYSGQ8hxg8DG1dEnWbfz80zq vvCas/ZB45VeW/aTiz4JfTmufmriMa6au5s79i4rWK+dF/pMeN7yBeVKLMUZiYZazEXFiQCx igOapAIAAA== X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQl0+k4Oqw8k+yRrMWsRgijnOfQJ5p5LFs3s5vsY+Bl082LvcIjRvnGL3jDVINL7PTXWLafh Api is added to decode peripheral id based on the interrupt number of the peripheral. Signed-off-by: Rajeshwari Shinde Acked-by; Simon Glass --- Changes in V1: -Rebased on latest u-boot-samsung arch/arm/cpu/armv7/exynos/pinmux.c | 28 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/periph.h | 31 ++++++++++++++++------------ arch/arm/include/asm/arch-exynos/pinmux.h | 8 +++++++ 3 files changed, 54 insertions(+), 13 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index f02f441..f9f6911 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -22,6 +22,7 @@ */ #include +#include #include #include #include @@ -396,3 +397,30 @@ int exynos_pinmux_config(int peripheral, int flags) return -1; } } + +#ifdef CONFIG_OF_CONTROL +static int exynos5_pinmux_decode_periph_id(const void *blob, int node) +{ + int err; + u32 cell[3]; + + err = fdtdec_get_int_array(blob, node, "interrupts", cell, + ARRAY_SIZE(cell)); + if (err) + return PERIPH_ID_NONE; + + if ((131 > cell[1]) || (cell[1] < 31)) + return cell[1]; + + debug(" invalid peripheral id\n"); + return PERIPH_ID_NONE; +} + +int pinmux_decode_periph_id(const void *blob, int node) +{ + if (cpu_is_exynos5()) + return exynos5_pinmux_decode_periph_id(blob, node); + else + return PERIPH_ID_NONE; +} +#endif diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h index 13abd2d..783b77c 100644 --- a/arch/arm/include/asm/arch-exynos/periph.h +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -25,12 +25,17 @@ #define __ASM_ARM_ARCH_PERIPH_H /* - * Peripherals requiring clock/pinmux configuration. List will + * Peripherals requiring pinmux configuration0. List will * grow with support for more devices getting added. + * Numbering based on interrupt table. * */ enum periph_id { - PERIPH_ID_I2C0, + PERIPH_ID_UART0 = 51, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + PERIPH_ID_UART3, + PERIPH_ID_I2C0 = 56, PERIPH_ID_I2C1, PERIPH_ID_I2C2, PERIPH_ID_I2C3, @@ -38,22 +43,22 @@ enum periph_id { PERIPH_ID_I2C5, PERIPH_ID_I2C6, PERIPH_ID_I2C7, - PERIPH_ID_I2S1, - PERIPH_ID_SDMMC0, + PERIPH_ID_SPI0 = 68, + PERIPH_ID_SPI1, + PERIPH_ID_SPI2, + PERIPH_ID_SDMMC0 = 75, PERIPH_ID_SDMMC1, PERIPH_ID_SDMMC2, PERIPH_ID_SDMMC3, - PERIPH_ID_SDMMC4, - PERIPH_ID_SROMC, - PERIPH_ID_SPI0, - PERIPH_ID_SPI1, - PERIPH_ID_SPI2, + PERIPH_ID_I2S1 = 99, + +/* Since following peripherals do not have shared peripheral interrupts (SPIs) + * they are numbered arbitiraly after the maximum SPIs Exynos has (128) + */ + PERIPH_ID_SROMC = 128, PERIPH_ID_SPI3, PERIPH_ID_SPI4, - PERIPH_ID_UART0, - PERIPH_ID_UART1, - PERIPH_ID_UART2, - PERIPH_ID_UART3, + PERIPH_ID_SDMMC4, PERIPH_ID_COUNT, PERIPH_ID_NONE = -1, diff --git a/arch/arm/include/asm/arch-exynos/pinmux.h b/arch/arm/include/asm/arch-exynos/pinmux.h index 10ea736..00cbb0d 100644 --- a/arch/arm/include/asm/arch-exynos/pinmux.h +++ b/arch/arm/include/asm/arch-exynos/pinmux.h @@ -55,4 +55,12 @@ enum { */ int exynos_pinmux_config(int peripheral, int flags); +/** + * Decode the peripheral id using the interrpt numbers. + * + * @param blob Device tree blbo + * @param node FDT I2C node to find + * @return peripheral id if ok, PERIPH_ID_NONE on error + */ +int pinmux_decode_periph_id(const void *blob, int node); #endif