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[203.254.224.24]) by mx.google.com with ESMTP id d7si12979490paw.269.2012.12.17.02.57.54; Mon, 17 Dec 2012 02:57:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of amarendra.xt@samsung.com designates 203.254.224.24 as permitted sender) client-ip=203.254.224.24; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of amarendra.xt@samsung.com designates 203.254.224.24 as permitted sender) smtp.mail=amarendra.xt@samsung.com Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MF600ADA92QUC30@mailout1.samsung.com>; Mon, 17 Dec 2012 19:57:30 +0900 (KST) Received: from epcpdlpp23 ( [172.20.52.123]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 1C.AA.12699.A9AFEC05; Mon, 17 Dec 2012 19:57:30 +0900 (KST) X-AuditID: cbfee61b-b7f616d00000319b-01-50cefa9a579b Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id CB.AA.12699.A9AFEC05; Mon, 17 Dec 2012 19:57:30 +0900 (KST) Received: from localhost.localdomain ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MF600FNU92TR670@mmp2.samsung.com>; Mon, 17 Dec 2012 19:57:30 +0900 (KST) From: Amar To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, afleming@gmail.com, jh80.chung@samsung.com Subject: [PATCH 5/9] EXYNOS5: DWMMC: API to set mmc clock divisor Date: Mon, 17 Dec 2012 16:49:32 +0530 Message-id: <1355743176-12305-6-git-send-email-amarendra.xt@samsung.com> X-Mailer: git-send-email 1.7.0.4 In-reply-to: <1355743176-12305-1-git-send-email-amarendra.xt@samsung.com> References: <1355743176-12305-1-git-send-email-amarendra.xt@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrILMWRmVeSWpSXmKPExsWyRsSkWnfWr3MBBh+WyVs8XH+TxWLK4S8s Dkwed67tYQtgjOKySUnNySxLLdK3S+DK+Pn0DmPBGtGKvTdPMTcwbhfsYuTkkBAwkZj69RQ7 hC0mceHeerYuRi4OIYFZjBJ9i2exwBRtfruRGSIxnVFi0bEDTCAJIYF2Jokbt2W6GDk42ARU JX4ttgcJiwhISPzqv8oIUs8s0MEosWPiZkaQhLCAo8TCXYuZQWwWoPotZ2+zgti8Ah4Sm3a1 QS1TkGhddgjsIk4BT4nPux+yQOzykNizazpUr4DEt8mHWED2SgjISmw6AHabhMB9NolXXasY IeZIShxccYNlAqPwAkaGVYyiqQXJBcVJ6blGesWJucWleel6yfm5mxiB4Xj63zPpHYyrGiwO MQpwMCrx8BqmngsQYk0sK67MPcQowcGsJMIr/QYoxJuSWFmVWpQfX1Sak1p8iNEH6JKJzFKi yfnAWMkriTc0NjE3NTa1NDIyMzXFIawkztvskRIgJJCeWJKanZpakFoEM46Jg1OqgXFpXWTX grV2G+zbGOvZjNakrqvMXFPe+7k70cJKbO66+hzBPbN/Oa6QmatRW+3ywvqZyH1T/vYFjKsr Pm+zNmoom71lSaVb/0yNRwI/1rd9mcWnfXjlFvatqjaMh113ijGU/wjdcfiHjOguw6tXHHXU s99Eu19Qvxy786HCEx391ASNtEN79ZVYijMSDbWYi4oTAQAhPKF0AgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprAIsWRmVeSWpSXmKPExsVy+t9jQd1Zv84FGPSvlbR4uP4mi8WUw19Y HJg87lzbwxbAGNXAaJORmpiSWqSQmpecn5KZl26r5B0c7xxvamZgqGtoaWGupJCXmJtqq+Ti E6DrlpkDNFtJoSwxpxQoFJBYXKykb4dpQmiIm64FTGOErm9IEFyPkQEaSFjDmPHz6R3GgjWi FXtvnmJuYNwu2MXIySEhYCKx+e1GZghbTOLCvfVsXYxcHEIC0xklFh07wASSEBJoZ5K4cVum i5GDg01AVeLXYnuQsIiAhMSv/quMIPXMAh2MEjsmbmYESQgLOEos3LUYbCgLUP2Ws7dZQWxe AQ+JTbvaWCCWKUi0LjvEDmJzCnhKfN79kAVil4fEnl3TmScw8i5gZFjFKJpakFxQnJSea6RX nJhbXJqXrpecn7uJERzsz6R3MK5qsDjEKMDBqMTDa5h6LkCINbGsuDL3EKMEB7OSCK/0G6AQ b0piZVVqUX58UWlOavEhRh+gqyYyS4km5wMjMa8k3tDYxNzU2NTSxMLEzBKHsJI4b7NHSoCQ QHpiSWp2ampBahHMOCYOTqkGxi2FmqEWoenhPFf3WnbbsNU6rtkSOfmVInPBoyDR3rTtoeEz s4NFvz+es9HxVd9cbuPrc25n5r0pnSA7d8mWpd01SpIrt0Tc3lWRwsu5bE3hIS1DThvOHzmp +xJ+P5kzWbzCPuOFr6MHcxNbcriL5rRduW3LViikOLo2mT19f7PiR2uctly9EktxRqKhFnNR cSIAlihkfqMCAAA= X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQlppMntT3H9AlXAwg3mbDPXY9GYXf4vtm4OqXQHpMUuaTYFLf1/asIjcEwVAj9dfvzrkWNg This API computes the divisor value based on MPLL clock and writes it into the FSYS1 register. Signed-off-by: Amar --- arch/arm/cpu/armv7/exynos/clock.c | 39 ++++++++++++++++++++++++++++++- arch/arm/include/asm/arch-exynos/clk.h | 1 + 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 731bbff..6517296 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -379,7 +379,7 @@ static unsigned long exynos4_get_mmc_clk(int dev_index) (struct exynos4_clock *)samsung_get_base_clock(); unsigned long uclk, sclk; unsigned int sel, ratio, pre_ratio; - int shift; + int shift = 0; sel = readl(&clk->src_fsys); sel = (sel >> (dev_index << 2)) & 0xf; @@ -428,7 +428,7 @@ static unsigned long exynos5_get_mmc_clk(int dev_index) (struct exynos5_clock *)samsung_get_base_clock(); unsigned long uclk, sclk; unsigned int sel, ratio, pre_ratio; - int shift; + int shift = 0; sel = readl(&clk->src_fsys); sel = (sel >> (dev_index << 2)) & 0xf; @@ -526,6 +526,41 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) writel(val, addr); } +/* exynos5: set the mmc clock div ratio in fsys1 */ +int exynos5_mmc_set_clk_div(int dev_index) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned int addr; + unsigned int clock; + unsigned int tmp; + unsigned int i; + + /* get mpll clock */ + clock = get_pll_clk(MPLL) / 1000000; + + /* + * CLK_DIV_FSYS1 + * MMC0_PRE_RATIO [15:8], MMC0_RATIO [3:0] + * CLK_DIV_FSYS2 + * MMC2_PRE_RATIO [15:8], MMC2_RATIO [3:0] + */ + if (dev_index < 2) { + addr = (unsigned int)&clk->div_fsys1; + } else { + addr = (unsigned int)&clk->div_fsys2; + } + + tmp = readl(addr) & ~FSYS1_MMC0_DIV_MASK; + for (i = 0; i <= 0xf; i++) { + if ((clock / (i + 1)) <= 400) { + writel(tmp | i << 0, addr); + break; + } + } + return 0; +} + /* get_lcd_clk: return lcd clock frequency */ static unsigned long exynos4_get_lcd_clk(void) { diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index ff155d8..b0ecdd4 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -36,6 +36,7 @@ unsigned long get_pwm_clk(void); unsigned long get_uart_clk(int dev_index); unsigned long get_mmc_clk(int deV_index); void set_mmc_clk(int dev_index, unsigned int div); +int exynos5_mmc_set_clk_div(int dev_index); unsigned long get_lcd_clk(void); void set_lcd_clk(void); void set_mipi_clk(void);