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[209.132.180.67]) by mx.google.com with ESMTP id 1-v6si22177672plz.101.2018.05.24.22.41.16; Thu, 24 May 2018 22:41:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cPgiKd02; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935872AbeEYFlO (ORCPT + 30 others); Fri, 25 May 2018 01:41:14 -0400 Received: from mail-pl0-f66.google.com ([209.85.160.66]:33012 "EHLO mail-pl0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964969AbeEYFkp (ORCPT ); Fri, 25 May 2018 01:40:45 -0400 Received: by mail-pl0-f66.google.com with SMTP id n10-v6so2465922plp.0 for ; Thu, 24 May 2018 22:40:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=R7AXhcykQKSlSx5Ebfq4WSBNV+A2kPnqRSDfYr9KGp0=; b=cPgiKd02y50IKgzkkBC0yh15c8el4N1As1RE3gi7AWPk6Tcme1ScYa5/hwjGZQJ1Md 5AL3E7OCZ08bmCCc00C7dvApnizXed5zN7StPLkUaAyotiiaU2liBFu1PR+Srjm+X56d ZvQag95ViOO/jtZ5UDZdssPrDqMG56OGdhMdM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=R7AXhcykQKSlSx5Ebfq4WSBNV+A2kPnqRSDfYr9KGp0=; b=P/NsMVK6TxTT10+nvTH/dXhzalSGF28FGWcndhyAQSaQcuUWoz3KfoeINEkcJGUkoU O91V7wdtdKLb4ZivXLuiIqn9j/ioYwa5gVR1QPLIDzGWItjqWV6vBus0pQilreqCht6f BMKCcCV9MmZAkp72t4bwhw7Au7AO0kq5uAedPKkAl2rL+CiZZ9W7taGpHAKXDjLFg7Z6 MECyOQ3NrAVBjYT//cqywGmCxsYkC2RMM4oBxiYo0CSOhK9BFhBEQ9540w6pE8QtQ+4d SOt+e5zliZP5fK7LVHAD/PwwCdjYHnGYCY9+BLDn3DY/rtiNVVQBsJM/bAxI4aRXNUgg TB4A== X-Gm-Message-State: ALKqPwegiH5QQRizXkAYcfBW1jZ024dtWZ+3ShK2lzLKXapCqHKiaM/u 4BHyDBIZqoqFaUf+Q1oqHetLNg== X-Received: by 2002:a17:902:4303:: with SMTP id i3-v6mr1147597pld.394.1527226844899; Thu, 24 May 2018 22:40:44 -0700 (PDT) Received: from localhost ([122.172.112.176]) by smtp.gmail.com with ESMTPSA id t14-v6sm49892747pfh.109.2018.05.24.22.40.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 May 2018 22:40:44 -0700 (PDT) From: Viresh Kumar To: arm@kernel.org, Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Heiko Stuebner Cc: Viresh Kumar , Vincent Guittot , ionela.voinescu@arm.com, Daniel Lezcano , chris.redpath@arm.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/6] arm64: dts: rockchip: Add missing cooling device properties for CPUs Date: Fri, 25 May 2018 11:10:05 +0530 Message-Id: X-Mailer: git-send-email 2.15.0.194.g9af6a3dea062 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Do minor rearrangement as well to keep ordering consistent. Signed-off-by: Viresh Kumar --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 3 +++ arch/arm64/boot/dts/rockchip/rk3368.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 8 ++++++-- 3 files changed, 21 insertions(+), 2 deletions(-) -- 2.15.0.194.g9af6a3dea062 diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index b8e9da15e00c..902a0907ad34 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -89,6 +89,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x1>; clocks = <&cru ARMCLK>; + #cooling-cells = <2>; dynamic-power-coefficient = <120>; enable-method = "psci"; next-level-cache = <&l2>; @@ -100,6 +101,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x2>; clocks = <&cru ARMCLK>; + #cooling-cells = <2>; dynamic-power-coefficient = <120>; enable-method = "psci"; next-level-cache = <&l2>; @@ -111,6 +113,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x3>; clocks = <&cru ARMCLK>; + #cooling-cells = <2>; dynamic-power-coefficient = <120>; enable-method = "psci"; next-level-cache = <&l2>; diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index ad91ced78649..c32f2a551a1f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -122,6 +122,8 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; + + #cooling-cells = <2>; /* min followed by max */ }; cpu_l2: cpu@2 { @@ -129,6 +131,8 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; + + #cooling-cells = <2>; /* min followed by max */ }; cpu_l3: cpu@3 { @@ -136,6 +140,8 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; + + #cooling-cells = <2>; /* min followed by max */ }; cpu_b0: cpu@100 { @@ -152,6 +158,8 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x101>; enable-method = "psci"; + + #cooling-cells = <2>; /* min followed by max */ }; cpu_b2: cpu@102 { @@ -159,6 +167,8 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x102>; enable-method = "psci"; + + #cooling-cells = <2>; /* min followed by max */ }; cpu_b3: cpu@103 { @@ -166,6 +176,8 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x103>; enable-method = "psci"; + + #cooling-cells = <2>; /* min followed by max */ }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index e0040b648f43..da935383a8f2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -108,8 +108,8 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; - #cooling-cells = <2>; /* min followed by max */ clocks = <&cru ARMCLKL>; + #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; }; @@ -119,6 +119,7 @@ reg = <0x0 0x1>; enable-method = "psci"; clocks = <&cru ARMCLKL>; + #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; }; @@ -128,6 +129,7 @@ reg = <0x0 0x2>; enable-method = "psci"; clocks = <&cru ARMCLKL>; + #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; }; @@ -137,6 +139,7 @@ reg = <0x0 0x3>; enable-method = "psci"; clocks = <&cru ARMCLKL>; + #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; }; @@ -145,8 +148,8 @@ compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; - #cooling-cells = <2>; /* min followed by max */ clocks = <&cru ARMCLKB>; + #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <436>; }; @@ -156,6 +159,7 @@ reg = <0x0 0x101>; enable-method = "psci"; clocks = <&cru ARMCLKB>; + #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <436>; }; };