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[209.132.180.67]) by mx.google.com with ESMTP id f62-v6si15290127pgc.651.2018.05.24.22.41.31; Thu, 24 May 2018 22:41:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JdGna9Nr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753343AbeEYFl3 (ORCPT + 30 others); Fri, 25 May 2018 01:41:29 -0400 Received: from mail-pf0-f194.google.com ([209.85.192.194]:40305 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964875AbeEYFki (ORCPT ); Fri, 25 May 2018 01:40:38 -0400 Received: by mail-pf0-f194.google.com with SMTP id f189-v6so2021200pfa.7 for ; Thu, 24 May 2018 22:40:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=oRUuLH7flE4Fvg206nWF7csPgcPeAXkHjdKNYq5dMh8=; b=JdGna9NrumQ0C3jprwSOW4n+BGRLVsJM2q8xYQ+ii88CadkPC2krp2SGJz+AryW7VN dzARt55d59RtyjEmZ4AToTi3SEBg3ONe32+cZTW97hVDC3UpfLw7dr1hAUUV1VjNtjX5 nkwqCDGE0+6OVUQ7yCmzPRK7lyThPvfEBX5ZY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=oRUuLH7flE4Fvg206nWF7csPgcPeAXkHjdKNYq5dMh8=; b=ntDBO8Pwshf8AXQwRH5q4blCD1iCfnBuzhFtskdib/DKq13mgc2Zqc8i6bdZ5PpNzz un0cQbjdzQjs9TuAQ4tkqCIfQYOR123QClbU1K4GqhNSeVta6ggN52jb2ZvTwQS5z/ak hDtA0PT3hKzT8Cg5AWdr3KaWPap11832ppVb7d0lx3QvT3kf4NN7KjeB4NFlF5SpDwz5 Apj0tJl9f/Vi/1uasmYduim8z8jYUezY4xERrsdHxtPGcS5J8MxMQOsGJbyq8TFCIo61 T1P89ombFRQLwIUZXwuQZeaAzxf85jJMsNceTcNqrvnK9v5AaWojjxrVDOBSUj7V3uK4 q0vg== X-Gm-Message-State: ALKqPweWamy4M9qP2wpIHRZEhtLN1RrnBIKV2/8/GipdOtY6paqSx5Ox yNkbI/5tk5ypHC1Mv3Tm5V2aMg== X-Received: by 2002:a63:69c3:: with SMTP id e186-v6mr832546pgc.353.1527226838329; Thu, 24 May 2018 22:40:38 -0700 (PDT) Received: from localhost ([122.172.112.176]) by smtp.gmail.com with ESMTPSA id c83-v6sm45342586pfc.111.2018.05.24.22.40.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 May 2018 22:40:37 -0700 (PDT) From: Viresh Kumar To: arm@kernel.org, Wei Xu , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon Cc: Viresh Kumar , Vincent Guittot , ionela.voinescu@arm.com, Daniel Lezcano , chris.redpath@arm.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/6] arm64: dts: hisilicon: Add missing cooling device properties for CPUs Date: Fri, 25 May 2018 11:10:03 +0530 Message-Id: <0754957a2c3842cf4e36fa27231d327fd8d6d499.1527225682.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.15.0.194.g9af6a3dea062 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Do minor rearrangement as well to keep ordering consistent. Signed-off-by: Viresh Kumar --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) -- 2.15.0.194.g9af6a3dea062 diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 586b281cd531..247024df714f 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -88,8 +88,8 @@ next-level-cache = <&CLUSTER0_L2>; clocks = <&stub_clock 0>; operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <311>; }; @@ -101,6 +101,8 @@ next-level-cache = <&CLUSTER0_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <311>; }; cpu2: cpu@2 { @@ -111,6 +113,8 @@ next-level-cache = <&CLUSTER0_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <311>; }; cpu3: cpu@3 { @@ -121,6 +125,8 @@ next-level-cache = <&CLUSTER0_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <311>; }; cpu4: cpu@100 { @@ -131,6 +137,8 @@ next-level-cache = <&CLUSTER1_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <311>; }; cpu5: cpu@101 { @@ -141,6 +149,8 @@ next-level-cache = <&CLUSTER1_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <311>; }; cpu6: cpu@102 { @@ -151,6 +161,8 @@ next-level-cache = <&CLUSTER1_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <311>; }; cpu7: cpu@103 { @@ -161,6 +173,8 @@ next-level-cache = <&CLUSTER1_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <311>; }; CLUSTER0_L2: l2-cache0 {