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[209.132.180.67]) by mx.google.com with ESMTP id j11-v6si739293pgn.129.2018.05.25.03.33.09; Fri, 25 May 2018 03:33:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UzlZbYrM; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966453AbeEYKdH (ORCPT + 30 others); Fri, 25 May 2018 06:33:07 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:45596 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S966415AbeEYKdD (ORCPT ); Fri, 25 May 2018 06:33:03 -0400 Received: by mail-pf0-f195.google.com with SMTP id c10-v6so2389380pfi.12 for ; Fri, 25 May 2018 03:33:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=MHvuztnncuTm520CThQq85XP/1Zrea3H9cY3BfMcbf8=; b=UzlZbYrMaSM8EbFgKbPqwEx9zJ/YWJ+abi5h1zRFwCE0Pwfnqg3e3zney5BWfASr9t tzfR3OA6pwVnekxc0FU1ayz9K4eFQO0Q9sTp9Or08nOgKkgWRPPNUpupQzuRD42Pid5Q W0FPdsQHHL9/wIRstZlSieE0XakHBX7mQe/0w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=MHvuztnncuTm520CThQq85XP/1Zrea3H9cY3BfMcbf8=; b=eUWd36RKMOQGtc87wk/6hnKhgv5G7L3HtTNkHX9w5WGBdJHyFZXf5LgIyoL7s4ZgSW m3mmP+DGdqP24YZwxJqmXOM73J91ZVNUbkIw99UTOak0i5k9G8gzGLj3L+AZ0dq4D5av YKsjW8LCoK5PJcvv9FDV/0ODL+kL4P0xw+X7cL/qJqid/5Mr5EE7fbv29tAWxHjWRKvA UeV5u2m+PuNUelPVGClxM6dkzyu+YCNTc0SqU4N7xmoorYFQTj8hHP9KVCAwsf4nnBGh 4n0YpMuq7+tVrB6W0G0VKia4BJ3rCNKU82l1zeFbM3Y0+AZd5PghDLiEH/65eRiMxNNF uVyA== X-Gm-Message-State: ALKqPweDItO8pb4Ajo5QxJcNPLfdJ8OMScpJCRvCYeBGjKKL9bgKStWL Ay3YIELSR4fRkNlczsSarxkX/g== X-Received: by 2002:aa7:8354:: with SMTP id z20-v6mr1981456pfm.166.1527244382484; Fri, 25 May 2018 03:33:02 -0700 (PDT) Received: from localhost ([122.172.112.176]) by smtp.gmail.com with ESMTPSA id x2-v6sm55438900pfk.113.2018.05.25.03.33.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 25 May 2018 03:33:01 -0700 (PDT) From: Viresh Kumar To: arm@kernel.org, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Mark Rutland Cc: Viresh Kumar , Vincent Guittot , ionela.voinescu@arm.com, Daniel Lezcano , chris.redpath@arm.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 15/15] arm: dts: imx: Add missing OPP properties for CPUs Date: Fri, 25 May 2018 16:02:01 +0530 Message-Id: <264124e14b966a1bbc07c364fbd89fc55aa765e6.1527244201.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.15.0.194.g9af6a3dea062 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The OPP properties, like "operating-points", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can create an OPP table. Add such missing properties. Fix other missing properties (like clocks, supply, clock latency) as well to make it all work. Signed-off-by: Viresh Kumar --- arch/arm/boot/dts/imx6dl.dtsi | 23 ++++++++++ arch/arm/boot/dts/imx6q-cm-fx6.dts | 66 +++++++++++++++++++++++++++++ arch/arm/boot/dts/imx6q.dtsi | 87 ++++++++++++++++++++++++++++++++++++-- arch/arm/boot/dts/imx7d.dtsi | 5 +++ 4 files changed, 178 insertions(+), 3 deletions(-) -- 2.15.0.194.g9af6a3dea062 diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index b384913c34dd..cc8ffc42d128 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -50,6 +50,29 @@ device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1150000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; }; diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts index 65ef4cacbc71..18ae4f3be6e3 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts @@ -187,6 +187,72 @@ >; }; +&cpu1 { + /* + * Although the imx6q fuse indicates that 1.2GHz operation is possible, + * the module behaves unstable at this frequency. Hence, remove the + * 1.2GHz operation point here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; +}; + +&cpu2 { + /* + * Although the imx6q fuse indicates that 1.2GHz operation is possible, + * the module behaves unstable at this frequency. Hence, remove the + * 1.2GHz operation point here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; +}; + +&cpu3 { + /* + * Although the imx6q fuse indicates that 1.2GHz operation is possible, + * the module behaves unstable at this frequency. Hence, remove the + * 1.2GHz operation point here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; +}; + &ecspi1 { cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 70483ce72ba6..78b89bb1bfed 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -50,25 +50,106 @@ soc-supply = <®_soc>; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; - cpu@2 { + cpu2: cpu@2 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <2>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; - cpu@3 { + cpu3: cpu@3 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <3>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; }; diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 4c9877ec29f2..5434a8aa5602 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -21,6 +21,11 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + operating-points = < + /* KHz uV */ + 996000 1075000 + 792000 975000 + >; clock-frequency = <996000000>; }; };