diff mbox series

[2/8] drm/amdgpu: fix 32-bit build warning

Message ID 20180525155030.3667352-2-arnd@arndb.de
State Accepted
Commit ebe1d22b57b86b6739f2739b5a0f52435596d84d
Headers show
Series [1/8] drm/sun4i: mark PM functions as __maybe_unused | expand

Commit Message

Arnd Bergmann May 25, 2018, 3:50 p.m. UTC
Casting a pointer to a 64-bit type causes a warning on 32-bit targets:

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:473:24: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
          lower_32_bits((uint64_t)wptr));
                        ^
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1701:53: note: in definition of macro 'WREG32'
 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
                                                     ^
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:473:10: note: in expansion of macro 'lower_32_bits'
          lower_32_bits((uint64_t)wptr));
          ^~~~~~~~~~~~~

The correct method is to cast to 'uintptr_t'.

Fixes: d5a114a6c5f7 ("drm/amdgpu: Add GFXv9 kfd2kgd interface functions")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

-- 
2.9.0

Comments

Oded Gabbay May 28, 2018, 9:47 a.m. UTC | #1
On Fri, May 25, 2018 at 6:50 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> Casting a pointer to a 64-bit type causes a warning on 32-bit targets:

>

> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:473:24: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]

>           lower_32_bits((uint64_t)wptr));

>                         ^

> drivers/gpu/drm/amd/amdgpu/amdgpu.h:1701:53: note: in definition of macro 'WREG32'

>  #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)

>                                                      ^

> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:473:10: note: in expansion of macro 'lower_32_bits'

>           lower_32_bits((uint64_t)wptr));

>           ^~~~~~~~~~~~~

>

> The correct method is to cast to 'uintptr_t'.

>

> Fixes: d5a114a6c5f7 ("drm/amdgpu: Add GFXv9 kfd2kgd interface functions")

> Signed-off-by: Arnd Bergmann <arnd@arndb.de>

> ---

>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 4 ++--

>  1 file changed, 2 insertions(+), 2 deletions(-)

>

> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

> index 8f37991df61b..f0c0d3953f69 100644

> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

> @@ -470,9 +470,9 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,

>                 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),

>                        upper_32_bits(guessed_wptr));

>                 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),

> -                      lower_32_bits((uint64_t)wptr));

> +                      lower_32_bits((uintptr_t)wptr));

>                 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),

> -                      upper_32_bits((uint64_t)wptr));

> +                      upper_32_bits((uintptr_t)wptr));

>                 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),

>                        get_queue_mask(adev, pipe_id, queue_id));

>         }

> --

> 2.9.0

>


There is a change scheduled for the next merge window that will cause
this file to not build anymore on 32-bit targets (because the amdkfd
driver is not supported on 32 bit targets).

Never the less I'm taking the patch for good measure.

This patch is:
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
index 8f37991df61b..f0c0d3953f69 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
@@ -470,9 +470,9 @@  static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
 		       upper_32_bits(guessed_wptr));
 		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
-		       lower_32_bits((uint64_t)wptr));
+		       lower_32_bits((uintptr_t)wptr));
 		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
-		       upper_32_bits((uint64_t)wptr));
+		       upper_32_bits((uintptr_t)wptr));
 		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),
 		       get_queue_mask(adev, pipe_id, queue_id));
 	}