[edk2,edk2-platforms,2/3] Silicon/Socionext/SynQuacer/Stage2Tables: add north SMMU level 3 table

Message ID 20180530181929.5066-3-ard.biesheuvel@linaro.org
State New
Headers show
Series
  • More SynQuacer updates
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Commit Message

Ard Biesheuvel May 30, 2018, 6:19 p.m.
Extend the static stage 2 page tables with a set of level 3 tables that
describe the ECAM space in a manner that allows the north SMMU to be used
to make the ECAM space appear sane to the CPUs.

It is up to the secure firmware to manipulate the north SMMU page tables
so that the level 2 block entries corresponding with busses #0 .. #1 in
the respective config spaces of PCI0 and PCI1 are replaced with table
entries pointing to the level 3 tables added by this patch.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

---
 Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S | 35 +++++++++++++++-----
 1 file changed, 26 insertions(+), 9 deletions(-)

-- 
2.17.0

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Comments

Leif Lindholm May 31, 2018, 9:14 a.m. | #1
On Wed, May 30, 2018 at 08:19:28PM +0200, Ard Biesheuvel wrote:
> Extend the static stage 2 page tables with a set of level 3 tables that

> describe the ECAM space in a manner that allows the north SMMU to be used

> to make the ECAM space appear sane to the CPUs.

> 

> It is up to the secure firmware to manipulate the north SMMU page tables


s/secure/EL3/ or s/secure/Secure/?

With either of those:
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>



> so that the level 2 block entries corresponding with busses #0 .. #1 in

> the respective config spaces of PCI0 and PCI1 are replaced with table

> entries pointing to the level 3 tables added by this patch.

> 

> Contributed-under: TianoCore Contribution Agreement 1.1

> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

> ---

>  Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S | 35 +++++++++++++++-----

>  1 file changed, 26 insertions(+), 9 deletions(-)

> 

> diff --git a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S

> index 313ef3c56abc..af55f27bca47 100644

> --- a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S

> +++ b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S

> @@ -20,15 +20,17 @@

>   *   the SoC.

>   */

>  

> -#define TT_S2_CONT_SHIFT          52

> -#define TT_S2_AF                  (0x1 << 10)

> -#define TT_S2_SH_NON_SHAREABLE    (0x0 << 8)

> -#define TT_S2_AP_RW               (0x3 << 6)

> -#define TT_S2_MEMATTR_DEVICE_nGRE (0x2 << 2)

> -#define TT_S2_MEMATTR_MEMORY_WB   (0xf << 2)

> -#define TT_S2_TABLE               (0x3 << 0)

> -#define TT_S2_L3_PAGE             (0x1 << 1)

> -#define TT_S2_VALID               (0x1 << 0)

> +#define TT_S2_CONT_SHIFT            52

> +#define TT_S2_AF                    (0x1 << 10)

> +#define TT_S2_SH_NON_SHAREABLE      (0x0 << 8)

> +#define TT_S2_AP_RO                 (0x1 << 6)

> +#define TT_S2_AP_RW                 (0x3 << 6)

> +#define TT_S2_MEMATTR_DEVICE_nGRE   (0x2 << 2)

> +#define TT_S2_MEMATTR_DEVICE_nGnRE  (0x1 << 2)

> +#define TT_S2_MEMATTR_MEMORY_WB     (0xf << 2)

> +#define TT_S2_TABLE                 (0x3 << 0)

> +#define TT_S2_L3_PAGE               (0x1 << 1)

> +#define TT_S2_VALID                 (0x1 << 0)

>  

>    .altmacro

>    .macro    for, start, count, do, arg2, arg3, arg4

> @@ -58,6 +60,12 @@

>              TT_S2_L3_PAGE | TT_S2_VALID | (\cont << TT_S2_CONT_SHIFT)

>    .endm

>  

> +  .macro    smmu_l3_entry, base, offset=0, ignore=0

> +  .quad     ((\base << 12) + \offset) | TT_S2_AF | TT_S2_AP_RO | \

> +            TT_S2_SH_NON_SHAREABLE | TT_S2_MEMATTR_DEVICE_nGnRE | \

> +            TT_S2_L3_PAGE | TT_S2_VALID

> +  .endm

> +

>    .section  ".rodata", "a", %progbits

>    /* level 1 */

>    s2_mem_entry  0      /* 0x0000_0000 - 0x3fff_ffff */

> @@ -86,3 +94,12 @@

>  3:for     0,   8, s2_l3_entry, 0x70000000

>    for     0,   8, s2_l3_entry, 0x70010000  /* hide device #1 */

>    for     0, 496, s2_l3_entry, 0x70010000, 1

> +

> +  /* level 3 for north SMMU */

> +  .org    0x6000

> +  for     0,   8, smmu_l3_entry, 0xc00060000000

> +  for     0,   8, smmu_l3_entry, 0xc00060010000  /* hide device #1 */

> +  for     0, 496, smmu_l3_entry, 0xc00060010000

> +  for     0,   8, smmu_l3_entry, 0x800070000000

> +  for     0,   8, smmu_l3_entry, 0x800070010000  /* hide device #1 */

> +  for     0, 496, smmu_l3_entry, 0x800070010000

> -- 

> 2.17.0

> 

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Ard Biesheuvel June 1, 2018, 10:18 a.m. | #2
On 31 May 2018 at 11:14, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> On Wed, May 30, 2018 at 08:19:28PM +0200, Ard Biesheuvel wrote:

>> Extend the static stage 2 page tables with a set of level 3 tables that

>> describe the ECAM space in a manner that allows the north SMMU to be used

>> to make the ECAM space appear sane to the CPUs.

>>

>> It is up to the secure firmware to manipulate the north SMMU page tables

>

> s/secure/EL3/ or s/secure/Secure/?

>

> With either of those:

> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

>


Thanks

Pushed as ba32985a0631

>

>> so that the level 2 block entries corresponding with busses #0 .. #1 in

>> the respective config spaces of PCI0 and PCI1 are replaced with table

>> entries pointing to the level 3 tables added by this patch.

>>

>> Contributed-under: TianoCore Contribution Agreement 1.1

>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

>> ---

>>  Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S | 35 +++++++++++++++-----

>>  1 file changed, 26 insertions(+), 9 deletions(-)

>>

>> diff --git a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S

>> index 313ef3c56abc..af55f27bca47 100644

>> --- a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S

>> +++ b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S

>> @@ -20,15 +20,17 @@

>>   *   the SoC.

>>   */

>>

>> -#define TT_S2_CONT_SHIFT          52

>> -#define TT_S2_AF                  (0x1 << 10)

>> -#define TT_S2_SH_NON_SHAREABLE    (0x0 << 8)

>> -#define TT_S2_AP_RW               (0x3 << 6)

>> -#define TT_S2_MEMATTR_DEVICE_nGRE (0x2 << 2)

>> -#define TT_S2_MEMATTR_MEMORY_WB   (0xf << 2)

>> -#define TT_S2_TABLE               (0x3 << 0)

>> -#define TT_S2_L3_PAGE             (0x1 << 1)

>> -#define TT_S2_VALID               (0x1 << 0)

>> +#define TT_S2_CONT_SHIFT            52

>> +#define TT_S2_AF                    (0x1 << 10)

>> +#define TT_S2_SH_NON_SHAREABLE      (0x0 << 8)

>> +#define TT_S2_AP_RO                 (0x1 << 6)

>> +#define TT_S2_AP_RW                 (0x3 << 6)

>> +#define TT_S2_MEMATTR_DEVICE_nGRE   (0x2 << 2)

>> +#define TT_S2_MEMATTR_DEVICE_nGnRE  (0x1 << 2)

>> +#define TT_S2_MEMATTR_MEMORY_WB     (0xf << 2)

>> +#define TT_S2_TABLE                 (0x3 << 0)

>> +#define TT_S2_L3_PAGE               (0x1 << 1)

>> +#define TT_S2_VALID                 (0x1 << 0)

>>

>>    .altmacro

>>    .macro    for, start, count, do, arg2, arg3, arg4

>> @@ -58,6 +60,12 @@

>>              TT_S2_L3_PAGE | TT_S2_VALID | (\cont << TT_S2_CONT_SHIFT)

>>    .endm

>>

>> +  .macro    smmu_l3_entry, base, offset=0, ignore=0

>> +  .quad     ((\base << 12) + \offset) | TT_S2_AF | TT_S2_AP_RO | \

>> +            TT_S2_SH_NON_SHAREABLE | TT_S2_MEMATTR_DEVICE_nGnRE | \

>> +            TT_S2_L3_PAGE | TT_S2_VALID

>> +  .endm

>> +

>>    .section  ".rodata", "a", %progbits

>>    /* level 1 */

>>    s2_mem_entry  0      /* 0x0000_0000 - 0x3fff_ffff */

>> @@ -86,3 +94,12 @@

>>  3:for     0,   8, s2_l3_entry, 0x70000000

>>    for     0,   8, s2_l3_entry, 0x70010000  /* hide device #1 */

>>    for     0, 496, s2_l3_entry, 0x70010000, 1

>> +

>> +  /* level 3 for north SMMU */

>> +  .org    0x6000

>> +  for     0,   8, smmu_l3_entry, 0xc00060000000

>> +  for     0,   8, smmu_l3_entry, 0xc00060010000  /* hide device #1 */

>> +  for     0, 496, smmu_l3_entry, 0xc00060010000

>> +  for     0,   8, smmu_l3_entry, 0x800070000000

>> +  for     0,   8, smmu_l3_entry, 0x800070010000  /* hide device #1 */

>> +  for     0, 496, smmu_l3_entry, 0x800070010000

>> --

>> 2.17.0

>>

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Patch

diff --git a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S
index 313ef3c56abc..af55f27bca47 100644
--- a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S
+++ b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S
@@ -20,15 +20,17 @@ 
  *   the SoC.
  */
 
-#define TT_S2_CONT_SHIFT          52
-#define TT_S2_AF                  (0x1 << 10)
-#define TT_S2_SH_NON_SHAREABLE    (0x0 << 8)
-#define TT_S2_AP_RW               (0x3 << 6)
-#define TT_S2_MEMATTR_DEVICE_nGRE (0x2 << 2)
-#define TT_S2_MEMATTR_MEMORY_WB   (0xf << 2)
-#define TT_S2_TABLE               (0x3 << 0)
-#define TT_S2_L3_PAGE             (0x1 << 1)
-#define TT_S2_VALID               (0x1 << 0)
+#define TT_S2_CONT_SHIFT            52
+#define TT_S2_AF                    (0x1 << 10)
+#define TT_S2_SH_NON_SHAREABLE      (0x0 << 8)
+#define TT_S2_AP_RO                 (0x1 << 6)
+#define TT_S2_AP_RW                 (0x3 << 6)
+#define TT_S2_MEMATTR_DEVICE_nGRE   (0x2 << 2)
+#define TT_S2_MEMATTR_DEVICE_nGnRE  (0x1 << 2)
+#define TT_S2_MEMATTR_MEMORY_WB     (0xf << 2)
+#define TT_S2_TABLE                 (0x3 << 0)
+#define TT_S2_L3_PAGE               (0x1 << 1)
+#define TT_S2_VALID                 (0x1 << 0)
 
   .altmacro
   .macro    for, start, count, do, arg2, arg3, arg4
@@ -58,6 +60,12 @@ 
             TT_S2_L3_PAGE | TT_S2_VALID | (\cont << TT_S2_CONT_SHIFT)
   .endm
 
+  .macro    smmu_l3_entry, base, offset=0, ignore=0
+  .quad     ((\base << 12) + \offset) | TT_S2_AF | TT_S2_AP_RO | \
+            TT_S2_SH_NON_SHAREABLE | TT_S2_MEMATTR_DEVICE_nGnRE | \
+            TT_S2_L3_PAGE | TT_S2_VALID
+  .endm
+
   .section  ".rodata", "a", %progbits
   /* level 1 */
   s2_mem_entry  0      /* 0x0000_0000 - 0x3fff_ffff */
@@ -86,3 +94,12 @@ 
 3:for     0,   8, s2_l3_entry, 0x70000000
   for     0,   8, s2_l3_entry, 0x70010000  /* hide device #1 */
   for     0, 496, s2_l3_entry, 0x70010000, 1
+
+  /* level 3 for north SMMU */
+  .org    0x6000
+  for     0,   8, smmu_l3_entry, 0xc00060000000
+  for     0,   8, smmu_l3_entry, 0xc00060010000  /* hide device #1 */
+  for     0, 496, smmu_l3_entry, 0xc00060010000
+  for     0,   8, smmu_l3_entry, 0x800070000000
+  for     0,   8, smmu_l3_entry, 0x800070010000  /* hide device #1 */
+  for     0, 496, smmu_l3_entry, 0x800070010000