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[198.145.21.10]) by mx.google.com with ESMTPS id t12-v6si28251547pgr.690.2018.05.30.11.19.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 May 2018 11:19:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=gCABZ4tF; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0316A210C9987; Wed, 30 May 2018 11:19:42 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::244; helo=mail-wm0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 12796210C9978 for ; Wed, 30 May 2018 11:19:40 -0700 (PDT) Received: by mail-wm0-x244.google.com with SMTP id 18-v6so43934053wml.2 for ; Wed, 30 May 2018 11:19:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fgYoYKWoshTorOCl2oPSlXJYjjZylJuB8SbfjrHR4GQ=; b=gCABZ4tFg/2lbL7dlQKIO6TiHkVwh4SzB2+s6Co8H6jNdTpbHQ6y3lLkaYk246OtaJ R4uX0JM2dQfHzjNBhgl/Y6DFZdZeuxDKNDGy3ETe5KYrwhkje3WoxqyWDCcDPlBpgeEr gTQHpXLYTTXAW+5B09jDqSAVEXGMBuXIEVt+Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fgYoYKWoshTorOCl2oPSlXJYjjZylJuB8SbfjrHR4GQ=; b=DgFltTx6ICWNoHgF8AoCHWc+RgpIvFmXY29OxKkbzfQT0zJnD3Meh4OjVbuLRm3Shu xCVZiluaifTUA6D1GyUvWAb5LiVnXIjmBbDQE/1bPFRGy+2f+3fddgIDaBMwodXRUz1Q cw62fXUyEqaqWXvQNcTX8aLGlCNZWnb0gxokNTvhV83tlcwh5X3+UwKmTASWMYWw/Vpr piG05yG1d5SLPse7T3ucq4N9+IJrsl83SUWJ7P/HUL3PNu9bKZG21cwCs5KeqyTH+3a6 tLxakq8rN3K5zLrehAA3A6eh+OqOcZKHfokmf+ESAkf4kzeIVgIui3Gy/wccl9/CXwac 8QHQ== X-Gm-Message-State: ALKqPwe3taOoj2WUkH0DRR7/nis4HCMXrrBmRGsqyldYOIbR8YXVKtBH lce2ffo754s35RbCDVxaHpwWDbo8zSs= X-Received: by 2002:a1c:17c9:: with SMTP id 192-v6mr2103620wmx.95.1527704378347; Wed, 30 May 2018 11:19:38 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:3995:5470:200:1aff:fe1b:b328]) by smtp.gmail.com with ESMTPSA id b105-v6sm48315705wrd.64.2018.05.30.11.19.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 May 2018 11:19:37 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 30 May 2018 20:19:29 +0200 Message-Id: <20180530181929.5066-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180530181929.5066-1-ard.biesheuvel@linaro.org> References: <20180530181929.5066-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 3/3] Silicon/SynQuacer/AcpiTables: add NETSEC/eMMC SMMU to the IORT X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Add a description of the SMMU that sits in front of the NETSEC and eMMC controllers to the IORT table so that ACPI based OSes can utilize it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc | 109 +++++++++++++++++++- 1 file changed, 107 insertions(+), 2 deletions(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc b/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc index 92c485f8006f..3f2aaa3d8858 100644 --- a/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc @@ -13,6 +13,7 @@ **/ #include +#include #include "AcpiTables.h" @@ -29,10 +30,23 @@ typedef struct { EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping; } SYNQUACER_RC_NODE; +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE Node; + EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT Context[8]; +} SYNQUACER_SMMU_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE Node; + CONST CHAR8 Name[11]; + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping; +} SYNQUACER_NC_NODE; + typedef struct { EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort; SYNQUACER_ITS_NODE ItsNode; SYNQUACER_RC_NODE RcNode[2]; + SYNQUACER_SMMU_NODE SmmuNode; + SYNQUACER_NC_NODE NamedCompNode[2]; } SYNQUACER_IO_REMAPPING_STRUCTURE; #define __SYNQUACER_ID_MAPPING(In, Num, Out, Ref, Flags) \ @@ -49,7 +63,7 @@ STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort = { __ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE, SYNQUACER_IO_REMAPPING_STRUCTURE, EFI_ACPI_IO_REMAPPING_TABLE_REVISION), - 3, // NumNodes + 6, // NumNodes sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset 0 // Reserved }, { @@ -94,7 +108,7 @@ STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort = { // __SYNQUACER_ID_MAPPING(0x0, 0x0, 0x0, ItsNode, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE), - }, { + }, { // PciRcNode { { @@ -121,6 +135,97 @@ STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort = { __SYNQUACER_ID_MAPPING(0x0, 0x0, 0x0, ItsNode, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE), } + }, { + // NETSEC/eMMC SMMU node + { + { + EFI_ACPI_IORT_TYPE_SMMUv1v2, + sizeof(SYNQUACER_SMMU_NODE), + 0x0, + 0x0, + 0x0, + 0x0, + }, + SYNQUACER_SCB_SMMU_BASE, + SYNQUACER_SCB_SMMU_SIZE, + EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500, + EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK, + FIELD_OFFSET(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE, + SMMU_NSgIrpt), + 0x8, + sizeof(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE), + 0x0, + 0x0, + 228, + EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, + 0x0, + 0x0, + }, { + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, + }, + }, { + { + // NETSEC named component node + { + { + EFI_ACPI_IORT_TYPE_NAMED_COMP, + sizeof(SYNQUACER_NC_NODE), + 0x0, + 0x0, + 0x1, + FIELD_OFFSET(SYNQUACER_NC_NODE, RcIdMapping), + }, + 0x0, + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, + 0x0, + 0x0, + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, + 40, + }, { + "\\_SB_.NET0" + }, { + 0x0, + 0x0, + 0x0, + FIELD_OFFSET(SYNQUACER_IO_REMAPPING_STRUCTURE, SmmuNode), + EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE + } + }, { + // eMMC named component node + { + { + EFI_ACPI_IORT_TYPE_NAMED_COMP, + sizeof(SYNQUACER_NC_NODE), + 0x0, + 0x0, + 0x1, + FIELD_OFFSET(SYNQUACER_NC_NODE, RcIdMapping), + }, + 0x0, + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, + 0x0, + 0x0, + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, + 40, + }, { + "\\_SB_.MMC0" + }, { + 0x0, + 0x0, + 0x0, + FIELD_OFFSET(SYNQUACER_IO_REMAPPING_STRUCTURE, SmmuNode), + EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE + } + } } };