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[203.254.224.25]) by mx.google.com with ESMTP id ru9si32332234pbc.250.2012.12.28.07.31.01; Fri, 28 Dec 2012 07:31:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of amarendra.xt@samsung.com designates 203.254.224.25 as permitted sender) client-ip=203.254.224.25; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of amarendra.xt@samsung.com designates 203.254.224.25 as permitted sender) smtp.mail=amarendra.xt@samsung.com Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MFQ00MY1Z2Z6040@mailout2.samsung.com>; Sat, 29 Dec 2012 00:30:49 +0900 (KST) Received: from epcpdlpp25 ( [172.20.52.125]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 9E.F5.01231.92BBDD05; Sat, 29 Dec 2012 00:30:49 +0900 (KST) X-AuditID: cbfee61a-b7fa66d0000004cf-b5-50ddbb297189 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 3E.F5.01231.92BBDD05; Sat, 29 Dec 2012 00:30:49 +0900 (KST) Received: from chrome-ubuntu.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MFQ008MSZ2SO710@mmp2.samsung.com>; Sat, 29 Dec 2012 00:30:49 +0900 (KST) From: Amar To: u-boot@lists.denx.de, jh80.chung@samsung.com Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, afleming@gmail.com Subject: [PATCH 5/9] EXYNOS5: DWMMC: API to set mmc clock divisor Date: Fri, 28 Dec 2012 10:52:48 -0500 Message-id: <1356709972-26549-6-git-send-email-amarendra.xt@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1356709972-26549-1-git-send-email-amarendra.xt@samsung.com> References: <1356709972-26549-1-git-send-email-amarendra.xt@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrHLMWRmVeSWpSXmKPExsWyRsSkVldz990Ag7sbVCwerr/JYjHl8BcW ByaPO9f2sAUwRnHZpKTmZJalFunbJXBlbFh0jrXgp1jF57c/2BoYnwl1MXJwSAiYSMx9m9PF yAlkiklcuLeerYuRi0NIYBajxOGPr1khEiYSj7f8g0pMZ5TYvKmJGcLpZZL4c/wIC8gkNgFV iV+L7UEaRAQMJKY/2c4KEmYWKJB4tlsMJCws4CixcNdiZhCbBaj62P2bbCAlvAIeEof6RCFW yUl82POIHcTmFPCUePRsEVi5EFDJ1U272CBaBSS+TT7EAnG+rMSmA2DHSAjcZpOY3zeZBWKO pMTBFTdYJjAKL2BkWMUomlqQXFCclJ5rqFecmFtcmpeul5yfu4kRGIin/z2T2sG4ssHiEKMA B6MSD+/CnjsBQqyJZcWVuYcYJTiYlUR4+5rvBgjxpiRWVqUW5ccXleakFh9i9AG6ZCKzlGhy PjBK8kriDY1NzE2NTS2NjMxMTXEIK4nzNnukBAgJpCeWpGanphakFsGMY+LglGpg1J3ddqb1 cM/ae3NZXE1FeHSF9pf781r5OKTdnVuUXv7+Vv6rA0ueLvHjTnqzPj8s/FXRiYnXH8nYfPWb bJI7c9+VP/vyqieuq5O+e+fcvX+6kdHT5G8unvqe+WScfXi0QZCKRfRSs7fbVh+7Ifv1QodJ hBSj47ZjgsqvnI52ZgR2tKmwPWxYocRSnJFoqMVcVJwIALIW+iFxAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupjkeLIzCtJLcpLzFFi42I5/e+xoK7m7rsBBpd+iFs8XH+TxWLK4S8s Dkwed67tYQtgjGpgtMlITUxJLVJIzUvOT8nMS7dV8g6Od443NTMw1DW0tDBXUshLzE21VXLx CdB1y8wBmq2kUJaYUwoUCkgsLlbSt8M0ITTETdcCpjFC1zckCK7HyAANJKxhzNiw6BxrwU+x is9vf7A1MD4T6mLk5JAQMJF4vOUfG4QtJnHh3nogm4tDSGA6o8TmTU3MEE4vk8Sf40dYuhg5 ONgEVCV+LbYHaRARMJCY/mQ7K0iYWaBA4tluMZCwsICjxMJdi5lBbBag6mP3b7KBlPAKeEgc 6hOFWCUn8WHPI3YQm1PAU+LRs0Vg5UJAJVc37WKbwMi7gJFhFaNoakFyQXFSeq6hXnFibnFp Xrpecn7uJkZwoD+T2sG4ssHiEKMAB6MSD+/CnjsBQqyJZcWVuYcYJTiYlUR4+5rvBgjxpiRW VqUW5ccXleakFh9i9AE6aiKzlGhyPjAK80riDY1NzE2NTS1NLEzMLHEIK4nzNnukBAgJpCeW pGanphakFsGMY+LglGpg5J7iptjVtPor03Ln8w8tHktMXyPSlGTYE6q8qaZjzkebmBimyJ4b jD+Lj+3YF+U3/Szv/6TvdZ2eBqpBC1REf71aI631YY7FUc+79ZGO658eOtAyf71XrunN1XM9 VTfeCvc0SjZheVyStT6ed1pv9hRO85YloVYvE/0SOjkTAvY7e9jfMzJRYinOSDTUYi4qTgQA jALRyaECAAA= X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQkDXGK2+iefvJyqxu9/Y4AVWDjU203sa95qinCQh4tViH+yPdQvFxlZOTaq6Ikle4i70RUY This API computes the divisor value based on MPLL clock and writes it into the FSYS1 register. Signed-off-by: Amar --- arch/arm/cpu/armv7/exynos/clock.c | 38 ++++++++++++++++++++++++++++++++-- arch/arm/include/asm/arch-exynos/clk.h | 3 +++ 2 files changed, 39 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 731bbff..bc8e585 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -379,7 +379,7 @@ static unsigned long exynos4_get_mmc_clk(int dev_index) (struct exynos4_clock *)samsung_get_base_clock(); unsigned long uclk, sclk; unsigned int sel, ratio, pre_ratio; - int shift; + int shift = 0; sel = readl(&clk->src_fsys); sel = (sel >> (dev_index << 2)) & 0xf; @@ -428,7 +428,7 @@ static unsigned long exynos5_get_mmc_clk(int dev_index) (struct exynos5_clock *)samsung_get_base_clock(); unsigned long uclk, sclk; unsigned int sel, ratio, pre_ratio; - int shift; + int shift = 0; sel = readl(&clk->src_fsys); sel = (sel >> (dev_index << 2)) & 0xf; @@ -526,6 +526,40 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) writel(val, addr); } +/* exynos5: set the mmc clock div ratio in fsys1 */ +int exynos5_mmc_set_clk_div(int dev_id) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned int addr; + unsigned int clock; + unsigned int tmp; + unsigned int i; + + /* get mpll clock */ + clock = get_pll_clk(MPLL) / 1000000; + + /* + * CLK_DIV_FSYS1 + * MMC0_PRE_RATIO [15:8], MMC0_RATIO [3:0] + * CLK_DIV_FSYS2 + * MMC2_PRE_RATIO [15:8], MMC2_RATIO [3:0] + */ + if (dev_id <= PERIPH_ID_SDMMC1) + addr = (unsigned int)&clk->div_fsys1; + else + addr = (unsigned int)&clk->div_fsys2; + + tmp = readl(addr) & ~FSYS1_MMC0_DIV_MASK; + for (i = 0; i <= 0xf; i++) { + if ((clock / (i + 1)) <= 400) { + writel(tmp | i << 0, addr); + break; + } + } + return 0; +} + /* get_lcd_clk: return lcd clock frequency */ static unsigned long exynos4_get_lcd_clk(void) { diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index ff155d8..3eaa041 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -29,6 +29,8 @@ #define VPLL 4 #define BPLL 5 +#define FSYS1_MMC0_DIV_MASK 0xff0f + unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); unsigned long get_i2c_clk(void); @@ -36,6 +38,7 @@ unsigned long get_pwm_clk(void); unsigned long get_uart_clk(int dev_index); unsigned long get_mmc_clk(int deV_index); void set_mmc_clk(int dev_index, unsigned int div); +int exynos5_mmc_set_clk_div(int dev_index); unsigned long get_lcd_clk(void); void set_lcd_clk(void); void set_mipi_clk(void);