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[203.254.224.25]) by mx.google.com with ESMTP id ru9si32332234pbc.250.2012.12.28.07.31.03; Fri, 28 Dec 2012 07:31:04 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of amarendra.xt@samsung.com designates 203.254.224.25 as permitted sender) client-ip=203.254.224.25; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of amarendra.xt@samsung.com designates 203.254.224.25 as permitted sender) smtp.mail=amarendra.xt@samsung.com Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MFQ00MY1Z2Z6040@mailout2.samsung.com>; Sat, 29 Dec 2012 00:30:55 +0900 (KST) Received: from epcpdlpp25 ( [172.20.52.125]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id C4.06.01231.E2BBDD05; Sat, 29 Dec 2012 00:30:55 +0900 (KST) X-AuditID: cbfee61a-b7fa66d0000004cf-df-50ddbb2e2ba4 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 24.06.01231.E2BBDD05; Sat, 29 Dec 2012 00:30:54 +0900 (KST) Received: from chrome-ubuntu.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MFQ008MSZ2SO710@mmp2.samsung.com>; Sat, 29 Dec 2012 00:30:54 +0900 (KST) From: Amar To: u-boot@lists.denx.de, jh80.chung@samsung.com Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, afleming@gmail.com Subject: [PATCH 8/9] SMDK5250: Enable EMMC booting Date: Fri, 28 Dec 2012 10:52:51 -0500 Message-id: <1356709972-26549-9-git-send-email-amarendra.xt@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1356709972-26549-1-git-send-email-amarendra.xt@samsung.com> References: <1356709972-26549-1-git-send-email-amarendra.xt@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrALMWRmVeSWpSXmKPExsWyRsSkVld/990Ag463LBYP199ksZhy+AuL A5PHnWt72AIYo7hsUlJzMstSi/TtErgyft9ayljwRKliacsCpgbG6zJdjJwcEgImEt+eX2SB sMUkLtxbz9bFyMUhJDCLUWLr4ZssMEXnJ65ghkhMZ5T4tvs2I4TTyySx8uNJpi5GDg42AVWJ X4vtQRpEBAwkpj/ZzgoSZhYokHi2WwwkLCxgJPHg2mo2EJsFqHr7+9esIDavgIfE5p1v2CB2 yUl82POIHcTmFPCUePRsETOILQRUc3XTLqheAYlvkw+xgIyXEJCV2HQA7DQJgftsEjv/PGaC mCMpcXDFDZYJjMILGBlWMYqmFiQXFCel5xrqFSfmFpfmpesl5+duYgQG4+l/z6R2MK5ssDjE KMDBqMTDu7DnToAQa2JZcWXuIUYJDmYlEd6+5rsBQrwpiZVVqUX58UWlOanFhxh9gC6ZyCwl mpwPjJS8knhDYxNzU2NTSyMjM1NTHMJK4rzNHikBQgLpiSWp2ampBalFMOOYODilGhi38QQE L5un+iL4SoCM5SNTprjiRdKHczNlbzefmZElGc6UdMphoZXGy+mbqwKbmHM9lS8oPHFUDxEv 7vU6ZJbFLRbKJiAwY14506QFjM+sJnQvWfR6oSCH2Z/8U5dffXWc3vvVeQtf1JeHIny3Drqn OstO4uMUDrNuW/709vLLnkZhLcIvpyixFGckGmoxFxUnAgAw4gdBcwIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupnkeLIzCtJLcpLzFFi42I5/e+xoK7e7rsBBguazS0err/JYjHl8BcW ByaPO9f2sAUwRjUw2mSkJqakFimk5iXnp2TmpdsqeQfHO8ebmhkY6hpaWpgrKeQl5qbaKrn4 BOi6ZeYAzVZSKEvMKQUKBSQWFyvp22GaEBripmsB0xih6xsSBNdjZIAGEtYwZvy+tZSx4IlS xdKWBUwNjNdluhg5OSQETCTOT1zBDGGLSVy4t56ti5GLQ0hgOqPEt923GSGcXiaJlR9PMnUx cnCwCahK/FpsD9IgImAgMf3JdlaQMLNAgcSz3WIgYWEBI4kH11azgdgsQNXb379mBbF5BTwk Nu98wwaxS07iw55H7CA2p4CnxKNni8BuEAKqubppF9sERt4FjAyrGEVTC5ILipPScw31ihNz i0vz0vWS83M3MYJD/ZnUDsaVDRaHGAU4GJV4eBf23AkQYk0sK67MPcQowcGsJMLb13w3QIg3 JbGyKrUoP76oNCe1+BCjD9BVE5mlRJPzgXGYVxJvaGxibmpsamliYWJmiUNYSZy32SMlQEgg PbEkNTs1tSC1CGYcEwenVAOj32Kx5bx2wr9rNr60/3z1SpG+xno2+6kXPm77znDmybcJ8pHx d/sanJ8Yr5Zcw33gxgWWVn31/ZVlmbm39zOKqu4vriuXneG7+l5owTPjd3IXInZe9z6y5m7C ijOPF+0sfV7LfVv/8b64WOtbpV/Cnhk+U1D4Ktuyhn356dMrj51cymdc5HFukxJLcUaioRZz UXEiANjgczaiAgAA X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQmuTvPapmK8sEgsIyK2Xzk5Ns4cOESxyOzm9RWgko6hXwKHROp/A50LKS0rlcq1BttGNei1 This patch adds support for EMMC booting on SMDK5250. Signed-off-by: Amar --- board/samsung/smdk5250/clock_init.c | 18 +++++++++++++ board/samsung/smdk5250/clock_init.h | 5 ++++ board/samsung/smdk5250/spl_boot.c | 52 ++++++++++++++++++++++++++++++++----- 3 files changed, 69 insertions(+), 6 deletions(-) diff --git a/board/samsung/smdk5250/clock_init.c b/board/samsung/smdk5250/clock_init.c index c009ae5..90d2199 100644 --- a/board/samsung/smdk5250/clock_init.c +++ b/board/samsung/smdk5250/clock_init.c @@ -28,6 +28,7 @@ #include #include #include +#include #include "clock_init.h" #include "setup.h" @@ -664,3 +665,20 @@ void clock_init_dp_clock(void) /* We run DP at 267 Mhz */ setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); } + +/* + * Set clock divisor value for booting from emmc. + * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz. + */ +void emmc_boot_clk_div_set(void) +{ + struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; + unsigned int addr; + unsigned int div_mmc; + + addr = (unsigned int) &clk->div_fsys1; + + div_mmc = readl(addr) & ~FSYS1_MMC0_DIV_MASK; + div_mmc |= FSYS1_MMC0_DIV_VAL; + writel(div_mmc, addr); +} diff --git a/board/samsung/smdk5250/clock_init.h b/board/samsung/smdk5250/clock_init.h index f751bcb..9b156f7 100644 --- a/board/samsung/smdk5250/clock_init.h +++ b/board/samsung/smdk5250/clock_init.h @@ -146,4 +146,9 @@ struct mem_timings *clock_get_mem_timings(void); * Initialize clock for the device */ void system_clock_init(void); + +/* + * Set clock divisor value for booting from emmc. + */ +void emmc_boot_clk_div_set(void); #endif diff --git a/board/samsung/smdk5250/spl_boot.c b/board/samsung/smdk5250/spl_boot.c index d8f3c1e..e94677b 100644 --- a/board/samsung/smdk5250/spl_boot.c +++ b/board/samsung/smdk5250/spl_boot.c @@ -23,16 +23,41 @@ #include #include +#include +#include +#include + +#include "clock_init.h" + +/* Index into irom ptr table */ +enum index { + MMC_INDEX, + EMMC44_INDEX, + EMMC44_END_INDEX, + SPI_INDEX, +}; + +/* IROM Function Pointers Table */ +void (*irom_ptr_table[])(void) = { + [MMC_INDEX] = (void *)0x02020030, /* iROM Function Pointer + -SDMMC boot */ + [EMMC44_INDEX] = (void *)0x02020044, /* iROM Function Pointer + -EMMC 4.4 boot */ + [EMMC44_END_INDEX] = (void *)0x02020048,/* iROM Function Pointer + -EMMC 4.4 end boot opration */ + [SPI_INDEX] = (void *)0x02020058, /* iROM Function Pointer + -SPI boot */ + }; + enum boot_mode { BOOT_MODE_MMC = 4, BOOT_MODE_SERIAL = 20, + BOOT_MODE_EMMC = 8, /* EMMC4.4 */ /* Boot based on Operating Mode pin settings */ BOOT_MODE_OM = 32, BOOT_MODE_USB, /* Boot using USB download */ }; - typedef u32 (*spi_copy_func_t)(u32 offset, u32 nblock, u32 dst); - /* * Copy U-boot from mmc to RAM: * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains @@ -40,23 +65,38 @@ enum boot_mode { */ void copy_uboot_to_ram(void) { - spi_copy_func_t spi_copy; enum boot_mode bootmode; - u32 (*copy_bl2)(u32, u32, u32); + u32 (*spi_copy)(u32 offset, u32 nblock, u32 dst); + u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst); + u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst); + void (*end_bootop_from_emmc)(void); bootmode = readl(EXYNOS5_POWER_BASE) & OM_STAT; switch (bootmode) { case BOOT_MODE_SERIAL: - spi_copy = *(spi_copy_func_t *)EXYNOS_COPY_SPI_FNPTR_ADDR; + spi_copy = (void *) *(u32 *)irom_ptr_table[SPI_INDEX]; spi_copy(SPI_FLASH_UBOOT_POS, CONFIG_BL2_SIZE, CONFIG_SYS_TEXT_BASE); break; case BOOT_MODE_MMC: - copy_bl2 = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR; + copy_bl2 = (void *) *(u32 *)irom_ptr_table[MMC_INDEX]; copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); break; + case BOOT_MODE_EMMC: + emmc_boot_clk_div_set(); + + copy_bl2_from_emmc = + (void *) *(u32 *)irom_ptr_table[EMMC44_INDEX]; + end_bootop_from_emmc = + (void *) *(u32 *)irom_ptr_table[EMMC44_END_INDEX]; + + copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); + end_bootop_from_emmc(); + + break; + default: break; }