From patchwork Fri Jun 1 14:12:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 137532 Delivered-To: patches@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp992015lji; Fri, 1 Jun 2018 07:12:29 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLd9Fjs8Ut68sH9LQpzCuNt/j4bnCv3EcznFZQcG4YgNkSj8XDnSDBR+oFwEu5WUjpYAnO0 X-Received: by 2002:adf:dd8c:: with SMTP id x12-v6mr9739235wrl.212.1527862349376; Fri, 01 Jun 2018 07:12:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527862349; cv=none; d=google.com; s=arc-20160816; b=ekSXiti7BlyQ2lai8lv8ie5kFlkUTmoh4IZeXPQiNirhm4lX/rXZmdhW0yeg+iTgn0 nIRuJJnW/ImzwH7GQ6jKZ9XZ1hBpkJAXLQgBjAo52ZjN7vsVzEaAf/Hrk71nzvziK+cb Ewzv9WyDzaURTyacAOMOrmpDu+VtPuCPBQPUieQMOTS8LGw6sGidcBrEqyXI0fGzEKID qDF0B2vayKaBlsT/5JN17E7GEunB66HfA4hWGp+B5wBBEgk1lir7Nlkw8krEh/M3kQVr aB+Ew4IdqyPt3J/hzcrlcoNhzJOPszm4d/7h+8REyqA2IE/xaPq/ojvmdUrHQqD7FPOX nWIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=Yyyz7M2s/zRocVSpcrTueIs2tGfn4soddIOtQX/p0Ow=; b=0IQTtzI+eb+fiCP8DTQpMx93C+r8wHzBrNybD3pQY0rtjOcOJuSgQof70al98+ZWzK ymsdF04CEFqeODvAdlNDwoBGh7AFFxC6ppfmXqpobivFUnOcTc4aXeHapbAONDJrHA/x H0gEuDKPQGionSHC/VLAmxQFeMyyylDlEctEf30tdDbHYO7PT0seKyKnIQ1hE5ZgJDbr igLlW4vzEwu2+jBMLxX0ZCK8f+zuiZpa+IUYABgUmyjTySSLHG/lC5RrtGFKRAMYZhnZ 79j17dxPfNI2MQn1w7yjd9nz6BIn804MlffzjFEOlHFKU4RnqXaCweuT0CmxYpsWGbAr z1bQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 134-v6si1583750wmp.229.2018.06.01.07.12.29 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 01 Jun 2018 07:12:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fOkn6-000446-Th; Fri, 01 Jun 2018 15:12:28 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Kevin Wolf , Max Reitz , "Michael S. Tsirkin" , Paolo Bonzini , Thomas Huth , Aurelien Jarno , qemu-block@nongnu.org, Yongbok Kim Subject: [PATCH 6/6] hw/char/parallel: Convert away from old_mmio Date: Fri, 1 Jun 2018 15:12:23 +0100 Message-Id: <20180601141223.26630-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180601141223.26630-1-peter.maydell@linaro.org> References: <20180601141223.26630-1-peter.maydell@linaro.org> Convert the parallel device away from using the old_mmio field of MemoryRegionOps. This change only affects the memory-mapped variant, which is used by the MIPS Jazz boards 'magnum' and 'pica61'. Signed-off-by: Peter Maydell --- hw/char/parallel.c | 50 ++++++++++------------------------------------ 1 file changed, 11 insertions(+), 39 deletions(-) -- 2.17.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/char/parallel.c b/hw/char/parallel.c index 1542d62201..35748e6c1b 100644 --- a/hw/char/parallel.c +++ b/hw/char/parallel.c @@ -554,56 +554,28 @@ static void parallel_isa_realizefn(DeviceState *dev, Error **errp) } /* Memory mapped interface */ -static uint32_t parallel_mm_readb (void *opaque, hwaddr addr) +static uint64_t parallel_mm_readfn(void *opaque, hwaddr addr, unsigned size) { ParallelState *s = opaque; - return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF; + return parallel_ioport_read_sw(s, addr >> s->it_shift) & + MAKE_64BIT_MASK(0, size * 8); } -static void parallel_mm_writeb (void *opaque, - hwaddr addr, uint32_t value) +static void parallel_mm_writefn(void *opaque, hwaddr addr, + uint64_t value, unsigned size) { ParallelState *s = opaque; - parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF); -} - -static uint32_t parallel_mm_readw (void *opaque, hwaddr addr) -{ - ParallelState *s = opaque; - - return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF; -} - -static void parallel_mm_writew (void *opaque, - hwaddr addr, uint32_t value) -{ - ParallelState *s = opaque; - - parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF); -} - -static uint32_t parallel_mm_readl (void *opaque, hwaddr addr) -{ - ParallelState *s = opaque; - - return parallel_ioport_read_sw(s, addr >> s->it_shift); -} - -static void parallel_mm_writel (void *opaque, - hwaddr addr, uint32_t value) -{ - ParallelState *s = opaque; - - parallel_ioport_write_sw(s, addr >> s->it_shift, value); + parallel_ioport_write_sw(s, addr >> s->it_shift, + value & MAKE_64BIT_MASK(0, size * 8)); } static const MemoryRegionOps parallel_mm_ops = { - .old_mmio = { - .read = { parallel_mm_readb, parallel_mm_readw, parallel_mm_readl }, - .write = { parallel_mm_writeb, parallel_mm_writew, parallel_mm_writel }, - }, + .read = parallel_mm_readfn, + .write = parallel_mm_writefn, + .valid.min_access_size = 1, + .valid.max_access_size = 4, .endianness = DEVICE_NATIVE_ENDIAN, };