From patchwork Fri Jun 1 14:43:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 137535 Delivered-To: patches@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1029376lji; Fri, 1 Jun 2018 07:43:31 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJREYvjoVcjYl9W7I7Oy7WQf07KT+ceW5xAwY6hGrtHigR2xeLyErp5l0cf3Der+GkBN53T X-Received: by 2002:adf:9844:: with SMTP id v62-v6mr8999774wrb.100.1527864211346; Fri, 01 Jun 2018 07:43:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527864211; cv=none; d=google.com; s=arc-20160816; b=YTkKflkQ0Mum8sgcQVMN7ryn70542tBgiKUHJHeFUeGmXhyqm+r/4WpNPH8RGLIGH9 XHEafThu4dmXmioTEDBdXYhR9N3F1aXB2AdFNdHM1ZF0OviUVcoYVAo/L4m8Npse2rCY PufKqPDgdFUxeF0FAl3Xpvhwc2WnpgbfzZJhnFbe3PIUM9CuhMhTZmjx7PpdWPW37Dd5 jZgYjnWLp+PLiirui+uTPdEa/ovKyW3bYOh5mVhJT9ez4rh3KEnZFPPpnJ/VQcy8hGZ6 80wgkT77DoMF7DU58Qitmf8mPEj3dWqPm+VZKevIw3Xz5azXkBE+/JQcH3IUKfpCKOnB u3Kg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=md5CzOwfzp6x9w0ab2GFuNtdfXVHTUCzNzCqNTcdzlk=; b=PXFYG9WrQHs8i45n/GvPmE4bnSWwOZvqRj9iVsp0HFam3H2ZO6eRzRfjOVAb+0Fpbk L8TcbkZctEfQCg/CQOuVnCOXRopudO4Ew1nCswUfDk6Y1NX11b3XT6hxB38+9kEUpshB Idl9SSrYcoDYurhkqnLOxJ5bgFBa8IOti1FdEBoMaWTr+V6o0cqGQ7DEnEl459GRPvjA 832SS4YZ6ALdzAivBHCycYAgCYMtiEsr7v74LlUJ3A+0IOIm5oLQ6XkoQ9Hu+byVvGSr 6NYJTNFtctN4uyYBzlmYZYEnXRQOviY7BqDuSUDSU/e7LoycGc6qnLUCEIV5plqdfIuG AIcg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id c18-v6si12251166wrg.158.2018.06.01.07.43.31 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 01 Jun 2018 07:43:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fOlH8-00047W-7x; Fri, 01 Jun 2018 15:43:30 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Julia Suvorova , Stefan Hajnoczi , Joel Stanley , Jim Mussared , =?utf-8?q?Steffen_G=C3=B6rtz?= Subject: [PATCH 1/2] stellaris: Stop using armv7m_init() Date: Fri, 1 Jun 2018 15:43:27 +0100 Message-Id: <20180601144328.23817-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180601144328.23817-1-peter.maydell@linaro.org> References: <20180601144328.23817-1-peter.maydell@linaro.org> The stellaris board is still using the legacy armv7m_init() function, which predates conversion of the ARMv7M into a proper QOM container object. Make the board code directly create the ARMv7M object instead. Signed-off-by: Peter Maydell --- hw/arm/stellaris.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) -- 2.17.1 Reviewed-by: Stefan Hajnoczi diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index e886f54976..1b2c383e9f 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -20,6 +20,7 @@ #include "qemu/log.h" #include "exec/address-spaces.h" #include "sysemu/sysemu.h" +#include "hw/arm/armv7m.h" #include "hw/char/pl011.h" #include "hw/misc/unimp.h" #include "cpu.h" @@ -1297,8 +1298,13 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) &error_fatal); memory_region_add_subregion(system_memory, 0x20000000, sram); - nvic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES, - ms->kernel_filename, ms->cpu_type); + nvic = qdev_create(NULL, TYPE_ARMV7M); + qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); + qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); + object_property_set_link(OBJECT(nvic), OBJECT(get_system_memory()), + "memory", &error_abort); + /* This will exit with an error if the user passed us a bad cpu_type */ + qdev_init_nofail(nvic); qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0, qemu_allocate_irq(&do_sys_reset, NULL, 0)); @@ -1430,6 +1436,8 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000); create_unimplemented_device("hibernation", 0x400fc000, 0x1000); create_unimplemented_device("flash-control", 0x400fd000, 0x1000); + + armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, flash_size); } /* FIXME: Figure out how to generate these from stellaris_boards. */