From patchwork Fri Jun 1 16:03:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 137538 Delivered-To: patches@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1123688lji; Fri, 1 Jun 2018 09:03:57 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLgu7p7+nVWBZrboujTgBuYHhSAPt51KB7FZ7FmIsDHry/xcBFe1oBr48beFnbT1s5DVHSF X-Received: by 2002:adf:f482:: with SMTP id l2-v6mr9190784wro.259.1527869037780; Fri, 01 Jun 2018 09:03:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527869037; cv=none; d=google.com; s=arc-20160816; b=nqF7yL8NoGItm0srfz0J1LCuig0d8Jrdf/oIpqb04FHe8PBF+KHwXA4RgSyjMa8Bha SrNVCzDWIdbKyWsi3dkt2lIZ+RIUwlw3pAh5wj060l47XDBk6M/rmj6CVImyWN+vmf5J LTn0J9wS43rvUfOY1qJfPXRy8jb4aky438N3L+mCBj/nbR/vuqbZISIW9/972er/l26x X9WFub5UN+HKmo8X+GkPN2LTPO4RT/OQrJIcyH38Y4xlKjBYmgmzOeSdGWott7dbw4Z0 83inBwwOAMGz+FtM4Wz7nEzCj6bJS1VNdHmFZ9J1dart8nXRhy3ohblvvY8af172TfYN X7vw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=message-id:date:subject:cc:to:from:arc-authentication-results; bh=ywHXxQ6ZiR7ZmT8vKEXfdz1Mg0UmTguDg6EqW61U0GY=; b=MxmHMZ/Geqcp1t4a2L7bvrts130QptJIwWeLClKWAsf3bFy5XAZPcpludMXSk4S7OT no23V2ccYMbwRAHCTz0Tsk4lkI+8QWAOfkaTITSD2fWtyMtwtxSvRduZDykYmzwBKR1v UoyGCNZ9lb9ju1/e6orKn6jBeOLw9X9mDuagrobfngu/FXTSdqx+rVdj6QHQyy/jnqSf FfKbbNEu73db8WErrGwZxcXwSWDJKYG4pu5uXqh5HBs8JpsjGN91gxkQ5VtaUrGKRdSw muxps23oswl8IAREHtmOVN0FbNVi7vcJNT24Z0wxEuuf4eI8rVsSrwR51hANIQkRvxmk KlCQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id v17-v6si20646879wrf.43.2018.06.01.09.03.57 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 01 Jun 2018 09:03:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fOmWy-0004DE-Lv; Fri, 01 Jun 2018 17:03:56 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH] arm: Don't crash if user tries to use a Cortex-M CPU without an NVIC Date: Fri, 1 Jun 2018 17:03:55 +0100 Message-Id: <20180601160355.15393-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 The Cortex-M CPU and its NVIC are two intimately intertwined parts of the same hardware; it is not possible to use one without the other. Unfortunately a lot of our board models don't do any sanity checking on the CPU type the user asks for, so a command line like qemu-system-arm -M versatilepb -cpu cortex-m3 will create an M3 without an NVIC, and coredump immediately. In the other direction, trying a non-M-profile CPU in an M-profile board won't blow up, but doesn't do anything useful either: qemu-system-arm -M lm3s6965evb -cpu arm926 Add some checking in the NVIC and CPU realize functions that the user isn't trying to use an NVIC without an M-profile CPU or an M-profile CPU without an NVIC, so we can produce a helpful error message rather than a core dump. Fixes: https://bugs.launchpad.net/qemu/+bug/1766896 Signed-off-by: Peter Maydell --- hw/arm/armv7m.c | 7 ++++++- hw/intc/armv7m_nvic.c | 6 +++++- target/arm/cpu.c | 18 ++++++++++++++++++ 3 files changed, 29 insertions(+), 2 deletions(-) -- 2.17.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index a4ab7d2069..9e00d4037c 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -178,6 +178,12 @@ static void armv7m_realize(DeviceState *dev, Error **errp) return; } } + + /* Tell the CPU where the NVIC is; it will fail realize if it doesn't + * have one. + */ + s->cpu->env.nvic = &s->nvic; + object_property_set_bool(OBJECT(s->cpu), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); @@ -202,7 +208,6 @@ static void armv7m_realize(DeviceState *dev, Error **errp) sbd = SYS_BUS_DEVICE(&s->nvic); sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); - s->cpu->env.nvic = &s->nvic; memory_region_add_subregion(&s->container, 0xe000e000, sysbus_mmio_get_region(sbd, 0)); diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index c51151fa8a..661be8878a 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2183,7 +2183,11 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) int regionlen; s->cpu = ARM_CPU(qemu_get_cpu(0)); - assert(s->cpu); + + if (!s->cpu || !arm_feature(&s->cpu->env, ARM_FEATURE_M)) { + error_setg(errp, "The NVIC can only be used with a Cortex-M CPU"); + return; + } if (s->num_irq > NVIC_MAX_IRQ) { error_setg(errp, "num-irq %d exceeds NVIC maximum", s->num_irq); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5d60893a07..eda1ce14fc 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -767,6 +767,24 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) return; } +#ifndef CONFIG_USER_ONLY + /* The NVIC and M-profile CPU are two halves of a single piece of + * hardware; trying to use one without the other is a command line + * error and will result in segfaults if not caught here. + */ + if (arm_feature(env, ARM_FEATURE_M)) { + if (!env->nvic) { + error_setg(errp, "This board cannot be used with Cortex-M CPUs"); + return; + } + } else { + if (env->nvic) { + error_setg(errp, "This board can only be used with Cortex-M CPUs"); + return; + } + } +#endif + cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err);