From patchwork Fri Jun 8 09:51:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 137946 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp695562lji; Fri, 8 Jun 2018 03:35:29 -0700 (PDT) X-Google-Smtp-Source: ADUXVKInCHalJx1lEN61mIGV4gZH6XIv4RNAS2GvLsphM8cn8V5vcHXRwaeJnc+Kn3inn6XcCbEJ X-Received: by 2002:aa7:d60f:: with SMTP id c15-v6mr6656645edr.301.1528454129653; Fri, 08 Jun 2018 03:35:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528454129; cv=none; d=google.com; s=arc-20160816; b=HXYNOsJqTrLym2T4ZVUA2MayE684PMGjKX56kTbSkItu+uq0OlQFe0sLcUgNFGgeER LUwj9oGtlcAzwKS0m80k/jzregfHOeIxmNlPN5SN/dRPiJxh/a/V42h8VPEhuD/OWzpb tH/30RZCvI8suyB5dAyceH0xqBgbWLnTIihguEZLRUg/qdxz7dLWCPn7X5YsrDecyN41 eBA1N70CfUVCiL0qb7QYQmn9cDUQHxx7UcZ88JpgsPwOP3I49TARpUqZz3kYcd83Hf65 SpNqWOAFJ4p4LDCSqkUNbS1PDKmiCxMs/MmyMWFZFMD//zuoz7121xbRWKlflhcAxmPf bt5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=9O4WtIsb76XBdRamoTW9Z8nKwWRX3JD8EjJu8iFohuE=; b=QaflWPSo45orYe5dlq+Hj/4KXjWaRoEHRzS0dRYA72iTPQqrK48gkkJc1AlEQL0+Ye Q4VbINHdiTbJWOOwDEFRw+xMQPQGwBTTiDdb7CvjZfigH1gsHXPIA3BFogODt2aj58L3 xlvsVh1HcX7vd5KUHTV6h2q7BYl492skOUP4G6qGfcZ74RTVtwc+n0S/T/0x6hbYeqw0 /vJ21aPdGRO5JS5eCw/tC6hLr+dnpUCiqqNITc+jwzFux5/c8S+QKNhASP/nPhczo8Ah 3vPX/loUIHvUs9Lg1hX6JS4kHMPjRC1wrCyxnGHFZKD+RcZaWb5kNYcCUXaelMWyR/U2 QjrQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=qW7YmiZO; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id g20-v6si2133260edp.450.2018.06.08.03.35.29; Fri, 08 Jun 2018 03:35:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=qW7YmiZO; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 3D089C21C51; Fri, 8 Jun 2018 10:35:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9DC72C21DB6; Fri, 8 Jun 2018 10:34:20 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 6BD3AC21BE5; Fri, 8 Jun 2018 09:51:29 +0000 (UTC) Received: from fllnx210.ext.ti.com (fllnx210.ext.ti.com [198.47.19.17]) by lists.denx.de (Postfix) with ESMTPS id B0582C21C27 for ; Fri, 8 Jun 2018 09:51:28 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id w589pQ1V001512 for ; Fri, 8 Jun 2018 04:51:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1528451486; bh=vQMlT/jflVgTLZ9LztLhF3gusw0P/DVJ6wTxoVkcvR8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=qW7YmiZOvRReaYBvPZqcvGdQuGZMI6Or+Fjl5iQ/N5XgldLZ/M9+jcAetOtrcN1MY VXd0yRInSd2arBtowi7+Nyv3EAoh2g823hpzvY6oe+IZvRyP7DBP0ESZXMCeu+DtH/ n7IfaNRFil+VwRAl1Wezf5j20edWEaH5GevqIjT4= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w589pQZc004975 for ; Fri, 8 Jun 2018 04:51:26 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 8 Jun 2018 04:51:26 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 8 Jun 2018 04:51:26 -0500 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w589pNmm023866; Fri, 8 Jun 2018 04:51:25 -0500 From: Tomi Valkeinen To: , Lokesh Vutla Date: Fri, 8 Jun 2018 12:51:20 +0300 Message-ID: <20180608095120.10875-2-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180608095120.10875-1-tomi.valkeinen@ti.com> References: <20180608095120.10875-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Mailman-Approved-At: Fri, 08 Jun 2018 10:34:16 +0000 Cc: Tomi Valkeinen Subject: [U-Boot] [PATCH 2/2] dra76: fix HDMI HPD pinmux X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The pin used for HDMI HPD should be set to GPIO mode on DRA76, similarly to all the other DRA7 and AM5 SoCs. Signed-off-by: Tomi Valkeinen --- board/ti/dra7xx/mux_data.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 7624152afb..f1f6bd5316 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -858,7 +858,7 @@ const struct pad_conf_entry dra76x_core_padconf_array[] = { {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */ {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */ {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */ - {SPI1_CS2, (M6 | 0x000f0000)}, /* spi1_cs2.hdmi1_hpd */ + {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */ {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */ {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */