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[81.169.180.215]) by mx.google.com with ESMTP id g61-v6si4565925ede.420.2018.06.11.03.54.02; Mon, 11 Jun 2018 03:54:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=IPJ72tdy; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 31606C21E12; Mon, 11 Jun 2018 10:53:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id EF176C21D72; Mon, 11 Jun 2018 10:52:54 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3F532C21C27; Mon, 11 Jun 2018 04:43:33 +0000 (UTC) Received: from mail-pf0-f196.google.com (mail-pf0-f196.google.com [209.85.192.196]) by lists.denx.de (Postfix) with ESMTPS id E9868C21BE5 for ; Mon, 11 Jun 2018 04:43:31 +0000 (UTC) Received: by mail-pf0-f196.google.com with SMTP id q1-v6so9545422pff.13 for ; Sun, 10 Jun 2018 21:43:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7bGRGmCRcrjmX7BvvOf4/7Shw8EKwF0SBEYrggTl5x4=; b=IPJ72tdylSdlCAwdgyuqKeTG2lqp2xn7Thc5hkQdgvN98AvJp1yVhXDiSLVquZB93H Mrvs/CjbFEWIjBPnKC7xREMIfDX2nCHcIDLUG0cbrE4hJ3FE/u/6o8Sidr1X812XDAoY j3OLlbKULj1w8ZtXhWcgxBGn7M6lb+qwehZJ0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7bGRGmCRcrjmX7BvvOf4/7Shw8EKwF0SBEYrggTl5x4=; b=c7C8g6xeaPWDRtl1K8wE3G1n2u1JeA8KKZ8us1qNdzbVAeIRkt4Izd6ynh9C7207BM if35f4S+gfAdtKU+SGzhIS+Dl1N5ajD4K1TWKRNssrk8msTwm1wY+K5e5X9JH0YO+1FX qJuoqE41jk3haod+wTIzCpT2un8JQRRLKpHB92AjcRU9/TARHMG+5dGOx8VB12wxVMRz JJ+uy6VEL3dBmrSabECKlIE+LgKdVkYTMi/8ouN0yyOiPJECTO8u75ZdbiyZKZcVRQmI /1oxUlG2B+Ymr0HQrP7FaNtq/XqkJIftNgepP83O3s3ePONU9z7DukzLBhVesxCInKa9 QOJg== X-Gm-Message-State: APt69E0XX0P3P7QqzeTIF9wB2h0PM5i296hHYH+f5h9U9jdkE7RpnLYu Q/uu33S+fU8os69VXLGejld3pxYi3w== X-Received: by 2002:a63:a809:: with SMTP id o9-v6mr13676207pgf.313.1528692209935; Sun, 10 Jun 2018 21:43:29 -0700 (PDT) Received: from localhost.localdomain ([2405:204:714c:560c:5161:793c:10bb:7502]) by smtp.gmail.com with ESMTPSA id j15-v6sm35232298pgv.17.2018.06.10.21.43.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 10 Jun 2018 21:43:29 -0700 (PDT) From: Manivannan Sadhasivam To: u-boot@lists.denx.de Date: Mon, 11 Jun 2018 10:12:57 +0530 Message-Id: <20180611044305.4009-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180611044305.4009-1-manivannan.sadhasivam@linaro.org> References: <20180611044305.4009-1-manivannan.sadhasivam@linaro.org> X-Mailman-Approved-At: Mon, 11 Jun 2018 10:52:50 +0000 Cc: daniel.thompson@linaro.org, bdong@ucrobotics.com, thomas.liau@actions-semi.com, hzhang@ucrobotics.com, amit.kucheria@linaro.org, liuwei@actions-semi.com, afaerber@suse.de, jeff.chen@actions-semi.com, mp-cs@actions-semi.com Subject: [U-Boot] [PATCH 1/9] arm: Add support for Actions Semi OWL SoC family X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This commit adds Actions Semi OWL SoC family support with S900 as the first target SoC. Signed-off-by: Manivannan Sadhasivam --- arch/arm/Kconfig | 9 +++++++++ arch/arm/Makefile | 1 + arch/arm/dts/s900.dtsi | 23 +++++++++++++++++++++++ arch/arm/mach-owl/Kconfig | 6 ++++++ arch/arm/mach-owl/Makefile | 3 +++ arch/arm/mach-owl/sysmap-s900.c | 32 ++++++++++++++++++++++++++++++++ 6 files changed, 74 insertions(+) create mode 100644 arch/arm/dts/s900.dtsi create mode 100644 arch/arm/mach-owl/Kconfig create mode 100644 arch/arm/mach-owl/Makefile create mode 100644 arch/arm/mach-owl/sysmap-s900.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index dde422bc5d..ec0bb5a42b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -699,6 +699,13 @@ config ARCH_MX5 select BOARD_EARLY_INIT_F imply MXC_GPIO +config ARCH_OWL + bool "Actions Semi OWL SoCs" + select ARM64 + select DM + select DM_SERIAL + select OF_CONTROL + config ARCH_QEMU bool "QEMU Virtual Platform" select DM @@ -1335,6 +1342,8 @@ source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig" source "arch/arm/mach-orion5x/Kconfig" +source "arch/arm/mach-owl/Kconfig" + source "arch/arm/mach-rmobile/Kconfig" source "arch/arm/mach-meson/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 680c6e8516..f15b2287df 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -66,6 +66,7 @@ machine-$(CONFIG_ARCH_MVEBU) += mvebu # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X machine-$(CONFIG_ORION5X) += orion5x machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2 +machine-$(CONFIG_ARCH_OWL) += owl machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx machine-$(CONFIG_ARCH_SUNXI) += sunxi machine-$(CONFIG_ARCH_SNAPDRAGON) += snapdragon diff --git a/arch/arm/dts/s900.dtsi b/arch/arm/dts/s900.dtsi new file mode 100644 index 0000000000..3bd14b82d4 --- /dev/null +++ b/arch/arm/dts/s900.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Device Tree Source for Actions Semi S900 SoC +// +// Copyright (C) 2015 Actions Semi Co., Ltd. +// Copyright (C) 2018 Manivannan Sadhasivam + +/dts-v1/; + +/ { + compatible = "actions,s900"; + #address-cells = <0x2>; + #size-cells = <0x2>; + + soc { + u-boot,dm-pre-reloc; + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + }; +}; + diff --git a/arch/arm/mach-owl/Kconfig b/arch/arm/mach-owl/Kconfig new file mode 100644 index 0000000000..f695c16d1e --- /dev/null +++ b/arch/arm/mach-owl/Kconfig @@ -0,0 +1,6 @@ +if ARCH_OWL + +config SYS_SOC + default "owl" + +endif diff --git a/arch/arm/mach-owl/Makefile b/arch/arm/mach-owl/Makefile new file mode 100644 index 0000000000..1b43dc2921 --- /dev/null +++ b/arch/arm/mach-owl/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += sysmap-s900.o diff --git a/arch/arm/mach-owl/sysmap-s900.c b/arch/arm/mach-owl/sysmap-s900.c new file mode 100644 index 0000000000..f78b639740 --- /dev/null +++ b/arch/arm/mach-owl/sysmap-s900.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Actions Semi S900 Memory map + * + * Copyright (C) 2015 Actions Semi Co., Ltd. + * Copyright (C) 2018 Manivannan Sadhasivam + */ + +#include +#include + +static struct mm_region s900_mem_map[] = { + { + .virt = 0x0UL, /* DDR */ + .phys = 0x0UL, /* DDR */ + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xE0000000UL, /* Peripheral block */ + .phys = 0xE0000000UL, /* Peripheral block */ + .size = 0x08000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = s900_mem_map;