From patchwork Mon Jun 11 17:10:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 138265 Delivered-To: patches@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp4300894lji; Mon, 11 Jun 2018 10:10:15 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIEYUOy+pxCaD9LmOfmxK0TFynx0AIjAHMtrCH4PRvBLEzNzBz8/pQXMNeBcZZnQPLM1vKK X-Received: by 2002:a1c:e619:: with SMTP id d25-v6mr11441wmh.23.1528737015261; Mon, 11 Jun 2018 10:10:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528737015; cv=none; d=google.com; s=arc-20160816; b=uC/ZbxbnlQySuHa8Q8kcNvtWBn0GL+MDVFBVotNvr+c7wySprPA0S5E5VW+gi8Pfjr zdlVArUYwQbyMDMkORQEGLiX1q/cAMs1HMRc0pW7zh+0NyacgjEz2GJB4EYC8lSmb1LP Njp0m3AOJveXenGPKDoVrIVrtP2z7tUdrwyrP+tvIb7dMGidvsPfMiKY3NYt4Oq/1AYl iX3gHFrf/otOQZp86mrPrfZTg+hvowsEl3HV0tONAubwqr8N1HljiZ+8TRVz9Bda11Be f9OYDqqlbMdZFrpZzke/PJyOE/e93+WtB221vAR28g3stB49uNVA2SfnBqESVCgva6tS +JMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=F/eK0c+JfjU14C8jon9rtDRl88yXqrEzhTUAo6kXVog=; b=aLBzUiG9RhOB3ZY4WxyzKwKgMx1rU06j2a5Z8oSFwdVGdrbYnE3cEGJShw37+woNvD M/78g9BN+KQmUT4jAHPn0T6b1HQCh5B46jLXh/DPsCrR3oCfii1U7mIRtoZ8r4c0t/RH 5uB6U4OVIeA+ry+6sOPNH1DrFxLgw+7HxYRb7x2NELpFqlus4oN8218IKfwP2kKVuSKK KCptPCFB3OxqckPpbOdUtzJPbgnOMhRwDEKgh0oP3xQ4x0adTAdfY7iSCdTZsvP679d6 4QSGXxXvPg6d3pYeC4uat4SeQMQRhEUfZf/U4UgkpvACVZxuQd/cg9QV7hSGFw8rpAr8 NDQg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id n187-v6si1145769wmn.35.2018.06.11.10.10.15 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Jun 2018 10:10:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fSQKc-0007F8-PJ; Mon, 11 Jun 2018 18:10:14 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Richard Henderson , Paolo Bonzini Subject: [PATCH 3/3] exec.c: Use stn_p() and ldn_p() instead of explicit switches Date: Mon, 11 Jun 2018 18:10:07 +0100 Message-Id: <20180611171007.4165-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180611171007.4165-1-peter.maydell@linaro.org> References: <20180611171007.4165-1-peter.maydell@linaro.org> Now we have stn_p() and ldn_p() we can use them in various functions in exec.c that used to have their own switch-on-size code. Signed-off-by: Peter Maydell --- exec.c | 112 +++++---------------------------------------------------- 1 file changed, 8 insertions(+), 104 deletions(-) -- 2.17.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson diff --git a/exec.c b/exec.c index 90b47cde7b1..1fa2cdb874f 100644 --- a/exec.c +++ b/exec.c @@ -2544,22 +2544,7 @@ static void notdirty_mem_write(void *opaque, hwaddr ram_addr, memory_notdirty_write_prepare(&ndi, current_cpu, current_cpu->mem_io_vaddr, ram_addr, size); - switch (size) { - case 1: - stb_p(qemu_map_ram_ptr(NULL, ram_addr), val); - break; - case 2: - stw_p(qemu_map_ram_ptr(NULL, ram_addr), val); - break; - case 4: - stl_p(qemu_map_ram_ptr(NULL, ram_addr), val); - break; - case 8: - stq_p(qemu_map_ram_ptr(NULL, ram_addr), val); - break; - default: - abort(); - } + stn_p(qemu_map_ram_ptr(NULL, ram_addr), size, val); memory_notdirty_write_complete(&ndi); } @@ -2739,22 +2724,8 @@ static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data, if (res) { return res; } - switch (len) { - case 1: - *data = ldub_p(buf); - return MEMTX_OK; - case 2: - *data = lduw_p(buf); - return MEMTX_OK; - case 4: - *data = (uint32_t)ldl_p(buf); - return MEMTX_OK; - case 8: - *data = ldq_p(buf); - return MEMTX_OK; - default: - abort(); - } + *data = ldn_p(buf, len); + return MEMTX_OK; } static MemTxResult subpage_write(void *opaque, hwaddr addr, @@ -2768,22 +2739,7 @@ static MemTxResult subpage_write(void *opaque, hwaddr addr, " value %"PRIx64"\n", __func__, subpage, len, addr, value); #endif - switch (len) { - case 1: - stb_p(buf, value); - break; - case 2: - stw_p(buf, value); - break; - case 4: - stl_p(buf, value); - break; - case 8: - stq_p(buf, value); - break; - default: - abort(); - } + stn_p(buf, len, value); return flatview_write(subpage->fv, addr + subpage->base, attrs, buf, len); } @@ -3129,34 +3085,8 @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr, l = memory_access_size(mr, l, addr1); /* XXX: could force current_cpu to NULL to avoid potential bugs */ - switch (l) { - case 8: - /* 64 bit write access */ - val = ldq_p(buf); - result |= memory_region_dispatch_write(mr, addr1, val, 8, - attrs); - break; - case 4: - /* 32 bit write access */ - val = (uint32_t)ldl_p(buf); - result |= memory_region_dispatch_write(mr, addr1, val, 4, - attrs); - break; - case 2: - /* 16 bit write access */ - val = lduw_p(buf); - result |= memory_region_dispatch_write(mr, addr1, val, 2, - attrs); - break; - case 1: - /* 8 bit write access */ - val = ldub_p(buf); - result |= memory_region_dispatch_write(mr, addr1, val, 1, - attrs); - break; - default: - abort(); - } + val = ldn_p(buf, l); + result |= memory_region_dispatch_write(mr, addr1, val, l, attrs); } else { /* RAM case */ ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); @@ -3217,34 +3147,8 @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr, /* I/O case */ release_lock |= prepare_mmio_access(mr); l = memory_access_size(mr, l, addr1); - switch (l) { - case 8: - /* 64 bit read access */ - result |= memory_region_dispatch_read(mr, addr1, &val, 8, - attrs); - stq_p(buf, val); - break; - case 4: - /* 32 bit read access */ - result |= memory_region_dispatch_read(mr, addr1, &val, 4, - attrs); - stl_p(buf, val); - break; - case 2: - /* 16 bit read access */ - result |= memory_region_dispatch_read(mr, addr1, &val, 2, - attrs); - stw_p(buf, val); - break; - case 1: - /* 8 bit read access */ - result |= memory_region_dispatch_read(mr, addr1, &val, 1, - attrs); - stb_p(buf, val); - break; - default: - abort(); - } + result |= memory_region_dispatch_read(mr, addr1, &val, l, attrs); + stn_p(buf, l, val); } else { /* RAM case */ ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);