From patchwork Wed Jun 13 08:09:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 138427 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp401692lji; Wed, 13 Jun 2018 01:09:17 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIczualkBIMQlBQuEtsdYNbqJCrWDtY5SZ5EvrMtv1CBPuKR9ZyLxFG7IOSKec4OLr72QoW X-Received: by 2002:a17:902:6b84:: with SMTP id p4-v6mr4070479plk.272.1528877356911; Wed, 13 Jun 2018 01:09:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528877356; cv=none; d=google.com; s=arc-20160816; b=H1ikkttMq86VsAoBjcPNC2PooOVRdRPaRZpYvOioMkyigpaFi+pBtqFl0eF4xnycOQ J5NQhnKqn66noWiWg2UJVqOnf7pf5Bgq+cdlj4vNnjwmyAwaKYX+Ns1FI5kj9fZJnzps puOdvMqyT88x0XZSZez0SX37zbRMxyls/PTVz02YH01Shnq+z+JAI739Z+9ozmYVE3Tr gYvlRK0PrF45fjgTPTp41DTO+mNM/lkOH53jswJkPPVlFwwBU4Nko8eugzP/uYnDI5fj KOl7AoZ2CA23fs9FecwEKbcjJj5tGgcOe/RzimgxHSXvv2VpkoI1x6MYa0kygLqMZA0Q ECtw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=1gkKPswNFz16Zyl9l0pqUfBUHG6IEHIp5SvnLZOi4dE=; b=hcJtx33ndspDzMbfjX1M1z+QIRQxEUZcFLOVsZAErGUEt4dl8FY0N6H6ofhDuRGYjs IZWLwrBG9kdE02z9G2Y4AdzNgbcYf1x2C9zWabo7iRuCT67HvimK6ibAUCgsjlZOafz7 f5lp0wEE2a/dZK6wsjIhPDifcWyS6hW5AOi28Ic/olk6Wz5o9eweS4pnXpxjs3yL0LVZ Ru6pVhWiwAa2AINqjGBnCqg6X8QKj7H0C8JKfu+KABsg8Wd8gqk1hyUcyYqFDsP9L7PC PtVIG+1qHh+VToj+fIXobs0xloGc0WBCZjpL8e2XvJE8y6clUr7a7N6Iy2PPoN86ryEf rBgg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=WnQY6d3W; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id p18-v6si1807126pgu.671.2018.06.13.01.09.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 13 Jun 2018 01:09:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=WnQY6d3W; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3C497211E00ED; Wed, 13 Jun 2018 01:09:13 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::231; helo=mail-wr0-x231.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x231.google.com (mail-wr0-x231.google.com [IPv6:2a00:1450:400c:c0c::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 95BE4226612DB for ; Wed, 13 Jun 2018 01:09:11 -0700 (PDT) Received: by mail-wr0-x231.google.com with SMTP id e18-v6so1694218wrs.5 for ; Wed, 13 Jun 2018 01:09:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MymDKa3gGQke6glFvCyLm6c+eSZPG5i3Z0yqNFbX1mQ=; b=WnQY6d3WwPUpywe34aMhhtqzO16I3L1jiYUtBzGyNTkyqOjuM5WnrkIjBNif0uvTT8 +0ITMy7eCPCzbiRvckCZav2uhwt6+m5V7js5ZLkpoqHJI8QBJpZW64apzXPRH4otp+g9 jh//p0ZWCwKKawPXtxV+35/CIqkudds23uLBw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MymDKa3gGQke6glFvCyLm6c+eSZPG5i3Z0yqNFbX1mQ=; b=plfheYWopjQNddWzSKvgXOyY0H6B6fw5Ho9RmJ9QbqIFSwAPcAyVLh1xWDDQfi2/H9 ACdek0szGEwNXQOeBNKdtGuPg2mSy98xJsRu4AR4+NMp9xRiUqgl6Os+zqdgSKCQlu6P +ueIN4X6AkhunthQ70xBoPpNXnTPu3rZZnWDsxPCUuk2+qFbXWy2M4qYqvWMrTqa2NGQ q+deknDSVsBNlD5tG21u446B42AAJFccyGR/illo9uw7tqzMRFUgK9DGdtiCHC9qiLb1 KiVxVvj0j0hbvMRGmNulFs5zqNzbld4sPmvM82sbOyL7kaiDhgiZsjXzDIIcaihxWgwW ghfw== X-Gm-Message-State: APt69E06WqA4+xR4UYsLvW19diFdOp2orr0cmbM6CjXOfndInDtTRqrl zNkrnkt+nhY04osYc4yj6H692H5yWaA= X-Received: by 2002:adf:b219:: with SMTP id u25-v6mr3333193wra.1.1528877349893; Wed, 13 Jun 2018 01:09:09 -0700 (PDT) Received: from dogfood.home ([2a01:cb1d:112:6f00:6dfc:b76c:4240:35ff]) by smtp.gmail.com with ESMTPSA id v31-v6sm4974772wrc.80.2018.06.13.01.09.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 13 Jun 2018 01:09:08 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 13 Jun 2018 10:09:01 +0200 Message-Id: <20180613080901.7156-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180613080901.7156-1-ard.biesheuvel@linaro.org> References: <20180613080901.7156-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v4 4/4] ArmPkg/ArmSmcPsciResetSystemLib: implement fallback for warm reboot X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: michael.d.kinney@intel.com, jiewen.yao@intel.com, star.zeng@intel.com, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Implement ResetSystemLib's EnterS3WithImmediateWake() routine using a jump back to the PEI entry point with interrupts and MMU+caches disabled. This is only possible at boot time, when we are sure that the current CPU is the only one up and running. Also, it depends on the platform whether the PEI code is preserved in memory (it may be copied to DRAM rather than execute in place), so also add a feature PCD to selectively enable this feature. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/ArmPkg.dec | 4 ++++ ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c | 21 ++++++++++++++++++-- ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf | 9 +++++++++ 3 files changed, 32 insertions(+), 2 deletions(-) -- 2.17.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec index debe066b6f7b..3aa229fe2ec9 100644 --- a/ArmPkg/ArmPkg.dec +++ b/ArmPkg/ArmPkg.dec @@ -85,6 +85,10 @@ [PcdsFeatureFlag.common] # Define if the GICv3 controller should use the GICv2 legacy gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042 + # Whether to implement warm reboot for capsule update using a jump back to the + # PEI entry point with caches and interrupts disabled. + gArmTokenSpaceGuid.PcdArmReenterPeiForCapsuleWarmReboot|FALSE|BOOLEAN|0x0000001F + [PcdsFeatureFlag.ARM] # Whether to map normal memory as non-shareable. FALSE is the safe choice, but # TRUE may be appropriate to fix performance problems if you don't care about diff --git a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c index d6d26bce5009..10ceafd14d5d 100644 --- a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c +++ b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c @@ -15,10 +15,13 @@ #include +#include +#include #include #include #include -#include +#include +#include #include @@ -89,7 +92,21 @@ EnterS3WithImmediateWake ( VOID ) { - // Not implemented + VOID (*Reset)(VOID); + + if (FeaturePcdGet (PcdArmReenterPeiForCapsuleWarmReboot) && + !EfiAtRuntime ()) { + // + // At boot time, we are the only core running, so we can implement the + // immediate wake (which is used by capsule update) by disabling the MMU + // and interrupts, and jumping to the PEI entry point. + // + Reset = (VOID (*)(VOID))(UINTN)FixedPcdGet64 (PcdFvBaseAddress); + + gBS->RaiseTPL (TPL_HIGH_LEVEL); + ArmDisableMmu (); + Reset (); + } } /** diff --git a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf index 5a1ee976e5bc..19021cd1e8b6 100644 --- a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf +++ b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf @@ -30,6 +30,15 @@ [Packages] MdePkg/MdePkg.dec [LibraryClasses] + ArmMmuLib ArmSmcLib BaseLib DebugLib + UefiBootServicesTableLib + UefiRuntimeLib + +[FeaturePcd] + gArmTokenSpaceGuid.PcdArmReenterPeiForCapsuleWarmReboot + +[FixedPcd] + gArmTokenSpaceGuid.PcdFvBaseAddress