| Message ID | CAKdteOaOQPNUvrv8iLOAz56ZjQyzyOg3w8Tyg+qk+_Qa-isrXQ@mail.gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | [ARM] Use __ARM_ARCH instead of __ARM_ARCH__ | expand |
On 15/06/18 15:30, Christophe Lyon wrote: > Hello, > > As suggested in [1], the attached patch removes all definitions and > uses of __ARM_ARCH__ and uses __ARM_ARCH instead. The later is indeed > defined by the preprocessor to the appropriate value. > > I ran make check on arm-none-eabi (with A-profile multilib), > arm-none-linux-gnueabi, arm-none-linux-gnueabihf (with cortex-a9, a15, > a5, a57 and armtdmi as --with-cpu), armeb-none-linux-gnueabihf and > armv8l-linux-gnueabihf, and noticed no regression. > > OK for trunk? > > Thanks, > > Christophe > > [1] https://gcc.gnu.org/ml/gcc-patches/2018-06/msg00445.html > > > ARM_ARCH.chlog.txt > > > libatomic/ChangeLog: > > 2018-06-15 Christophe Lyon <christophe.lyon@linaro.org> > > * config/arm/arm-config.h (__ARM_ARCH__): Remove definitions, use > __ARM_ARCH instead. > > libgcc/ChangeLog: > > 2018-06-15 Christophe Lyon <christophe.lyon@linaro.org> > > * config/arm/lib1funcs.S (__ARM_ARCH__): Remove definitions, use > __ARM_ARCH instead. > * config/arm/ieee754-df.S: Use __ARM_ARCH instead of __ARM_ARCH__. > * config/arm/ieee754-sf.S: Likewise. > * config/arm/libunwind.S: Likewise. > > > ARM_ARCH.patch.txt > Thanks, this is a useful start. We can, however, go further. ACLE defines a number of 'feature' pre-defines and we can use those to void direct tests of the architecture version directly. For example, __ARM_FEATURE_LDREX could directly replace having to calculate HAVE_STREX and HAVE_STREXBHD. From a quick look it looks like the only one we can't really support with the new tests is the check for DMB. I'll have a chat with the ACLE maintainers about that... R. > > diff --git a/libatomic/config/arm/arm-config.h b/libatomic/config/arm/arm-config.h > index c0504be..ce8ff0e 100644 > --- a/libatomic/config/arm/arm-config.h > +++ b/libatomic/config/arm/arm-config.h > @@ -23,57 +23,15 @@ > <http://www.gnu.org/licenses/>. */ > > > -#if defined(__ARM_ARCH_2__) > -# define __ARM_ARCH__ 2 > -#endif > - > -#if defined(__ARM_ARCH_3__) > -# define __ARM_ARCH__ 3 > -#endif > - > -#if defined(__ARM_ARCH_3M__) || defined(__ARM_ARCH_4__) \ > - || defined(__ARM_ARCH_4T__) > -/* We use __ARM_ARCH__ set to 4 here, but in reality it's any processor with > - long multiply instructions. That includes v3M. */ > -# define __ARM_ARCH__ 4 > -#endif > - > -#if defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__) \ > - || defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \ > - || defined(__ARM_ARCH_5TEJ__) > -# define __ARM_ARCH__ 5 > -#endif > - > -#if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \ > - || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) \ > - || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) \ > - || defined(__ARM_ARCH_6M__) > -# define __ARM_ARCH__ 6 > -#endif > - > -#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \ > - || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \ > - || defined(__ARM_ARCH_7EM__) > -# define __ARM_ARCH__ 7 > -#endif > - > -#if defined(__ARM_ARCH_8A__) > -# define __ARM_ARCH__ 8 > -#endif > - > -#ifndef __ARM_ARCH__ > -#error Unable to determine architecture. > -#endif > - > -#if __ARM_ARCH__ >= 7 || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6ZK__) > +#if __ARM_ARCH >= 7 || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6ZK__) > # define HAVE_STREX 1 > # define HAVE_STREXBHD 1 > -#elif __ARM_ARCH__ == 6 > +#elif __ARM_ARCH == 6 > # define HAVE_STREX 1 > #endif > > -#if __ARM_ARCH__ >= 7 > +#if __ARM_ARCH >= 7 > # define HAVE_DMB 1 > -#elif __ARM_ARCH__ == 6 > +#elif __ARM_ARCH == 6 > # define HAVE_DMB_MCR 1 > #endif > diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S > index 04c1b77..264d54a 100644 > --- a/libgcc/config/arm/lib1funcs.S > +++ b/libgcc/config/arm/lib1funcs.S > @@ -74,49 +74,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see > > /* Function end macros. Variants for interworking. */ > > -#if defined(__ARM_ARCH_2__) > -# define __ARM_ARCH__ 2 > -#endif > - > -#if defined(__ARM_ARCH_3__) > -# define __ARM_ARCH__ 3 > -#endif > - > -#if defined(__ARM_ARCH_3M__) || defined(__ARM_ARCH_4__) \ > - || defined(__ARM_ARCH_4T__) > -/* We use __ARM_ARCH__ set to 4 here, but in reality it's any processor with > - long multiply instructions. That includes v3M. */ > -# define __ARM_ARCH__ 4 > -#endif > - > -#if defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__) \ > - || defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \ > - || defined(__ARM_ARCH_5TEJ__) > -# define __ARM_ARCH__ 5 > -#endif > - > -#if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \ > - || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) \ > - || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) \ > - || defined(__ARM_ARCH_6M__) > -# define __ARM_ARCH__ 6 > -#endif > - > -#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \ > - || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \ > - || defined(__ARM_ARCH_7EM__) > -# define __ARM_ARCH__ 7 > -#endif > - > -#if defined(__ARM_ARCH_8A__) || defined(__ARM_ARCH_8M_BASE__) \ > - || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8R__) > -# define __ARM_ARCH__ 8 > -#endif > - > -#ifndef __ARM_ARCH__ > -#error Unable to determine architecture. > -#endif > - > /* There are times when we might prefer Thumb1 code even if ARM code is > permitted, for example, the code might be smaller, or there might be > interworking problems with switching to ARM state if interworking is > @@ -135,13 +92,13 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see > > /* How to return from a function call depends on the architecture variant. */ > > -#if (__ARM_ARCH__ > 4) || defined(__ARM_ARCH_4T__) > +#if (__ARM_ARCH > 4) || defined(__ARM_ARCH_4T__) > > # define RET bx lr > # define RETc(x) bx##x lr > > /* Special precautions for interworking on armv4t. */ > -# if (__ARM_ARCH__ == 4) > +# if (__ARM_ARCH == 4) > > /* Always use bx, not ldr pc. */ > # if (defined(__thumb__) || defined(__THUMB_INTERWORK__)) > @@ -544,7 +501,7 @@ pc .req r15 > /* ------------------------------------------------------------------------ */ > .macro ARM_DIV_BODY dividend, divisor, result, curbit > > -#if __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__) > +#if __ARM_ARCH >= 5 && ! defined (__OPTIMIZE_SIZE__) > > #if defined (__thumb2__) > clz \curbit, \dividend > @@ -584,8 +541,8 @@ pc .req r15 > .endr > #endif > > -#else /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ > -#if __ARM_ARCH__ >= 5 > +#else /* __ARM_ARCH < 5 || defined (__OPTIMIZE_SIZE__) */ > +#if __ARM_ARCH >= 5 > > clz \curbit, \divisor > clz \result, \dividend > @@ -595,7 +552,7 @@ pc .req r15 > mov \curbit, \curbit, lsl \result > mov \result, #0 > > -#else /* __ARM_ARCH__ < 5 */ > +#else /* __ARM_ARCH < 5 */ > > @ Initially shift the divisor left 3 bits if possible, > @ set curbit accordingly. This allows for curbit to be located > @@ -626,7 +583,7 @@ pc .req r15 > > mov \result, #0 > > -#endif /* __ARM_ARCH__ < 5 */ > +#endif /* __ARM_ARCH < 5 */ > > @ Division loop > 1: cmp \dividend, \divisor > @@ -651,13 +608,13 @@ pc .req r15 > movne \divisor, \divisor, lsr #4 > bne 1b > > -#endif /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ > +#endif /* __ARM_ARCH < 5 || defined (__OPTIMIZE_SIZE__) */ > > .endm > /* ------------------------------------------------------------------------ */ > .macro ARM_DIV2_ORDER divisor, order > > -#if __ARM_ARCH__ >= 5 > +#if __ARM_ARCH >= 5 > > clz \order, \divisor > rsb \order, \order, #31 > @@ -687,7 +644,7 @@ pc .req r15 > /* ------------------------------------------------------------------------ */ > .macro ARM_MOD_BODY dividend, divisor, order, spare > > -#if __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__) > +#if __ARM_ARCH >= 5 && ! defined (__OPTIMIZE_SIZE__) > > clz \order, \divisor > clz \spare, \dividend > @@ -702,15 +659,15 @@ pc .req r15 > subcs \dividend, \dividend, \divisor, lsl #shift > .endr > > -#else /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ > -#if __ARM_ARCH__ >= 5 > +#else /* __ARM_ARCH < 5 || defined (__OPTIMIZE_SIZE__) */ > +#if __ARM_ARCH >= 5 > > clz \order, \divisor > clz \spare, \dividend > sub \order, \order, \spare > mov \divisor, \divisor, lsl \order > > -#else /* __ARM_ARCH__ < 5 */ > +#else /* __ARM_ARCH < 5 */ > > mov \order, #0 > > @@ -732,7 +689,7 @@ pc .req r15 > addlo \order, \order, #1 > blo 1b > > -#endif /* __ARM_ARCH__ < 5 */ > +#endif /* __ARM_ARCH < 5 */ > > @ Perform all needed substractions to keep only the reminder. > @ Do comparisons in batch of 4 first. > @@ -770,7 +727,7 @@ pc .req r15 > subhs \dividend, \dividend, \divisor > 5: > > -#endif /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ > +#endif /* __ARM_ARCH < 5 || defined (__OPTIMIZE_SIZE__) */ > > .endm > /* ------------------------------------------------------------------------ */ > @@ -1560,7 +1517,7 @@ LSYM(Lover12): > @ EABI GNU/Linux call to cacheflush syscall. > ARM_FUNC_START clear_cache > do_push {r7} > -#if __ARM_ARCH__ >= 7 || defined(__ARM_ARCH_6T2__) > +#if __ARM_ARCH >= 7 || defined(__ARM_ARCH_6T2__) > movw r7, #2 > movt r7, #0xf > #else > @@ -1701,8 +1658,8 @@ LSYM(Lover12): > > #if (__ARM_ARCH_ISA_THUMB == 2 \ > || (__ARM_ARCH_ISA_ARM \ > - && (__ARM_ARCH__ > 5 \ > - || (__ARM_ARCH__ == 5 && __ARM_ARCH_ISA_THUMB)))) > + && (__ARM_ARCH > 5 \ > + || (__ARM_ARCH == 5 && __ARM_ARCH_ISA_THUMB)))) > #define HAVE_ARM_CLZ 1 > #endif > > @@ -1887,7 +1844,7 @@ ARM_FUNC_START ctzsi2 > not support Thumb instructions. (This can be a multilib option). */ > #if defined __ARM_ARCH_4T__ || defined __ARM_ARCH_5T__\ > || defined __ARM_ARCH_5TE__ || defined __ARM_ARCH_5TEJ__ \ > - || __ARM_ARCH__ >= 6 > + || __ARM_ARCH >= 6 > > #if defined L_call_via_rX > > diff --git a/libgcc/config/arm/ieee754-df.S b/libgcc/config/arm/ieee754-df.S > index 570e5f6..7c5260e 100644 > --- a/libgcc/config/arm/ieee754-df.S > +++ b/libgcc/config/arm/ieee754-df.S > @@ -245,7 +245,7 @@ LSYM(Lad_a): > @ No rounding necessary since ip will always be 0 at this point. > LSYM(Lad_l): > > -#if __ARM_ARCH__ < 5 > +#if __ARM_ARCH < 5 > > teq xh, #0 > movne r3, #20 > @@ -656,7 +656,7 @@ ARM_FUNC_ALIAS aeabi_dmul muldf3 > orr yh, yh, #0x00100000 > beq LSYM(Lml_1) > > -#if __ARM_ARCH__ < 4 > +#if __ARM_ARCH < 4 > > @ Put sign bit in r6, which will be restored in yl later. > and r6, r6, #0x80000000 > diff --git a/libgcc/config/arm/ieee754-sf.S b/libgcc/config/arm/ieee754-sf.S > index dac3e2e..00a8d9c 100644 > --- a/libgcc/config/arm/ieee754-sf.S > +++ b/libgcc/config/arm/ieee754-sf.S > @@ -175,7 +175,7 @@ LSYM(Lad_a): > @ No rounding necessary since r1 will always be 0 at this point. > LSYM(Lad_l): > > -#if __ARM_ARCH__ < 5 > +#if __ARM_ARCH < 5 > > movs ip, r0, lsr #12 > moveq r0, r0, lsl #12 > @@ -370,7 +370,7 @@ ARM_FUNC_ALIAS aeabi_l2f floatdisf > subeq r3, r3, #(32 << 23) > 2: sub r3, r3, #(1 << 23) > > -#if __ARM_ARCH__ < 5 > +#if __ARM_ARCH < 5 > > mov r2, #23 > cmp ip, #(1 << 16) > @@ -460,7 +460,7 @@ LSYM(Lml_x): > orr r0, r3, r0, lsr #5 > orr r1, r3, r1, lsr #5 > > -#if __ARM_ARCH__ < 4 > +#if __ARM_ARCH < 4 > > @ Put sign bit in r3, which will be restored into r0 later. > and r3, ip, #0x80000000 > diff --git a/libgcc/config/arm/libunwind.S b/libgcc/config/arm/libunwind.S > index 3302447..50c58dc 100644 > --- a/libgcc/config/arm/libunwind.S > +++ b/libgcc/config/arm/libunwind.S > @@ -46,7 +46,7 @@ > EQUIV SYM (\name), SYM (__\name) > .endm > > -#if (__ARM_ARCH__ == 4) > +#if (__ARM_ARCH == 4) > /* Some coprocessors require armv5t. We know this code will never be run on > other cpus. Tell gas to allow armv5t, but only mark the objects as armv4. > */ >
On Fri, 15 Jun 2018 at 17:22, Richard Earnshaw (lists) <Richard.Earnshaw@arm.com> wrote: > > On 15/06/18 15:30, Christophe Lyon wrote: > > Hello, > > > > As suggested in [1], the attached patch removes all definitions and > > uses of __ARM_ARCH__ and uses __ARM_ARCH instead. The later is indeed > > defined by the preprocessor to the appropriate value. > > > > I ran make check on arm-none-eabi (with A-profile multilib), > > arm-none-linux-gnueabi, arm-none-linux-gnueabihf (with cortex-a9, a15, > > a5, a57 and armtdmi as --with-cpu), armeb-none-linux-gnueabihf and > > armv8l-linux-gnueabihf, and noticed no regression. > > > > OK for trunk? > > > > Thanks, > > > > Christophe > > > > [1] https://gcc.gnu.org/ml/gcc-patches/2018-06/msg00445.html > > > > > > ARM_ARCH.chlog.txt > > > > > > libatomic/ChangeLog: > > > > 2018-06-15 Christophe Lyon <christophe.lyon@linaro.org> > > > > * config/arm/arm-config.h (__ARM_ARCH__): Remove definitions, use > > __ARM_ARCH instead. > > > > libgcc/ChangeLog: > > > > 2018-06-15 Christophe Lyon <christophe.lyon@linaro.org> > > > > * config/arm/lib1funcs.S (__ARM_ARCH__): Remove definitions, use > > __ARM_ARCH instead. > > * config/arm/ieee754-df.S: Use __ARM_ARCH instead of __ARM_ARCH__. > > * config/arm/ieee754-sf.S: Likewise. > > * config/arm/libunwind.S: Likewise. > > > > > > ARM_ARCH.patch.txt > > > > Thanks, this is a useful start. We can, however, go further. ACLE > defines a number of 'feature' pre-defines and we can use those to void > direct tests of the architecture version directly. For example, > __ARM_FEATURE_LDREX could directly replace having to calculate > HAVE_STREX and HAVE_STREXBHD. > Hi, Here is an updated patch using __ARM_FEATURE_LDREX. I didn't find other opportunities to use ACLE pre-defines, did I miss any? Thanks, Christophe > From a quick look it looks like the only one we can't really support > with the new tests is the check for DMB. I'll have a chat with the ACLE > maintainers about that... > > R. > > > > > diff --git a/libatomic/config/arm/arm-config.h b/libatomic/config/arm/arm-config.h > > index c0504be..ce8ff0e 100644 > > --- a/libatomic/config/arm/arm-config.h > > +++ b/libatomic/config/arm/arm-config.h > > @@ -23,57 +23,15 @@ > > <http://www.gnu.org/licenses/>. */ > > > > > > -#if defined(__ARM_ARCH_2__) > > -# define __ARM_ARCH__ 2 > > -#endif > > - > > -#if defined(__ARM_ARCH_3__) > > -# define __ARM_ARCH__ 3 > > -#endif > > - > > -#if defined(__ARM_ARCH_3M__) || defined(__ARM_ARCH_4__) \ > > - || defined(__ARM_ARCH_4T__) > > -/* We use __ARM_ARCH__ set to 4 here, but in reality it's any processor with > > - long multiply instructions. That includes v3M. */ > > -# define __ARM_ARCH__ 4 > > -#endif > > - > > -#if defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__) \ > > - || defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \ > > - || defined(__ARM_ARCH_5TEJ__) > > -# define __ARM_ARCH__ 5 > > -#endif > > - > > -#if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \ > > - || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) \ > > - || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) \ > > - || defined(__ARM_ARCH_6M__) > > -# define __ARM_ARCH__ 6 > > -#endif > > - > > -#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \ > > - || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \ > > - || defined(__ARM_ARCH_7EM__) > > -# define __ARM_ARCH__ 7 > > -#endif > > - > > -#if defined(__ARM_ARCH_8A__) > > -# define __ARM_ARCH__ 8 > > -#endif > > - > > -#ifndef __ARM_ARCH__ > > -#error Unable to determine architecture. > > -#endif > > - > > -#if __ARM_ARCH__ >= 7 || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6ZK__) > > +#if __ARM_ARCH >= 7 || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6ZK__) > > # define HAVE_STREX 1 > > # define HAVE_STREXBHD 1 > > -#elif __ARM_ARCH__ == 6 > > +#elif __ARM_ARCH == 6 > > # define HAVE_STREX 1 > > #endif > > > > -#if __ARM_ARCH__ >= 7 > > +#if __ARM_ARCH >= 7 > > # define HAVE_DMB 1 > > -#elif __ARM_ARCH__ == 6 > > +#elif __ARM_ARCH == 6 > > # define HAVE_DMB_MCR 1 > > #endif > > diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S > > index 04c1b77..264d54a 100644 > > --- a/libgcc/config/arm/lib1funcs.S > > +++ b/libgcc/config/arm/lib1funcs.S > > @@ -74,49 +74,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see > > > > /* Function end macros. Variants for interworking. */ > > > > -#if defined(__ARM_ARCH_2__) > > -# define __ARM_ARCH__ 2 > > -#endif > > - > > -#if defined(__ARM_ARCH_3__) > > -# define __ARM_ARCH__ 3 > > -#endif > > - > > -#if defined(__ARM_ARCH_3M__) || defined(__ARM_ARCH_4__) \ > > - || defined(__ARM_ARCH_4T__) > > -/* We use __ARM_ARCH__ set to 4 here, but in reality it's any processor with > > - long multiply instructions. That includes v3M. */ > > -# define __ARM_ARCH__ 4 > > -#endif > > - > > -#if defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__) \ > > - || defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \ > > - || defined(__ARM_ARCH_5TEJ__) > > -# define __ARM_ARCH__ 5 > > -#endif > > - > > -#if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \ > > - || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) \ > > - || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) \ > > - || defined(__ARM_ARCH_6M__) > > -# define __ARM_ARCH__ 6 > > -#endif > > - > > -#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \ > > - || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \ > > - || defined(__ARM_ARCH_7EM__) > > -# define __ARM_ARCH__ 7 > > -#endif > > - > > -#if defined(__ARM_ARCH_8A__) || defined(__ARM_ARCH_8M_BASE__) \ > > - || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8R__) > > -# define __ARM_ARCH__ 8 > > -#endif > > - > > -#ifndef __ARM_ARCH__ > > -#error Unable to determine architecture. > > -#endif > > - > > /* There are times when we might prefer Thumb1 code even if ARM code is > > permitted, for example, the code might be smaller, or there might be > > interworking problems with switching to ARM state if interworking is > > @@ -135,13 +92,13 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see > > > > /* How to return from a function call depends on the architecture variant. */ > > > > -#if (__ARM_ARCH__ > 4) || defined(__ARM_ARCH_4T__) > > +#if (__ARM_ARCH > 4) || defined(__ARM_ARCH_4T__) > > > > # define RET bx lr > > # define RETc(x) bx##x lr > > > > /* Special precautions for interworking on armv4t. */ > > -# if (__ARM_ARCH__ == 4) > > +# if (__ARM_ARCH == 4) > > > > /* Always use bx, not ldr pc. */ > > # if (defined(__thumb__) || defined(__THUMB_INTERWORK__)) > > @@ -544,7 +501,7 @@ pc .req r15 > > /* ------------------------------------------------------------------------ */ > > .macro ARM_DIV_BODY dividend, divisor, result, curbit > > > > -#if __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__) > > +#if __ARM_ARCH >= 5 && ! defined (__OPTIMIZE_SIZE__) > > > > #if defined (__thumb2__) > > clz \curbit, \dividend > > @@ -584,8 +541,8 @@ pc .req r15 > > .endr > > #endif > > > > -#else /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ > > -#if __ARM_ARCH__ >= 5 > > +#else /* __ARM_ARCH < 5 || defined (__OPTIMIZE_SIZE__) */ > > +#if __ARM_ARCH >= 5 > > > > clz \curbit, \divisor > > clz \result, \dividend > > @@ -595,7 +552,7 @@ pc .req r15 > > mov \curbit, \curbit, lsl \result > > mov \result, #0 > > > > -#else /* __ARM_ARCH__ < 5 */ > > +#else /* __ARM_ARCH < 5 */ > > > > @ Initially shift the divisor left 3 bits if possible, > > @ set curbit accordingly. This allows for curbit to be located > > @@ -626,7 +583,7 @@ pc .req r15 > > > > mov \result, #0 > > > > -#endif /* __ARM_ARCH__ < 5 */ > > +#endif /* __ARM_ARCH < 5 */ > > > > @ Division loop > > 1: cmp \dividend, \divisor > > @@ -651,13 +608,13 @@ pc .req r15 > > movne \divisor, \divisor, lsr #4 > > bne 1b > > > > -#endif /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ > > +#endif /* __ARM_ARCH < 5 || defined (__OPTIMIZE_SIZE__) */ > > > > .endm > > /* ------------------------------------------------------------------------ */ > > .macro ARM_DIV2_ORDER divisor, order > > > > -#if __ARM_ARCH__ >= 5 > > +#if __ARM_ARCH >= 5 > > > > clz \order, \divisor > > rsb \order, \order, #31 > > @@ -687,7 +644,7 @@ pc .req r15 > > /* ------------------------------------------------------------------------ */ > > .macro ARM_MOD_BODY dividend, divisor, order, spare > > > > -#if __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__) > > +#if __ARM_ARCH >= 5 && ! defined (__OPTIMIZE_SIZE__) > > > > clz \order, \divisor > > clz \spare, \dividend > > @@ -702,15 +659,15 @@ pc .req r15 > > subcs \dividend, \dividend, \divisor, lsl #shift > > .endr > > > > -#else /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ > > -#if __ARM_ARCH__ >= 5 > > +#else /* __ARM_ARCH < 5 || defined (__OPTIMIZE_SIZE__) */ > > +#if __ARM_ARCH >= 5 > > > > clz \order, \divisor > > clz \spare, \dividend > > sub \order, \order, \spare > > mov \divisor, \divisor, lsl \order > > > > -#else /* __ARM_ARCH__ < 5 */ > > +#else /* __ARM_ARCH < 5 */ > > > > mov \order, #0 > > > > @@ -732,7 +689,7 @@ pc .req r15 > > addlo \order, \order, #1 > > blo 1b > > > > -#endif /* __ARM_ARCH__ < 5 */ > > +#endif /* __ARM_ARCH < 5 */ > > > > @ Perform all needed substractions to keep only the reminder. > > @ Do comparisons in batch of 4 first. > > @@ -770,7 +727,7 @@ pc .req r15 > > subhs \dividend, \dividend, \divisor > > 5: > > > > -#endif /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ > > +#endif /* __ARM_ARCH < 5 || defined (__OPTIMIZE_SIZE__) */ > > > > .endm > > /* ------------------------------------------------------------------------ */ > > @@ -1560,7 +1517,7 @@ LSYM(Lover12): > > @ EABI GNU/Linux call to cacheflush syscall. > > ARM_FUNC_START clear_cache > > do_push {r7} > > -#if __ARM_ARCH__ >= 7 || defined(__ARM_ARCH_6T2__) > > +#if __ARM_ARCH >= 7 || defined(__ARM_ARCH_6T2__) > > movw r7, #2 > > movt r7, #0xf > > #else > > @@ -1701,8 +1658,8 @@ LSYM(Lover12): > > > > #if (__ARM_ARCH_ISA_THUMB == 2 \ > > || (__ARM_ARCH_ISA_ARM \ > > - && (__ARM_ARCH__ > 5 \ > > - || (__ARM_ARCH__ == 5 && __ARM_ARCH_ISA_THUMB)))) > > + && (__ARM_ARCH > 5 \ > > + || (__ARM_ARCH == 5 && __ARM_ARCH_ISA_THUMB)))) > > #define HAVE_ARM_CLZ 1 > > #endif > > > > @@ -1887,7 +1844,7 @@ ARM_FUNC_START ctzsi2 > > not support Thumb instructions. (This can be a multilib option). */ > > #if defined __ARM_ARCH_4T__ || defined __ARM_ARCH_5T__\ > > || defined __ARM_ARCH_5TE__ || defined __ARM_ARCH_5TEJ__ \ > > - || __ARM_ARCH__ >= 6 > > + || __ARM_ARCH >= 6 > > > > #if defined L_call_via_rX > > > > diff --git a/libgcc/config/arm/ieee754-df.S b/libgcc/config/arm/ieee754-df.S > > index 570e5f6..7c5260e 100644 > > --- a/libgcc/config/arm/ieee754-df.S > > +++ b/libgcc/config/arm/ieee754-df.S > > @@ -245,7 +245,7 @@ LSYM(Lad_a): > > @ No rounding necessary since ip will always be 0 at this point. > > LSYM(Lad_l): > > > > -#if __ARM_ARCH__ < 5 > > +#if __ARM_ARCH < 5 > > > > teq xh, #0 > > movne r3, #20 > > @@ -656,7 +656,7 @@ ARM_FUNC_ALIAS aeabi_dmul muldf3 > > orr yh, yh, #0x00100000 > > beq LSYM(Lml_1) > > > > -#if __ARM_ARCH__ < 4 > > +#if __ARM_ARCH < 4 > > > > @ Put sign bit in r6, which will be restored in yl later. > > and r6, r6, #0x80000000 > > diff --git a/libgcc/config/arm/ieee754-sf.S b/libgcc/config/arm/ieee754-sf.S > > index dac3e2e..00a8d9c 100644 > > --- a/libgcc/config/arm/ieee754-sf.S > > +++ b/libgcc/config/arm/ieee754-sf.S > > @@ -175,7 +175,7 @@ LSYM(Lad_a): > > @ No rounding necessary since r1 will always be 0 at this point. > > LSYM(Lad_l): > > > > -#if __ARM_ARCH__ < 5 > > +#if __ARM_ARCH < 5 > > > > movs ip, r0, lsr #12 > > moveq r0, r0, lsl #12 > > @@ -370,7 +370,7 @@ ARM_FUNC_ALIAS aeabi_l2f floatdisf > > subeq r3, r3, #(32 << 23) > > 2: sub r3, r3, #(1 << 23) > > > > -#if __ARM_ARCH__ < 5 > > +#if __ARM_ARCH < 5 > > > > mov r2, #23 > > cmp ip, #(1 << 16) > > @@ -460,7 +460,7 @@ LSYM(Lml_x): > > orr r0, r3, r0, lsr #5 > > orr r1, r3, r1, lsr #5 > > > > -#if __ARM_ARCH__ < 4 > > +#if __ARM_ARCH < 4 > > > > @ Put sign bit in r3, which will be restored into r0 later. > > and r3, ip, #0x80000000 > > diff --git a/libgcc/config/arm/libunwind.S b/libgcc/config/arm/libunwind.S > > index 3302447..50c58dc 100644 > > --- a/libgcc/config/arm/libunwind.S > > +++ b/libgcc/config/arm/libunwind.S > > @@ -46,7 +46,7 @@ > > EQUIV SYM (\name), SYM (__\name) > > .endm > > > > -#if (__ARM_ARCH__ == 4) > > +#if (__ARM_ARCH == 4) > > /* Some coprocessors require armv5t. We know this code will never be run on > > other cpus. Tell gas to allow armv5t, but only mark the objects as armv4. > > */ > > > libatomic/ChangeLog: 2018-06-18 Christophe Lyon <christophe.lyon@linaro.org> * config/arm/arm-config.h (__ARM_ARCH__): Remove definitions, use __ARM_ARCH instead. Use __ARM_FEATURE_LDREX to define HAVE_STREX and HAVE_STREXBHD libgcc/ChangeLog: 2018-06-18 Christophe Lyon <christophe.lyon@linaro.org> * config/arm/lib1funcs.S (__ARM_ARCH__): Remove definitions, use __ARM_ARCH instead. * config/arm/ieee754-df.S: Use __ARM_ARCH instead of __ARM_ARCH__. * config/arm/ieee754-sf.S: Likewise. * config/arm/libunwind.S: Likewise. diff --git a/libatomic/config/arm/arm-config.h b/libatomic/config/arm/arm-config.h index c0504be..b4783ad 100644 --- a/libatomic/config/arm/arm-config.h +++ b/libatomic/config/arm/arm-config.h @@ -23,57 +23,15 @@ <http://www.gnu.org/licenses/>. */ -#if defined(__ARM_ARCH_2__) -# define __ARM_ARCH__ 2 -#endif - -#if defined(__ARM_ARCH_3__) -# define __ARM_ARCH__ 3 -#endif - -#if defined(__ARM_ARCH_3M__) || defined(__ARM_ARCH_4__) \ - || defined(__ARM_ARCH_4T__) -/* We use __ARM_ARCH__ set to 4 here, but in reality it's any processor with - long multiply instructions. That includes v3M. */ -# define __ARM_ARCH__ 4 -#endif - -#if defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__) \ - || defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \ - || defined(__ARM_ARCH_5TEJ__) -# define __ARM_ARCH__ 5 -#endif - -#if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \ - || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) \ - || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) \ - || defined(__ARM_ARCH_6M__) -# define __ARM_ARCH__ 6 -#endif - -#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \ - || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \ - || defined(__ARM_ARCH_7EM__) -# define __ARM_ARCH__ 7 -#endif - -#if defined(__ARM_ARCH_8A__) -# define __ARM_ARCH__ 8 -#endif - -#ifndef __ARM_ARCH__ -#error Unable to determine architecture. -#endif - -#if __ARM_ARCH__ >= 7 || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6ZK__) +#if __ARM_FEATURE_LDREX & 4 # define HAVE_STREX 1 +#endif +#if (__ARM_FEATURE_LDREX & 0xF) == 0xF # define HAVE_STREXBHD 1 -#elif __ARM_ARCH__ == 6 -# define HAVE_STREX 1 #endif -#if __ARM_ARCH__ >= 7 +#if __ARM_ARCH >= 7 # define HAVE_DMB 1 -#elif __ARM_ARCH__ == 6 +#elif __ARM_ARCH == 6 # define HAVE_DMB_MCR 1 #endif diff --git a/libgcc/config/arm/ieee754-df.S b/libgcc/config/arm/ieee754-df.S index 570e5f6..7c5260e 100644 --- a/libgcc/config/arm/ieee754-df.S +++ b/libgcc/config/arm/ieee754-df.S @@ -245,7 +245,7 @@ LSYM(Lad_a): @ No rounding necessary since ip will always be 0 at this point. LSYM(Lad_l): -#if __ARM_ARCH__ < 5 +#if __ARM_ARCH < 5 teq xh, #0 movne r3, #20 @@ -656,7 +656,7 @@ ARM_FUNC_ALIAS aeabi_dmul muldf3 orr yh, yh, #0x00100000 beq LSYM(Lml_1) -#if __ARM_ARCH__ < 4 +#if __ARM_ARCH < 4 @ Put sign bit in r6, which will be restored in yl later. and r6, r6, #0x80000000 diff --git a/libgcc/config/arm/ieee754-sf.S b/libgcc/config/arm/ieee754-sf.S index dac3e2e..00a8d9c 100644 --- a/libgcc/config/arm/ieee754-sf.S +++ b/libgcc/config/arm/ieee754-sf.S @@ -175,7 +175,7 @@ LSYM(Lad_a): @ No rounding necessary since r1 will always be 0 at this point. LSYM(Lad_l): -#if __ARM_ARCH__ < 5 +#if __ARM_ARCH < 5 movs ip, r0, lsr #12 moveq r0, r0, lsl #12 @@ -370,7 +370,7 @@ ARM_FUNC_ALIAS aeabi_l2f floatdisf subeq r3, r3, #(32 << 23) 2: sub r3, r3, #(1 << 23) -#if __ARM_ARCH__ < 5 +#if __ARM_ARCH < 5 mov r2, #23 cmp ip, #(1 << 16) @@ -460,7 +460,7 @@ LSYM(Lml_x): orr r0, r3, r0, lsr #5 orr r1, r3, r1, lsr #5 -#if __ARM_ARCH__ < 4 +#if __ARM_ARCH < 4 @ Put sign bit in r3, which will be restored into r0 later. and r3, ip, #0x80000000 diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S index 04c1b77..264d54a 100644 --- a/libgcc/config/arm/lib1funcs.S +++ b/libgcc/config/arm/lib1funcs.S @@ -74,49 +74,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see /* Function end macros. Variants for interworking. */ -#if defined(__ARM_ARCH_2__) -# define __ARM_ARCH__ 2 -#endif - -#if defined(__ARM_ARCH_3__) -# define __ARM_ARCH__ 3 -#endif - -#if defined(__ARM_ARCH_3M__) || defined(__ARM_ARCH_4__) \ - || defined(__ARM_ARCH_4T__) -/* We use __ARM_ARCH__ set to 4 here, but in reality it's any processor with - long multiply instructions. That includes v3M. */ -# define __ARM_ARCH__ 4 -#endif - -#if defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__) \ - || defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \ - || defined(__ARM_ARCH_5TEJ__) -# define __ARM_ARCH__ 5 -#endif - -#if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \ - || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) \ - || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) \ - || defined(__ARM_ARCH_6M__) -# define __ARM_ARCH__ 6 -#endif - -#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \ - || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \ - || defined(__ARM_ARCH_7EM__) -# define __ARM_ARCH__ 7 -#endif - -#if defined(__ARM_ARCH_8A__) || defined(__ARM_ARCH_8M_BASE__) \ - || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8R__) -# define __ARM_ARCH__ 8 -#endif - -#ifndef __ARM_ARCH__ -#error Unable to determine architecture. -#endif - /* There are times when we might prefer Thumb1 code even if ARM code is permitted, for example, the code might be smaller, or there might be interworking problems with switching to ARM state if interworking is @@ -135,13 +92,13 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see /* How to return from a function call depends on the architecture variant. */ -#if (__ARM_ARCH__ > 4) || defined(__ARM_ARCH_4T__) +#if (__ARM_ARCH > 4) || defined(__ARM_ARCH_4T__) # define RET bx lr # define RETc(x) bx##x lr /* Special precautions for interworking on armv4t. */ -# if (__ARM_ARCH__ == 4) +# if (__ARM_ARCH == 4) /* Always use bx, not ldr pc. */ # if (defined(__thumb__) || defined(__THUMB_INTERWORK__)) @@ -544,7 +501,7 @@ pc .req r15 /* ------------------------------------------------------------------------ */ .macro ARM_DIV_BODY dividend, divisor, result, curbit -#if __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__) +#if __ARM_ARCH >= 5 && ! defined (__OPTIMIZE_SIZE__) #if defined (__thumb2__) clz \curbit, \dividend @@ -584,8 +541,8 @@ pc .req r15 .endr #endif -#else /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ -#if __ARM_ARCH__ >= 5 +#else /* __ARM_ARCH < 5 || defined (__OPTIMIZE_SIZE__) */ +#if __ARM_ARCH >= 5 clz \curbit, \divisor clz \result, \dividend @@ -595,7 +552,7 @@ pc .req r15 mov \curbit, \curbit, lsl \result mov \result, #0 -#else /* __ARM_ARCH__ < 5 */ +#else /* __ARM_ARCH < 5 */ @ Initially shift the divisor left 3 bits if possible, @ set curbit accordingly. This allows for curbit to be located @@ -626,7 +583,7 @@ pc .req r15 mov \result, #0 -#endif /* __ARM_ARCH__ < 5 */ +#endif /* __ARM_ARCH < 5 */ @ Division loop 1: cmp \dividend, \divisor @@ -651,13 +608,13 @@ pc .req r15 movne \divisor, \divisor, lsr #4 bne 1b -#endif /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ +#endif /* __ARM_ARCH < 5 || defined (__OPTIMIZE_SIZE__) */ .endm /* ------------------------------------------------------------------------ */ .macro ARM_DIV2_ORDER divisor, order -#if __ARM_ARCH__ >= 5 +#if __ARM_ARCH >= 5 clz \order, \divisor rsb \order, \order, #31 @@ -687,7 +644,7 @@ pc .req r15 /* ------------------------------------------------------------------------ */ .macro ARM_MOD_BODY dividend, divisor, order, spare -#if __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__) +#if __ARM_ARCH >= 5 && ! defined (__OPTIMIZE_SIZE__) clz \order, \divisor clz \spare, \dividend @@ -702,15 +659,15 @@ pc .req r15 subcs \dividend, \dividend, \divisor, lsl #shift .endr -#else /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ -#if __ARM_ARCH__ >= 5 +#else /* __ARM_ARCH < 5 || defined (__OPTIMIZE_SIZE__) */ +#if __ARM_ARCH >= 5 clz \order, \divisor clz \spare, \dividend sub \order, \order, \spare mov \divisor, \divisor, lsl \order -#else /* __ARM_ARCH__ < 5 */ +#else /* __ARM_ARCH < 5 */ mov \order, #0 @@ -732,7 +689,7 @@ pc .req r15 addlo \order, \order, #1 blo 1b -#endif /* __ARM_ARCH__ < 5 */ +#endif /* __ARM_ARCH < 5 */ @ Perform all needed substractions to keep only the reminder. @ Do comparisons in batch of 4 first. @@ -770,7 +727,7 @@ pc .req r15 subhs \dividend, \dividend, \divisor 5: -#endif /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ +#endif /* __ARM_ARCH < 5 || defined (__OPTIMIZE_SIZE__) */ .endm /* ------------------------------------------------------------------------ */ @@ -1560,7 +1517,7 @@ LSYM(Lover12): @ EABI GNU/Linux call to cacheflush syscall. ARM_FUNC_START clear_cache do_push {r7} -#if __ARM_ARCH__ >= 7 || defined(__ARM_ARCH_6T2__) +#if __ARM_ARCH >= 7 || defined(__ARM_ARCH_6T2__) movw r7, #2 movt r7, #0xf #else @@ -1701,8 +1658,8 @@ LSYM(Lover12): #if (__ARM_ARCH_ISA_THUMB == 2 \ || (__ARM_ARCH_ISA_ARM \ - && (__ARM_ARCH__ > 5 \ - || (__ARM_ARCH__ == 5 && __ARM_ARCH_ISA_THUMB)))) + && (__ARM_ARCH > 5 \ + || (__ARM_ARCH == 5 && __ARM_ARCH_ISA_THUMB)))) #define HAVE_ARM_CLZ 1 #endif @@ -1887,7 +1844,7 @@ ARM_FUNC_START ctzsi2 not support Thumb instructions. (This can be a multilib option). */ #if defined __ARM_ARCH_4T__ || defined __ARM_ARCH_5T__\ || defined __ARM_ARCH_5TE__ || defined __ARM_ARCH_5TEJ__ \ - || __ARM_ARCH__ >= 6 + || __ARM_ARCH >= 6 #if defined L_call_via_rX diff --git a/libgcc/config/arm/libunwind.S b/libgcc/config/arm/libunwind.S index 3302447..50c58dc 100644 --- a/libgcc/config/arm/libunwind.S +++ b/libgcc/config/arm/libunwind.S @@ -46,7 +46,7 @@ EQUIV SYM (\name), SYM (__\name) .endm -#if (__ARM_ARCH__ == 4) +#if (__ARM_ARCH == 4) /* Some coprocessors require armv5t. We know this code will never be run on other cpus. Tell gas to allow armv5t, but only mark the objects as armv4. */
Hi Christophe, On 17/06/18 21:23, Christophe Lyon wrote: > On Fri, 15 Jun 2018 at 17:22, Richard Earnshaw (lists) > <Richard.Earnshaw@arm.com> wrote: > > > > On 15/06/18 15:30, Christophe Lyon wrote: > > > Hello, > > > > > > As suggested in [1], the attached patch removes all definitions and > > > uses of __ARM_ARCH__ and uses __ARM_ARCH instead. The later is indeed > > > defined by the preprocessor to the appropriate value. > > > > > > I ran make check on arm-none-eabi (with A-profile multilib), > > > arm-none-linux-gnueabi, arm-none-linux-gnueabihf (with cortex-a9, a15, > > > a5, a57 and armtdmi as --with-cpu), armeb-none-linux-gnueabihf and > > > armv8l-linux-gnueabihf, and noticed no regression. > > > > > > OK for trunk? > > > > > > Thanks, > > > > > > Christophe > > > > > > [1] https://gcc.gnu.org/ml/gcc-patches/2018-06/msg00445.html > > > > > > > > > ARM_ARCH.chlog.txt > > > > > > > > > libatomic/ChangeLog: > > > > > > 2018-06-15 Christophe Lyon <christophe.lyon@linaro.org> > > > > > > * config/arm/arm-config.h (__ARM_ARCH__): Remove definitions, use > > > __ARM_ARCH instead. > > > > > > libgcc/ChangeLog: > > > > > > 2018-06-15 Christophe Lyon <christophe.lyon@linaro.org> > > > > > > * config/arm/lib1funcs.S (__ARM_ARCH__): Remove definitions, use > > > __ARM_ARCH instead. > > > * config/arm/ieee754-df.S: Use __ARM_ARCH instead of __ARM_ARCH__. > > > * config/arm/ieee754-sf.S: Likewise. > > > * config/arm/libunwind.S: Likewise. > > > > > > > > > ARM_ARCH.patch.txt > > > > > > > Thanks, this is a useful start. We can, however, go further. ACLE > > defines a number of 'feature' pre-defines and we can use those to void > > direct tests of the architecture version directly. For example, > > __ARM_FEATURE_LDREX could directly replace having to calculate > > HAVE_STREX and HAVE_STREXBHD. > > > Hi, > > Here is an updated patch using __ARM_FEATURE_LDREX. > I didn't find other opportunities to use ACLE pre-defines, did I miss any? > Thanks for doing this. I think we can catch a few more... diff --git a/libgcc/config/arm/ieee754-df.S b/libgcc/config/arm/ieee754-df.S index 570e5f6..7c5260e 100644 --- a/libgcc/config/arm/ieee754-df.S +++ b/libgcc/config/arm/ieee754-df.S @@ -245,7 +245,7 @@ LSYM(Lad_a): @ No rounding necessary since ip will always be 0 at this point. LSYM(Lad_l): -#if __ARM_ARCH__ < 5 +#if __ARM_ARCH < 5 This path exists to handle the case when the CLZ instruction is not available (the #else path uses CLZ). So we can change this to #ifndef __ARM_FEATURE_CLZ teq xh, #0 movne r3, #20 @@ -656,7 +656,7 @@ ARM_FUNC_ALIAS aeabi_dmul muldf3 orr yh, yh, #0x00100000 beq LSYM(Lml_1) -#if __ARM_ARCH__ < 4 +#if __ARM_ARCH < 4 We can delete this whole path as we no longer support anything older than 4 diff --git a/libgcc/config/arm/ieee754-sf.S b/libgcc/config/arm/ieee754-sf.S index dac3e2e..00a8d9c 100644 --- a/libgcc/config/arm/ieee754-sf.S +++ b/libgcc/config/arm/ieee754-sf.S @@ -175,7 +175,7 @@ LSYM(Lad_a): @ No rounding necessary since r1 will always be 0 at this point. LSYM(Lad_l): -#if __ARM_ARCH__ < 5 +#if __ARM_ARCH < 5 movs ip, r0, lsr #12 moveq r0, r0, lsl #12 @@ -370,7 +370,7 @@ ARM_FUNC_ALIAS aeabi_l2f floatdisf subeq r3, r3, #(32 << 23) 2: sub r3, r3, #(1 << 23) -#if __ARM_ARCH__ < 5 +#if __ARM_ARCH < 5 mov r2, #23 cmp ip, #(1 << 16) Similar comment on checking __ARM_FEATURE_CLZ in the above two checks. @@ -460,7 +460,7 @@ LSYM(Lml_x): orr r0, r3, r0, lsr #5 orr r1, r3, r1, lsr #5 -#if __ARM_ARCH__ < 4 +#if __ARM_ARCH < 4 @ Put sign bit in r3, which will be restored into r0 later. and r3, ip, #0x80000000 Likewise on deleting the < 4 path. diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S index 04c1b77..264d54a 100644 --- a/libgcc/config/arm/lib1funcs.S +++ b/libgcc/config/arm/lib1funcs.S @@ -74,49 +74,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see <snip> -#if __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__) +#if __ARM_ARCH >= 5 && ! defined (__OPTIMIZE_SIZE__) Likewise I believe this check should be for __ARM_FEATURE_CLZ, with the rest of the #elses updated accordingly. <snip> @@ -1701,8 +1658,8 @@ LSYM(Lover12): #if (__ARM_ARCH_ISA_THUMB == 2 \ || (__ARM_ARCH_ISA_ARM \ - && (__ARM_ARCH__ > 5 \ - || (__ARM_ARCH__ == 5 && __ARM_ARCH_ISA_THUMB)))) + && (__ARM_ARCH > 5 \ + || (__ARM_ARCH == 5 && __ARM_ARCH_ISA_THUMB)))) #define HAVE_ARM_CLZ 1 #endif This HAVE_ARM_CLZ should now be redundant as we can update its uses to __ARM_FEATURE_CLZ Thanks, Kyrill
On Tue, 19 Jun 2018 at 10:50, Kyrill Tkachov <kyrylo.tkachov@foss.arm.com> wrote: > > Hi Christophe, > > On 17/06/18 21:23, Christophe Lyon wrote: > > On Fri, 15 Jun 2018 at 17:22, Richard Earnshaw (lists) > > <Richard.Earnshaw@arm.com> wrote: > > > > > > On 15/06/18 15:30, Christophe Lyon wrote: > > > > Hello, > > > > > > > > As suggested in [1], the attached patch removes all definitions and > > > > uses of __ARM_ARCH__ and uses __ARM_ARCH instead. The later is indeed > > > > defined by the preprocessor to the appropriate value. > > > > > > > > I ran make check on arm-none-eabi (with A-profile multilib), > > > > arm-none-linux-gnueabi, arm-none-linux-gnueabihf (with cortex-a9, a15, > > > > a5, a57 and armtdmi as --with-cpu), armeb-none-linux-gnueabihf and > > > > armv8l-linux-gnueabihf, and noticed no regression. > > > > > > > > OK for trunk? > > > > > > > > Thanks, > > > > > > > > Christophe > > > > > > > > [1] https://gcc.gnu.org/ml/gcc-patches/2018-06/msg00445.html > > > > > > > > > > > > ARM_ARCH.chlog.txt > > > > > > > > > > > > libatomic/ChangeLog: > > > > > > > > 2018-06-15 Christophe Lyon <christophe.lyon@linaro.org> > > > > > > > > * config/arm/arm-config.h (__ARM_ARCH__): Remove definitions, use > > > > __ARM_ARCH instead. > > > > > > > > libgcc/ChangeLog: > > > > > > > > 2018-06-15 Christophe Lyon <christophe.lyon@linaro.org> > > > > > > > > * config/arm/lib1funcs.S (__ARM_ARCH__): Remove definitions, use > > > > __ARM_ARCH instead. > > > > * config/arm/ieee754-df.S: Use __ARM_ARCH instead of __ARM_ARCH__. > > > > * config/arm/ieee754-sf.S: Likewise. > > > > * config/arm/libunwind.S: Likewise. > > > > > > > > > > > > ARM_ARCH.patch.txt > > > > > > > > > > Thanks, this is a useful start. We can, however, go further. ACLE > > > defines a number of 'feature' pre-defines and we can use those to void > > > direct tests of the architecture version directly. For example, > > > __ARM_FEATURE_LDREX could directly replace having to calculate > > > HAVE_STREX and HAVE_STREXBHD. > > > > > Hi, > > > > Here is an updated patch using __ARM_FEATURE_LDREX. > > I didn't find other opportunities to use ACLE pre-defines, did I miss any? > > > > Thanks for doing this. I think we can catch a few more... > OK, I didn't grep accurately enough it seems. Here is a new version hopefully addressing your comments. However, I'm not sure whether replacing uses of __ARM_ARCH__ and removing support for arches < 4 should be in the same patch: this goes beyond my original intent, and I've noticed probable dead code in include/longlong.h (support for umul_ppmm on arm v2 and v3) Similarly there is code to define __ARM_ARCH in libffi/src/arm/sysv.S. So it seems further cleanup would be needed. Christophe > diff --git a/libgcc/config/arm/ieee754-df.S b/libgcc/config/arm/ieee754-df.S > index 570e5f6..7c5260e 100644 > --- a/libgcc/config/arm/ieee754-df.S > +++ b/libgcc/config/arm/ieee754-df.S > @@ -245,7 +245,7 @@ LSYM(Lad_a): > @ No rounding necessary since ip will always be 0 at this point. > LSYM(Lad_l): > > -#if __ARM_ARCH__ < 5 > +#if __ARM_ARCH < 5 > > This path exists to handle the case when the CLZ instruction is not available (the #else path uses CLZ). > So we can change this to #ifndef __ARM_FEATURE_CLZ > > > teq xh, #0 > movne r3, #20 > @@ -656,7 +656,7 @@ ARM_FUNC_ALIAS aeabi_dmul muldf3 > orr yh, yh, #0x00100000 > beq LSYM(Lml_1) > > -#if __ARM_ARCH__ < 4 > +#if __ARM_ARCH < 4 > > We can delete this whole path as we no longer support anything older than 4 > > diff --git a/libgcc/config/arm/ieee754-sf.S b/libgcc/config/arm/ieee754-sf.S > index dac3e2e..00a8d9c 100644 > --- a/libgcc/config/arm/ieee754-sf.S > +++ b/libgcc/config/arm/ieee754-sf.S > @@ -175,7 +175,7 @@ LSYM(Lad_a): > @ No rounding necessary since r1 will always be 0 at this point. > LSYM(Lad_l): > > -#if __ARM_ARCH__ < 5 > +#if __ARM_ARCH < 5 > > movs ip, r0, lsr #12 > moveq r0, r0, lsl #12 > @@ -370,7 +370,7 @@ ARM_FUNC_ALIAS aeabi_l2f floatdisf > subeq r3, r3, #(32 << 23) > 2: sub r3, r3, #(1 << 23) > > -#if __ARM_ARCH__ < 5 > +#if __ARM_ARCH < 5 > > mov r2, #23 > cmp ip, #(1 << 16) > > Similar comment on checking __ARM_FEATURE_CLZ in the above two checks. > > > @@ -460,7 +460,7 @@ LSYM(Lml_x): > orr r0, r3, r0, lsr #5 > orr r1, r3, r1, lsr #5 > > -#if __ARM_ARCH__ < 4 > +#if __ARM_ARCH < 4 > > @ Put sign bit in r3, which will be restored into r0 later. > and r3, ip, #0x80000000 > > > Likewise on deleting the < 4 path. > > diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S > index 04c1b77..264d54a 100644 > --- a/libgcc/config/arm/lib1funcs.S > +++ b/libgcc/config/arm/lib1funcs.S > @@ -74,49 +74,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see > > <snip> > > -#if __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__) > +#if __ARM_ARCH >= 5 && ! defined (__OPTIMIZE_SIZE__) > > > Likewise I believe this check should be for __ARM_FEATURE_CLZ, with the rest of the #elses > updated accordingly. > > <snip> > > @@ -1701,8 +1658,8 @@ LSYM(Lover12): > > #if (__ARM_ARCH_ISA_THUMB == 2 \ > || (__ARM_ARCH_ISA_ARM \ > - && (__ARM_ARCH__ > 5 \ > - || (__ARM_ARCH__ == 5 && __ARM_ARCH_ISA_THUMB)))) > + && (__ARM_ARCH > 5 \ > + || (__ARM_ARCH == 5 && __ARM_ARCH_ISA_THUMB)))) > #define HAVE_ARM_CLZ 1 > #endif > > This HAVE_ARM_CLZ should now be redundant as we can update its uses to __ARM_FEATURE_CLZ > > Thanks, > Kyrill > libatomic/ChangeLog: 2018-06-21 Christophe Lyon <christophe.lyon@linaro.org> * config/arm/arm-config.h (__ARM_ARCH__): Remove definitions, use __ARM_ARCH instead. Use __ARM_FEATURE_LDREX to define HAVE_STREX and HAVE_STREXBHD libgcc/ChangeLog: 2018-06-21 Christophe Lyon <christophe.lyon@linaro.org> * config/arm/lib1funcs.S (__ARM_ARCH__): Remove definitions, use __ARM_ARCH and __ARM_FEATURE_CLZ instead. (HAVE_ARM_CLZ): Remove and use __ARM_FEATURE_CLZ instead. * config/arm/ieee754-df.S: Use __ARM_FEATURE_CLZ instead of __ARM_ARCH__. Remove code for __ARM_ARCH__ < 4, no longer supported. * config/arm/ieee754-sf.S: Likewise. * config/arm/libunwind.S: Use __ARM_ARCH instead of __ARM_ARCH__. commit cdcf481009e0a8c9482fdab255fc9066b7dfbf8b Author: Christophe Lyon <christophe.lyon@linaro.org> Date: Tue Jun 12 22:27:33 2018 +0000 Replace __ARM_ARCH__ with __ARM_ARCH Also use __ARM_FEATURE_LDREX and __ARM_FEATURE_CLZ Change-Id: If36b56585fb95f5b138aee89f6cd28b82dae7873 diff --git a/libatomic/config/arm/arm-config.h b/libatomic/config/arm/arm-config.h index c0504be..b4783ad 100644 --- a/libatomic/config/arm/arm-config.h +++ b/libatomic/config/arm/arm-config.h @@ -23,57 +23,15 @@ <http://www.gnu.org/licenses/>. */ -#if defined(__ARM_ARCH_2__) -# define __ARM_ARCH__ 2 -#endif - -#if defined(__ARM_ARCH_3__) -# define __ARM_ARCH__ 3 -#endif - -#if defined(__ARM_ARCH_3M__) || defined(__ARM_ARCH_4__) \ - || defined(__ARM_ARCH_4T__) -/* We use __ARM_ARCH__ set to 4 here, but in reality it's any processor with - long multiply instructions. That includes v3M. */ -# define __ARM_ARCH__ 4 -#endif - -#if defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__) \ - || defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \ - || defined(__ARM_ARCH_5TEJ__) -# define __ARM_ARCH__ 5 -#endif - -#if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \ - || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) \ - || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) \ - || defined(__ARM_ARCH_6M__) -# define __ARM_ARCH__ 6 -#endif - -#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \ - || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \ - || defined(__ARM_ARCH_7EM__) -# define __ARM_ARCH__ 7 -#endif - -#if defined(__ARM_ARCH_8A__) -# define __ARM_ARCH__ 8 -#endif - -#ifndef __ARM_ARCH__ -#error Unable to determine architecture. -#endif - -#if __ARM_ARCH__ >= 7 || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6ZK__) +#if __ARM_FEATURE_LDREX & 4 # define HAVE_STREX 1 +#endif +#if (__ARM_FEATURE_LDREX & 0xF) == 0xF # define HAVE_STREXBHD 1 -#elif __ARM_ARCH__ == 6 -# define HAVE_STREX 1 #endif -#if __ARM_ARCH__ >= 7 +#if __ARM_ARCH >= 7 # define HAVE_DMB 1 -#elif __ARM_ARCH__ == 6 +#elif __ARM_ARCH == 6 # define HAVE_DMB_MCR 1 #endif diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S index 04c1b77..b9919aa 100644 --- a/libgcc/config/arm/lib1funcs.S +++ b/libgcc/config/arm/lib1funcs.S @@ -74,49 +74,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see /* Function end macros. Variants for interworking. */ -#if defined(__ARM_ARCH_2__) -# define __ARM_ARCH__ 2 -#endif - -#if defined(__ARM_ARCH_3__) -# define __ARM_ARCH__ 3 -#endif - -#if defined(__ARM_ARCH_3M__) || defined(__ARM_ARCH_4__) \ - || defined(__ARM_ARCH_4T__) -/* We use __ARM_ARCH__ set to 4 here, but in reality it's any processor with - long multiply instructions. That includes v3M. */ -# define __ARM_ARCH__ 4 -#endif - -#if defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__) \ - || defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \ - || defined(__ARM_ARCH_5TEJ__) -# define __ARM_ARCH__ 5 -#endif - -#if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \ - || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) \ - || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) \ - || defined(__ARM_ARCH_6M__) -# define __ARM_ARCH__ 6 -#endif - -#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \ - || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \ - || defined(__ARM_ARCH_7EM__) -# define __ARM_ARCH__ 7 -#endif - -#if defined(__ARM_ARCH_8A__) || defined(__ARM_ARCH_8M_BASE__) \ - || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8R__) -# define __ARM_ARCH__ 8 -#endif - -#ifndef __ARM_ARCH__ -#error Unable to determine architecture. -#endif - /* There are times when we might prefer Thumb1 code even if ARM code is permitted, for example, the code might be smaller, or there might be interworking problems with switching to ARM state if interworking is @@ -135,13 +92,13 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see /* How to return from a function call depends on the architecture variant. */ -#if (__ARM_ARCH__ > 4) || defined(__ARM_ARCH_4T__) +#if (__ARM_ARCH > 4) || defined(__ARM_ARCH_4T__) # define RET bx lr # define RETc(x) bx##x lr /* Special precautions for interworking on armv4t. */ -# if (__ARM_ARCH__ == 4) +# if (__ARM_ARCH == 4) /* Always use bx, not ldr pc. */ # if (defined(__thumb__) || defined(__THUMB_INTERWORK__)) @@ -544,7 +501,7 @@ pc .req r15 /* ------------------------------------------------------------------------ */ .macro ARM_DIV_BODY dividend, divisor, result, curbit -#if __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__) +#if defined (__ARM_FEATURE_CLZ) && ! defined (__OPTIMIZE_SIZE__) #if defined (__thumb2__) clz \curbit, \dividend @@ -584,8 +541,8 @@ pc .req r15 .endr #endif -#else /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ -#if __ARM_ARCH__ >= 5 +#else /* !defined (__ARM_FEATURE_CLZ) || defined (__OPTIMIZE_SIZE__) */ +#if defined (__ARM_FEATURE_CLZ) clz \curbit, \divisor clz \result, \dividend @@ -595,7 +552,7 @@ pc .req r15 mov \curbit, \curbit, lsl \result mov \result, #0 -#else /* __ARM_ARCH__ < 5 */ +#else /* !defined (__ARM_FEATURE_CLZ) */ @ Initially shift the divisor left 3 bits if possible, @ set curbit accordingly. This allows for curbit to be located @@ -626,7 +583,7 @@ pc .req r15 mov \result, #0 -#endif /* __ARM_ARCH__ < 5 */ +#endif /* !defined (__ARM_FEATURE_CLZ) */ @ Division loop 1: cmp \dividend, \divisor @@ -651,13 +608,13 @@ pc .req r15 movne \divisor, \divisor, lsr #4 bne 1b -#endif /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ +#endif /* !defined (__ARM_FEATURE_CLZ) || defined (__OPTIMIZE_SIZE__) */ .endm /* ------------------------------------------------------------------------ */ .macro ARM_DIV2_ORDER divisor, order -#if __ARM_ARCH__ >= 5 +#if defined (__ARM_FEATURE_CLZ) clz \order, \divisor rsb \order, \order, #31 @@ -687,7 +644,7 @@ pc .req r15 /* ------------------------------------------------------------------------ */ .macro ARM_MOD_BODY dividend, divisor, order, spare -#if __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__) +#if defined(__ARM_FEATURE_CLZ) && ! defined (__OPTIMIZE_SIZE__) clz \order, \divisor clz \spare, \dividend @@ -702,15 +659,15 @@ pc .req r15 subcs \dividend, \dividend, \divisor, lsl #shift .endr -#else /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ -#if __ARM_ARCH__ >= 5 +#else /* !defined (__ARM_FEATURE_CLZ) || defined (__OPTIMIZE_SIZE__) */ +#if defined (__ARM_FEATURE_CLZ) clz \order, \divisor clz \spare, \dividend sub \order, \order, \spare mov \divisor, \divisor, lsl \order -#else /* __ARM_ARCH__ < 5 */ +#else /* !defined (__ARM_FEATURE_CLZ) */ mov \order, #0 @@ -732,7 +689,7 @@ pc .req r15 addlo \order, \order, #1 blo 1b -#endif /* __ARM_ARCH__ < 5 */ +#endif /* !defined (__ARM_FEATURE_CLZ) */ @ Perform all needed substractions to keep only the reminder. @ Do comparisons in batch of 4 first. @@ -770,7 +727,7 @@ pc .req r15 subhs \dividend, \dividend, \divisor 5: -#endif /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ +#endif /* !defined (__ARM_FEATURE_CLZ) || defined (__OPTIMIZE_SIZE__) */ .endm /* ------------------------------------------------------------------------ */ @@ -1560,7 +1517,7 @@ LSYM(Lover12): @ EABI GNU/Linux call to cacheflush syscall. ARM_FUNC_START clear_cache do_push {r7} -#if __ARM_ARCH__ >= 7 || defined(__ARM_ARCH_6T2__) +#if __ARM_ARCH >= 7 || defined(__ARM_ARCH_6T2__) movw r7, #2 movt r7, #0xf #else @@ -1699,13 +1656,6 @@ LSYM(Lover12): #endif /* __symbian__ */ -#if (__ARM_ARCH_ISA_THUMB == 2 \ - || (__ARM_ARCH_ISA_ARM \ - && (__ARM_ARCH__ > 5 \ - || (__ARM_ARCH__ == 5 && __ARM_ARCH_ISA_THUMB)))) -#define HAVE_ARM_CLZ 1 -#endif - #ifdef L_clzsi2 #ifdef NOT_ISA_TARGET_32BIT FUNC_START clzsi2 @@ -1736,7 +1686,7 @@ FUNC_START clzsi2 FUNC_END clzsi2 #else ARM_FUNC_START clzsi2 -# if defined(HAVE_ARM_CLZ) +# if defined (__ARM_FEATURE_CLZ) clz r0, r0 RET # else @@ -1760,13 +1710,13 @@ ARM_FUNC_START clzsi2 .align 2 1: .byte 4, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 -# endif /* !HAVE_ARM_CLZ */ +# endif /* !defined (__ARM_FEATURE_CLZ) */ FUNC_END clzsi2 #endif #endif /* L_clzsi2 */ #ifdef L_clzdi2 -#if !defined(HAVE_ARM_CLZ) +#if !defined (__ARM_FEATURE_CLZ) # ifdef NOT_ISA_TARGET_32BIT FUNC_START clzdi2 @@ -1800,7 +1750,7 @@ ARM_FUNC_START clzdi2 # endif FUNC_END clzdi2 -#else /* HAVE_ARM_CLZ */ +#else /* defined (__ARM_FEATURE_CLZ) */ ARM_FUNC_START clzdi2 cmp xxh, #0 @@ -1848,7 +1798,7 @@ FUNC_START ctzsi2 ARM_FUNC_START ctzsi2 rsb r1, r0, #0 and r0, r0, r1 -# if defined(HAVE_ARM_CLZ) +# if defined (__ARM_FEATURE_CLZ) clz r0, r0 rsb r0, r0, #31 RET @@ -1873,7 +1823,7 @@ ARM_FUNC_START ctzsi2 .align 2 1: .byte 27, 28, 29, 29, 30, 30, 30, 30, 31, 31, 31, 31, 31, 31, 31, 31 -# endif /* !HAVE_ARM_CLZ */ +# endif /* !defined (__ARM_FEATURE_CLZ) */ FUNC_END ctzsi2 #endif #endif /* L_clzsi2 */ @@ -1887,7 +1837,7 @@ ARM_FUNC_START ctzsi2 not support Thumb instructions. (This can be a multilib option). */ #if defined __ARM_ARCH_4T__ || defined __ARM_ARCH_5T__\ || defined __ARM_ARCH_5TE__ || defined __ARM_ARCH_5TEJ__ \ - || __ARM_ARCH__ >= 6 + || __ARM_ARCH >= 6 #if defined L_call_via_rX diff --git a/libgcc/config/arm/ieee754-df.S b/libgcc/config/arm/ieee754-df.S index 570e5f6..8741aa9 100644 --- a/libgcc/config/arm/ieee754-df.S +++ b/libgcc/config/arm/ieee754-df.S @@ -245,7 +245,7 @@ LSYM(Lad_a): @ No rounding necessary since ip will always be 0 at this point. LSYM(Lad_l): -#if __ARM_ARCH__ < 5 +#if !defined (__ARM_FEATURE_CLZ) teq xh, #0 movne r3, #20 @@ -656,78 +656,8 @@ ARM_FUNC_ALIAS aeabi_dmul muldf3 orr yh, yh, #0x00100000 beq LSYM(Lml_1) -#if __ARM_ARCH__ < 4 - - @ Put sign bit in r6, which will be restored in yl later. - and r6, r6, #0x80000000 - - @ Well, no way to make it shorter without the umull instruction. - stmfd sp!, {r6, r7, r8, r9, sl, fp} @ sp -= 24 - .cfi_remember_state @ Save the current CFI state. - .cfi_adjust_cfa_offset 24 @ CFA is now sp + previousOffset + 24. - .cfi_rel_offset r6, 0 @ Registers are saved from sp to sp + 20. - .cfi_rel_offset r7, 4 - .cfi_rel_offset r8, 8 - .cfi_rel_offset r9, 12 - .cfi_rel_offset sl, 16 - .cfi_rel_offset fp, 20 - - mov r7, xl, lsr #16 - mov r8, yl, lsr #16 - mov r9, xh, lsr #16 - mov sl, yh, lsr #16 - bic xl, xl, r7, lsl #16 - bic yl, yl, r8, lsl #16 - bic xh, xh, r9, lsl #16 - bic yh, yh, sl, lsl #16 - mul ip, xl, yl - mul fp, xl, r8 - mov lr, #0 - adds ip, ip, fp, lsl #16 - adc lr, lr, fp, lsr #16 - mul fp, r7, yl - adds ip, ip, fp, lsl #16 - adc lr, lr, fp, lsr #16 - mul fp, xl, sl - mov r5, #0 - adds lr, lr, fp, lsl #16 - adc r5, r5, fp, lsr #16 - mul fp, r7, yh - adds lr, lr, fp, lsl #16 - adc r5, r5, fp, lsr #16 - mul fp, xh, r8 - adds lr, lr, fp, lsl #16 - adc r5, r5, fp, lsr #16 - mul fp, r9, yl - adds lr, lr, fp, lsl #16 - adc r5, r5, fp, lsr #16 - mul fp, xh, sl - mul r6, r9, sl - adds r5, r5, fp, lsl #16 - adc r6, r6, fp, lsr #16 - mul fp, r9, yh - adds r5, r5, fp, lsl #16 - adc r6, r6, fp, lsr #16 - mul fp, xl, yh - adds lr, lr, fp - mul fp, r7, sl - adcs r5, r5, fp - mul fp, xh, yl - adc r6, r6, #0 - adds lr, lr, fp - mul fp, r9, r8 - adcs r5, r5, fp - mul fp, r7, r8 - adc r6, r6, #0 - adds lr, lr, fp - mul fp, xh, yh - adcs r5, r5, fp - adc r6, r6, #0 - ldmfd sp!, {yl, r7, r8, r9, sl, fp} @ sp += 24 - .cfi_restore_state @ Restore the previous CFI state. -#else - @ Here is the actual multiplication. + @ This code works on architecture versions > 4 umull ip, lr, xl, yl mov r5, #0 umlal lr, r5, xh, yl @@ -736,8 +666,6 @@ ARM_FUNC_ALIAS aeabi_dmul muldf3 mov r6, #0 umlal r5, r6, xh, yh -#endif - @ The LSBs in ip are only significant for the final rounding. @ Fold them into lr. teq ip, #0 diff --git a/libgcc/config/arm/ieee754-sf.S b/libgcc/config/arm/ieee754-sf.S index dac3e2e..d80d5e9 100644 --- a/libgcc/config/arm/ieee754-sf.S +++ b/libgcc/config/arm/ieee754-sf.S @@ -175,7 +175,7 @@ LSYM(Lad_a): @ No rounding necessary since r1 will always be 0 at this point. LSYM(Lad_l): -#if __ARM_ARCH__ < 5 +#if !defined (__ARM_FEATURE_CLZ) movs ip, r0, lsr #12 moveq r0, r0, lsl #12 @@ -370,7 +370,7 @@ ARM_FUNC_ALIAS aeabi_l2f floatdisf subeq r3, r3, #(32 << 23) 2: sub r3, r3, #(1 << 23) -#if __ARM_ARCH__ < 5 +#if !defined (__ARM_FEATURE_CLZ) mov r2, #23 cmp ip, #(1 << 16) @@ -460,42 +460,13 @@ LSYM(Lml_x): orr r0, r3, r0, lsr #5 orr r1, r3, r1, lsr #5 -#if __ARM_ARCH__ < 4 - - @ Put sign bit in r3, which will be restored into r0 later. - and r3, ip, #0x80000000 - - @ Well, no way to make it shorter without the umull instruction. - do_push {r3, r4, r5} @ sp -= 12 - .cfi_remember_state @ Save the current CFI state - .cfi_adjust_cfa_offset 12 @ CFA is now sp + previousOffset + 12 - .cfi_rel_offset r3, 0 @ Registers are saved from sp to sp + 8 - .cfi_rel_offset r4, 4 - .cfi_rel_offset r5, 8 - - mov r4, r0, lsr #16 - mov r5, r1, lsr #16 - bic r0, r0, r4, lsl #16 - bic r1, r1, r5, lsl #16 - mul ip, r4, r5 - mul r3, r0, r1 - mul r0, r5, r0 - mla r0, r4, r1, r0 - adds r3, r3, r0, lsl #16 - adc r1, ip, r0, lsr #16 - do_pop {r0, r4, r5} @ sp += 12 - .cfi_restore_state @ Restore the previous CFI state - -#else - @ The actual multiplication. + @ This code works on architecture versions > 4 umull r3, r1, r0, r1 @ Put final sign in r0. and r0, ip, #0x80000000 -#endif - @ Adjust result upon the MSB position. cmp r1, #(1 << 23) do_it cc, tt diff --git a/libgcc/config/arm/libunwind.S b/libgcc/config/arm/libunwind.S index 3302447..50c58dc 100644 --- a/libgcc/config/arm/libunwind.S +++ b/libgcc/config/arm/libunwind.S @@ -46,7 +46,7 @@ EQUIV SYM (\name), SYM (__\name) .endm -#if (__ARM_ARCH__ == 4) +#if (__ARM_ARCH == 4) /* Some coprocessors require armv5t. We know this code will never be run on other cpus. Tell gas to allow armv5t, but only mark the objects as armv4. */
On 21/06/18 07:59, Christophe Lyon wrote: > On Tue, 19 Jun 2018 at 10:50, Kyrill Tkachov > <kyrylo.tkachov@foss.arm.com> wrote: >> Hi Christophe, >> >> On 17/06/18 21:23, Christophe Lyon wrote: >>> On Fri, 15 Jun 2018 at 17:22, Richard Earnshaw (lists) >>> <Richard.Earnshaw@arm.com> wrote: >>>> On 15/06/18 15:30, Christophe Lyon wrote: >>>>> Hello, >>>>> >>>>> As suggested in [1], the attached patch removes all definitions and >>>>> uses of __ARM_ARCH__ and uses __ARM_ARCH instead. The later is indeed >>>>> defined by the preprocessor to the appropriate value. >>>>> >>>>> I ran make check on arm-none-eabi (with A-profile multilib), >>>>> arm-none-linux-gnueabi, arm-none-linux-gnueabihf (with cortex-a9, a15, >>>>> a5, a57 and armtdmi as --with-cpu), armeb-none-linux-gnueabihf and >>>>> armv8l-linux-gnueabihf, and noticed no regression. >>>>> >>>>> OK for trunk? >>>>> >>>>> Thanks, >>>>> >>>>> Christophe >>>>> >>>>> [1] https://gcc.gnu.org/ml/gcc-patches/2018-06/msg00445.html >>>>> >>>>> >>>>> ARM_ARCH.chlog.txt >>>>> >>>>> >>>>> libatomic/ChangeLog: >>>>> >>>>> 2018-06-15 Christophe Lyon <christophe.lyon@linaro.org> >>>>> >>>>> * config/arm/arm-config.h (__ARM_ARCH__): Remove definitions, use >>>>> __ARM_ARCH instead. >>>>> >>>>> libgcc/ChangeLog: >>>>> >>>>> 2018-06-15 Christophe Lyon <christophe.lyon@linaro.org> >>>>> >>>>> * config/arm/lib1funcs.S (__ARM_ARCH__): Remove definitions, use >>>>> __ARM_ARCH instead. >>>>> * config/arm/ieee754-df.S: Use __ARM_ARCH instead of __ARM_ARCH__. >>>>> * config/arm/ieee754-sf.S: Likewise. >>>>> * config/arm/libunwind.S: Likewise. >>>>> >>>>> >>>>> ARM_ARCH.patch.txt >>>>> >>>> Thanks, this is a useful start. We can, however, go further. ACLE >>>> defines a number of 'feature' pre-defines and we can use those to void >>>> direct tests of the architecture version directly. For example, >>>> __ARM_FEATURE_LDREX could directly replace having to calculate >>>> HAVE_STREX and HAVE_STREXBHD. >>>> >>> Hi, >>> >>> Here is an updated patch using __ARM_FEATURE_LDREX. >>> I didn't find other opportunities to use ACLE pre-defines, did I miss any? >>> >> Thanks for doing this. I think we can catch a few more... >> > OK, I didn't grep accurately enough it seems. > > Here is a new version hopefully addressing your comments. yes, that looks good now. > However, I'm not sure whether replacing uses of __ARM_ARCH__ and > removing support for arches < 4 should be in the same patch: this goes > beyond my original intent, and I've noticed probable dead code in > include/longlong.h (support for umul_ppmm on arm v2 and v3) I see your point. It could indeed be cleaner if the code removal hunk was put in a separate patch. A bugzilla entry about the dead code to be removed would be appreciated, I can take care of that then. > Similarly there is code to define __ARM_ARCH in libffi/src/arm/sysv.S. I believe libffi is its own separate project that we import in GCC, so it may want to support compiling with older GCC versions. I'd need to double-check that. > So it seems further cleanup would be needed. Indeed. This patch is ok with the __ARM_ARCH < 4 path removals separated into their own patch. Thanks, Kyrill > > Christophe > > >> diff --git a/libgcc/config/arm/ieee754-df.S b/libgcc/config/arm/ieee754-df.S >> index 570e5f6..7c5260e 100644 >> --- a/libgcc/config/arm/ieee754-df.S >> +++ b/libgcc/config/arm/ieee754-df.S >> @@ -245,7 +245,7 @@ LSYM(Lad_a): >> @ No rounding necessary since ip will always be 0 at this point. >> LSYM(Lad_l): >> >> -#if __ARM_ARCH__ < 5 >> +#if __ARM_ARCH < 5 >> >> This path exists to handle the case when the CLZ instruction is not available (the #else path uses CLZ). >> So we can change this to #ifndef __ARM_FEATURE_CLZ >> >> >> teq xh, #0 >> movne r3, #20 >> @@ -656,7 +656,7 @@ ARM_FUNC_ALIAS aeabi_dmul muldf3 >> orr yh, yh, #0x00100000 >> beq LSYM(Lml_1) >> >> -#if __ARM_ARCH__ < 4 >> +#if __ARM_ARCH < 4 >> >> We can delete this whole path as we no longer support anything older than 4 >> >> diff --git a/libgcc/config/arm/ieee754-sf.S b/libgcc/config/arm/ieee754-sf.S >> index dac3e2e..00a8d9c 100644 >> --- a/libgcc/config/arm/ieee754-sf.S >> +++ b/libgcc/config/arm/ieee754-sf.S >> @@ -175,7 +175,7 @@ LSYM(Lad_a): >> @ No rounding necessary since r1 will always be 0 at this point. >> LSYM(Lad_l): >> >> -#if __ARM_ARCH__ < 5 >> +#if __ARM_ARCH < 5 >> >> movs ip, r0, lsr #12 >> moveq r0, r0, lsl #12 >> @@ -370,7 +370,7 @@ ARM_FUNC_ALIAS aeabi_l2f floatdisf >> subeq r3, r3, #(32 << 23) >> 2: sub r3, r3, #(1 << 23) >> >> -#if __ARM_ARCH__ < 5 >> +#if __ARM_ARCH < 5 >> >> mov r2, #23 >> cmp ip, #(1 << 16) >> >> Similar comment on checking __ARM_FEATURE_CLZ in the above two checks. >> >> >> @@ -460,7 +460,7 @@ LSYM(Lml_x): >> orr r0, r3, r0, lsr #5 >> orr r1, r3, r1, lsr #5 >> >> -#if __ARM_ARCH__ < 4 >> +#if __ARM_ARCH < 4 >> >> @ Put sign bit in r3, which will be restored into r0 later. >> and r3, ip, #0x80000000 >> >> >> Likewise on deleting the < 4 path. >> >> diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S >> index 04c1b77..264d54a 100644 >> --- a/libgcc/config/arm/lib1funcs.S >> +++ b/libgcc/config/arm/lib1funcs.S >> @@ -74,49 +74,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see >> >> <snip> >> >> -#if __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__) >> +#if __ARM_ARCH >= 5 && ! defined (__OPTIMIZE_SIZE__) >> >> >> Likewise I believe this check should be for __ARM_FEATURE_CLZ, with the rest of the #elses >> updated accordingly. >> >> <snip> >> >> @@ -1701,8 +1658,8 @@ LSYM(Lover12): >> >> #if (__ARM_ARCH_ISA_THUMB == 2 \ >> || (__ARM_ARCH_ISA_ARM \ >> - && (__ARM_ARCH__ > 5 \ >> - || (__ARM_ARCH__ == 5 && __ARM_ARCH_ISA_THUMB)))) >> + && (__ARM_ARCH > 5 \ >> + || (__ARM_ARCH == 5 && __ARM_ARCH_ISA_THUMB)))) >> #define HAVE_ARM_CLZ 1 >> #endif >> >> This HAVE_ARM_CLZ should now be redundant as we can update its uses to __ARM_FEATURE_CLZ >> >> Thanks, >> Kyrill >>
On Thu, 21 Jun 2018 at 10:00, Kyrill Tkachov <kyrylo.tkachov@foss.arm.com> wrote: > > > On 21/06/18 07:59, Christophe Lyon wrote: > > On Tue, 19 Jun 2018 at 10:50, Kyrill Tkachov > > <kyrylo.tkachov@foss.arm.com> wrote: > >> Hi Christophe, > >> > >> On 17/06/18 21:23, Christophe Lyon wrote: > >>> On Fri, 15 Jun 2018 at 17:22, Richard Earnshaw (lists) > >>> <Richard.Earnshaw@arm.com> wrote: > >>>> On 15/06/18 15:30, Christophe Lyon wrote: > >>>>> Hello, > >>>>> > >>>>> As suggested in [1], the attached patch removes all definitions and > >>>>> uses of __ARM_ARCH__ and uses __ARM_ARCH instead. The later is indeed > >>>>> defined by the preprocessor to the appropriate value. > >>>>> > >>>>> I ran make check on arm-none-eabi (with A-profile multilib), > >>>>> arm-none-linux-gnueabi, arm-none-linux-gnueabihf (with cortex-a9, a15, > >>>>> a5, a57 and armtdmi as --with-cpu), armeb-none-linux-gnueabihf and > >>>>> armv8l-linux-gnueabihf, and noticed no regression. > >>>>> > >>>>> OK for trunk? > >>>>> > >>>>> Thanks, > >>>>> > >>>>> Christophe > >>>>> > >>>>> [1] https://gcc.gnu.org/ml/gcc-patches/2018-06/msg00445.html > >>>>> > >>>>> > >>>>> ARM_ARCH.chlog.txt > >>>>> > >>>>> > >>>>> libatomic/ChangeLog: > >>>>> > >>>>> 2018-06-15 Christophe Lyon <christophe.lyon@linaro.org> > >>>>> > >>>>> * config/arm/arm-config.h (__ARM_ARCH__): Remove definitions, use > >>>>> __ARM_ARCH instead. > >>>>> > >>>>> libgcc/ChangeLog: > >>>>> > >>>>> 2018-06-15 Christophe Lyon <christophe.lyon@linaro.org> > >>>>> > >>>>> * config/arm/lib1funcs.S (__ARM_ARCH__): Remove definitions, use > >>>>> __ARM_ARCH instead. > >>>>> * config/arm/ieee754-df.S: Use __ARM_ARCH instead of __ARM_ARCH__. > >>>>> * config/arm/ieee754-sf.S: Likewise. > >>>>> * config/arm/libunwind.S: Likewise. > >>>>> > >>>>> > >>>>> ARM_ARCH.patch.txt > >>>>> > >>>> Thanks, this is a useful start. We can, however, go further. ACLE > >>>> defines a number of 'feature' pre-defines and we can use those to void > >>>> direct tests of the architecture version directly. For example, > >>>> __ARM_FEATURE_LDREX could directly replace having to calculate > >>>> HAVE_STREX and HAVE_STREXBHD. > >>>> > >>> Hi, > >>> > >>> Here is an updated patch using __ARM_FEATURE_LDREX. > >>> I didn't find other opportunities to use ACLE pre-defines, did I miss any? > >>> > >> Thanks for doing this. I think we can catch a few more... > >> > > OK, I didn't grep accurately enough it seems. > > > > Here is a new version hopefully addressing your comments. > > yes, that looks good now. > > > However, I'm not sure whether replacing uses of __ARM_ARCH__ and > > removing support for arches < 4 should be in the same patch: this goes > > beyond my original intent, and I've noticed probable dead code in > > include/longlong.h (support for umul_ppmm on arm v2 and v3) > > I see your point. It could indeed be cleaner if the code removal hunk was > put in a separate patch. A bugzilla entry about the dead code to be removed would > be appreciated, I can take care of that then. > OK, I've filed https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86264 > > Similarly there is code to define __ARM_ARCH in libffi/src/arm/sysv.S. > > I believe libffi is its own separate project that we import in GCC, so it may want > to support compiling with older GCC versions. I'd need to double-check that. > Indeed, that worried me too. > > So it seems further cleanup would be needed. > > Indeed. This patch is ok with the __ARM_ARCH < 4 path removals separated into > their own patch. > Thanks, committed as r261840 and r261841. > Thanks, > Kyrill > > > > > Christophe > > > > > >> diff --git a/libgcc/config/arm/ieee754-df.S b/libgcc/config/arm/ieee754-df.S > >> index 570e5f6..7c5260e 100644 > >> --- a/libgcc/config/arm/ieee754-df.S > >> +++ b/libgcc/config/arm/ieee754-df.S > >> @@ -245,7 +245,7 @@ LSYM(Lad_a): > >> @ No rounding necessary since ip will always be 0 at this point. > >> LSYM(Lad_l): > >> > >> -#if __ARM_ARCH__ < 5 > >> +#if __ARM_ARCH < 5 > >> > >> This path exists to handle the case when the CLZ instruction is not available (the #else path uses CLZ). > >> So we can change this to #ifndef __ARM_FEATURE_CLZ > >> > >> > >> teq xh, #0 > >> movne r3, #20 > >> @@ -656,7 +656,7 @@ ARM_FUNC_ALIAS aeabi_dmul muldf3 > >> orr yh, yh, #0x00100000 > >> beq LSYM(Lml_1) > >> > >> -#if __ARM_ARCH__ < 4 > >> +#if __ARM_ARCH < 4 > >> > >> We can delete this whole path as we no longer support anything older than 4 > >> > >> diff --git a/libgcc/config/arm/ieee754-sf.S b/libgcc/config/arm/ieee754-sf.S > >> index dac3e2e..00a8d9c 100644 > >> --- a/libgcc/config/arm/ieee754-sf.S > >> +++ b/libgcc/config/arm/ieee754-sf.S > >> @@ -175,7 +175,7 @@ LSYM(Lad_a): > >> @ No rounding necessary since r1 will always be 0 at this point. > >> LSYM(Lad_l): > >> > >> -#if __ARM_ARCH__ < 5 > >> +#if __ARM_ARCH < 5 > >> > >> movs ip, r0, lsr #12 > >> moveq r0, r0, lsl #12 > >> @@ -370,7 +370,7 @@ ARM_FUNC_ALIAS aeabi_l2f floatdisf > >> subeq r3, r3, #(32 << 23) > >> 2: sub r3, r3, #(1 << 23) > >> > >> -#if __ARM_ARCH__ < 5 > >> +#if __ARM_ARCH < 5 > >> > >> mov r2, #23 > >> cmp ip, #(1 << 16) > >> > >> Similar comment on checking __ARM_FEATURE_CLZ in the above two checks. > >> > >> > >> @@ -460,7 +460,7 @@ LSYM(Lml_x): > >> orr r0, r3, r0, lsr #5 > >> orr r1, r3, r1, lsr #5 > >> > >> -#if __ARM_ARCH__ < 4 > >> +#if __ARM_ARCH < 4 > >> > >> @ Put sign bit in r3, which will be restored into r0 later. > >> and r3, ip, #0x80000000 > >> > >> > >> Likewise on deleting the < 4 path. > >> > >> diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S > >> index 04c1b77..264d54a 100644 > >> --- a/libgcc/config/arm/lib1funcs.S > >> +++ b/libgcc/config/arm/lib1funcs.S > >> @@ -74,49 +74,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see > >> > >> <snip> > >> > >> -#if __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__) > >> +#if __ARM_ARCH >= 5 && ! defined (__OPTIMIZE_SIZE__) > >> > >> > >> Likewise I believe this check should be for __ARM_FEATURE_CLZ, with the rest of the #elses > >> updated accordingly. > >> > >> <snip> > >> > >> @@ -1701,8 +1658,8 @@ LSYM(Lover12): > >> > >> #if (__ARM_ARCH_ISA_THUMB == 2 \ > >> || (__ARM_ARCH_ISA_ARM \ > >> - && (__ARM_ARCH__ > 5 \ > >> - || (__ARM_ARCH__ == 5 && __ARM_ARCH_ISA_THUMB)))) > >> + && (__ARM_ARCH > 5 \ > >> + || (__ARM_ARCH == 5 && __ARM_ARCH_ISA_THUMB)))) > >> #define HAVE_ARM_CLZ 1 > >> #endif > >> > >> This HAVE_ARM_CLZ should now be redundant as we can update its uses to __ARM_FEATURE_CLZ > >> > >> Thanks, > >> Kyrill > >> >
diff --git a/libatomic/config/arm/arm-config.h b/libatomic/config/arm/arm-config.h index c0504be..ce8ff0e 100644 --- a/libatomic/config/arm/arm-config.h +++ b/libatomic/config/arm/arm-config.h @@ -23,57 +23,15 @@ <http://www.gnu.org/licenses/>. */ -#if defined(__ARM_ARCH_2__) -# define __ARM_ARCH__ 2 -#endif - -#if defined(__ARM_ARCH_3__) -# define __ARM_ARCH__ 3 -#endif - -#if defined(__ARM_ARCH_3M__) || defined(__ARM_ARCH_4__) \ - || defined(__ARM_ARCH_4T__) -/* We use __ARM_ARCH__ set to 4 here, but in reality it's any processor with - long multiply instructions. That includes v3M. */ -# define __ARM_ARCH__ 4 -#endif - -#if defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__) \ - || defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \ - || defined(__ARM_ARCH_5TEJ__) -# define __ARM_ARCH__ 5 -#endif - -#if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \ - || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) \ - || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) \ - || defined(__ARM_ARCH_6M__) -# define __ARM_ARCH__ 6 -#endif - -#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \ - || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \ - || defined(__ARM_ARCH_7EM__) -# define __ARM_ARCH__ 7 -#endif - -#if defined(__ARM_ARCH_8A__) -# define __ARM_ARCH__ 8 -#endif - -#ifndef __ARM_ARCH__ -#error Unable to determine architecture. -#endif - -#if __ARM_ARCH__ >= 7 || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6ZK__) +#if __ARM_ARCH >= 7 || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6ZK__) # define HAVE_STREX 1 # define HAVE_STREXBHD 1 -#elif __ARM_ARCH__ == 6 +#elif __ARM_ARCH == 6 # define HAVE_STREX 1 #endif -#if __ARM_ARCH__ >= 7 +#if __ARM_ARCH >= 7 # define HAVE_DMB 1 -#elif __ARM_ARCH__ == 6 +#elif __ARM_ARCH == 6 # define HAVE_DMB_MCR 1 #endif diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S index 04c1b77..264d54a 100644 --- a/libgcc/config/arm/lib1funcs.S +++ b/libgcc/config/arm/lib1funcs.S @@ -74,49 +74,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see /* Function end macros. Variants for interworking. */ -#if defined(__ARM_ARCH_2__) -# define __ARM_ARCH__ 2 -#endif - -#if defined(__ARM_ARCH_3__) -# define __ARM_ARCH__ 3 -#endif - -#if defined(__ARM_ARCH_3M__) || defined(__ARM_ARCH_4__) \ - || defined(__ARM_ARCH_4T__) -/* We use __ARM_ARCH__ set to 4 here, but in reality it's any processor with - long multiply instructions. That includes v3M. */ -# define __ARM_ARCH__ 4 -#endif - -#if defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__) \ - || defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \ - || defined(__ARM_ARCH_5TEJ__) -# define __ARM_ARCH__ 5 -#endif - -#if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \ - || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) \ - || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) \ - || defined(__ARM_ARCH_6M__) -# define __ARM_ARCH__ 6 -#endif - -#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \ - || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \ - || defined(__ARM_ARCH_7EM__) -# define __ARM_ARCH__ 7 -#endif - -#if defined(__ARM_ARCH_8A__) || defined(__ARM_ARCH_8M_BASE__) \ - || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8R__) -# define __ARM_ARCH__ 8 -#endif - -#ifndef __ARM_ARCH__ -#error Unable to determine architecture. -#endif - /* There are times when we might prefer Thumb1 code even if ARM code is permitted, for example, the code might be smaller, or there might be interworking problems with switching to ARM state if interworking is @@ -135,13 +92,13 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see /* How to return from a function call depends on the architecture variant. */ -#if (__ARM_ARCH__ > 4) || defined(__ARM_ARCH_4T__) +#if (__ARM_ARCH > 4) || defined(__ARM_ARCH_4T__) # define RET bx lr # define RETc(x) bx##x lr /* Special precautions for interworking on armv4t. */ -# if (__ARM_ARCH__ == 4) +# if (__ARM_ARCH == 4) /* Always use bx, not ldr pc. */ # if (defined(__thumb__) || defined(__THUMB_INTERWORK__)) @@ -544,7 +501,7 @@ pc .req r15 /* ------------------------------------------------------------------------ */ .macro ARM_DIV_BODY dividend, divisor, result, curbit -#if __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__) +#if __ARM_ARCH >= 5 && ! defined (__OPTIMIZE_SIZE__) #if defined (__thumb2__) clz \curbit, \dividend @@ -584,8 +541,8 @@ pc .req r15 .endr #endif -#else /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ -#if __ARM_ARCH__ >= 5 +#else /* __ARM_ARCH < 5 || defined (__OPTIMIZE_SIZE__) */ +#if __ARM_ARCH >= 5 clz \curbit, \divisor clz \result, \dividend @@ -595,7 +552,7 @@ pc .req r15 mov \curbit, \curbit, lsl \result mov \result, #0 -#else /* __ARM_ARCH__ < 5 */ +#else /* __ARM_ARCH < 5 */ @ Initially shift the divisor left 3 bits if possible, @ set curbit accordingly. This allows for curbit to be located @@ -626,7 +583,7 @@ pc .req r15 mov \result, #0 -#endif /* __ARM_ARCH__ < 5 */ +#endif /* __ARM_ARCH < 5 */ @ Division loop 1: cmp \dividend, \divisor @@ -651,13 +608,13 @@ pc .req r15 movne \divisor, \divisor, lsr #4 bne 1b -#endif /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ +#endif /* __ARM_ARCH < 5 || defined (__OPTIMIZE_SIZE__) */ .endm /* ------------------------------------------------------------------------ */ .macro ARM_DIV2_ORDER divisor, order -#if __ARM_ARCH__ >= 5 +#if __ARM_ARCH >= 5 clz \order, \divisor rsb \order, \order, #31 @@ -687,7 +644,7 @@ pc .req r15 /* ------------------------------------------------------------------------ */ .macro ARM_MOD_BODY dividend, divisor, order, spare -#if __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__) +#if __ARM_ARCH >= 5 && ! defined (__OPTIMIZE_SIZE__) clz \order, \divisor clz \spare, \dividend @@ -702,15 +659,15 @@ pc .req r15 subcs \dividend, \dividend, \divisor, lsl #shift .endr -#else /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ -#if __ARM_ARCH__ >= 5 +#else /* __ARM_ARCH < 5 || defined (__OPTIMIZE_SIZE__) */ +#if __ARM_ARCH >= 5 clz \order, \divisor clz \spare, \dividend sub \order, \order, \spare mov \divisor, \divisor, lsl \order -#else /* __ARM_ARCH__ < 5 */ +#else /* __ARM_ARCH < 5 */ mov \order, #0 @@ -732,7 +689,7 @@ pc .req r15 addlo \order, \order, #1 blo 1b -#endif /* __ARM_ARCH__ < 5 */ +#endif /* __ARM_ARCH < 5 */ @ Perform all needed substractions to keep only the reminder. @ Do comparisons in batch of 4 first. @@ -770,7 +727,7 @@ pc .req r15 subhs \dividend, \dividend, \divisor 5: -#endif /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ +#endif /* __ARM_ARCH < 5 || defined (__OPTIMIZE_SIZE__) */ .endm /* ------------------------------------------------------------------------ */ @@ -1560,7 +1517,7 @@ LSYM(Lover12): @ EABI GNU/Linux call to cacheflush syscall. ARM_FUNC_START clear_cache do_push {r7} -#if __ARM_ARCH__ >= 7 || defined(__ARM_ARCH_6T2__) +#if __ARM_ARCH >= 7 || defined(__ARM_ARCH_6T2__) movw r7, #2 movt r7, #0xf #else @@ -1701,8 +1658,8 @@ LSYM(Lover12): #if (__ARM_ARCH_ISA_THUMB == 2 \ || (__ARM_ARCH_ISA_ARM \ - && (__ARM_ARCH__ > 5 \ - || (__ARM_ARCH__ == 5 && __ARM_ARCH_ISA_THUMB)))) + && (__ARM_ARCH > 5 \ + || (__ARM_ARCH == 5 && __ARM_ARCH_ISA_THUMB)))) #define HAVE_ARM_CLZ 1 #endif @@ -1887,7 +1844,7 @@ ARM_FUNC_START ctzsi2 not support Thumb instructions. (This can be a multilib option). */ #if defined __ARM_ARCH_4T__ || defined __ARM_ARCH_5T__\ || defined __ARM_ARCH_5TE__ || defined __ARM_ARCH_5TEJ__ \ - || __ARM_ARCH__ >= 6 + || __ARM_ARCH >= 6 #if defined L_call_via_rX diff --git a/libgcc/config/arm/ieee754-df.S b/libgcc/config/arm/ieee754-df.S index 570e5f6..7c5260e 100644 --- a/libgcc/config/arm/ieee754-df.S +++ b/libgcc/config/arm/ieee754-df.S @@ -245,7 +245,7 @@ LSYM(Lad_a): @ No rounding necessary since ip will always be 0 at this point. LSYM(Lad_l): -#if __ARM_ARCH__ < 5 +#if __ARM_ARCH < 5 teq xh, #0 movne r3, #20 @@ -656,7 +656,7 @@ ARM_FUNC_ALIAS aeabi_dmul muldf3 orr yh, yh, #0x00100000 beq LSYM(Lml_1) -#if __ARM_ARCH__ < 4 +#if __ARM_ARCH < 4 @ Put sign bit in r6, which will be restored in yl later. and r6, r6, #0x80000000 diff --git a/libgcc/config/arm/ieee754-sf.S b/libgcc/config/arm/ieee754-sf.S index dac3e2e..00a8d9c 100644 --- a/libgcc/config/arm/ieee754-sf.S +++ b/libgcc/config/arm/ieee754-sf.S @@ -175,7 +175,7 @@ LSYM(Lad_a): @ No rounding necessary since r1 will always be 0 at this point. LSYM(Lad_l): -#if __ARM_ARCH__ < 5 +#if __ARM_ARCH < 5 movs ip, r0, lsr #12 moveq r0, r0, lsl #12 @@ -370,7 +370,7 @@ ARM_FUNC_ALIAS aeabi_l2f floatdisf subeq r3, r3, #(32 << 23) 2: sub r3, r3, #(1 << 23) -#if __ARM_ARCH__ < 5 +#if __ARM_ARCH < 5 mov r2, #23 cmp ip, #(1 << 16) @@ -460,7 +460,7 @@ LSYM(Lml_x): orr r0, r3, r0, lsr #5 orr r1, r3, r1, lsr #5 -#if __ARM_ARCH__ < 4 +#if __ARM_ARCH < 4 @ Put sign bit in r3, which will be restored into r0 later. and r3, ip, #0x80000000 diff --git a/libgcc/config/arm/libunwind.S b/libgcc/config/arm/libunwind.S index 3302447..50c58dc 100644 --- a/libgcc/config/arm/libunwind.S +++ b/libgcc/config/arm/libunwind.S @@ -46,7 +46,7 @@ EQUIV SYM (\name), SYM (__\name) .endm -#if (__ARM_ARCH__ == 4) +#if (__ARM_ARCH == 4) /* Some coprocessors require armv5t. We know this code will never be run on other cpus. Tell gas to allow armv5t, but only mark the objects as armv4. */