@@ -6703,6 +6703,22 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
&& opnds[0].reg.regno == opnds[1].reg.regno)
as_warn (_("unpredictable load of register pair -- `%s'"), str);
break;
+
+ case ldstexcl:
+ /* It is unpredictable if the destination and status registers are the
+ same. */
+ if ((aarch64_get_operand_class (opnds[0].type)
+ == AARCH64_OPND_CLASS_INT_REG)
+ && (aarch64_get_operand_class (opnds[1].type)
+ == AARCH64_OPND_CLASS_INT_REG)
+ && (opnds[0].reg.regno == opnds[1].reg.regno
+ || opnds[0].reg.regno == opnds[2].reg.regno))
+ as_warn (_("unpredictable: identical transfer and status registers"
+ " --`%s'"),
+ str);
+
+ break;
+
default:
break;
}
@@ -172,3 +172,13 @@
[^:]*:300: Warning: ignoring redefinition of register alias 'ip1'
[^:]*:301: Warning: ignoring redefinition of register alias 'lr'
[^:]*:302: Warning: ignoring redefinition of register alias 'fp'
+[^:]*:304: Warning: unpredictable: identical transfer and status registers --`stlxrb w26,w26,\[x0\]'
+[^:]*:305: Warning: unpredictable: identical transfer and status registers --`stlxrh w26,w26,\[x1\]'
+[^:]*:306: Warning: unpredictable: identical transfer and status registers --`stlxr w26,w26,\[x2\]'
+[^:]*:307: Warning: unpredictable: identical transfer and status registers --`stlxrb w26,w27,\[x26\]'
+[^:]*:308: Warning: unpredictable: identical transfer and status registers --`stlxrh w26,w27,\[x26\]'
+[^:]*:309: Warning: unpredictable: identical transfer and status registers --`stlxr w26,w27,\[x26\]'
+[^:]*:310: Warning: unpredictable: identical transfer and status registers --`stlxr w26,x27,\[x26\]'
+[^:]*:311: Warning: unpredictable: identical transfer and status registers --`stlxr w26,x26,\[x3\]'
+[^:]*:312: Warning: unpredictable: identical transfer and status registers --`ldxp x26,x26,\[x5\]'
+[^:]*:313: Warning: unpredictable: identical transfer and status registers --`ldxp x26,x1,\[x26\]'
@@ -300,3 +300,14 @@
ip1 .req x1
lr .req x2
fp .req x3
+
+ stlxrb w26, w26, [x0]
+ stlxrh w26, w26, [x1]
+ stlxr w26, w26, [x2]
+ stlxrb w26, w27, [x26]
+ stlxrh w26, w27, [x26]
+ stlxr w26, w27, [x26]
+ stlxr w26, x27, [x26]
+ stlxr w26, x26, [x3]
+ ldxp x26, x26, [x5]
+ ldxp x26, x1, [x26]
A recent case in golang highlighted that gas wasn't warning on these unpredictable cases in the architecture. Fixed thusly. Tested aarch64-none-elf. Ok ? regards Ramana 2018-06-17 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * config/tc-aarch64.c (warn_unpredictable_ldst): Add unpredictable cases for ldxp, stlxrb, stlxrh, stlxr. * testsuite/gas/aarch64/diagnostic.s: New tests. * testsuite/gas/aarch64/diagnostic.l: Adjust.