From patchwork Fri Jun 22 16:06:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 139721 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp1052946lji; Fri, 22 Jun 2018 09:08:33 -0700 (PDT) X-Google-Smtp-Source: ADUXVKK+nKDU2ADppwhInYgwDHAOduIorHiGFJPiWaoRybgVx5IIdfsb6fdX9kQ+cD1t+XG++KsW X-Received: by 2002:a62:1013:: with SMTP id y19-v6mr2385941pfi.166.1529683713190; Fri, 22 Jun 2018 09:08:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529683713; cv=none; d=google.com; s=arc-20160816; b=OzeBxzj8sAfLVexqNKHLTpBhfB9MwtwKspjSmWOnsvnAglTx1nVwQMfVPb9XkJs83M hK3L4Y/EAYwW7sjgbGb7vKvc6eVtZChdkw57TToBFHrsRUAxU3iN/b8VxrYfigQdK4Oy MnepVSvyk7kzXxkkR2ILhGm64W4L45IArkNorZDYrKDgFql8sElEZXaTwZlXt5leWFOW 4xLX9j4dWRnX3LgKTElgt5KOP52xFQuq0L0C9nxVm2q0Kj/FqyPw2m24X2vVzQOJIhyk kkyGEpwznlHIjoWI80LTm9/ueUhMXS47wZAK5Z5Zjl5brY7/z9z5ScameLi4M4a0W2SG AvgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=TY7lBRRVAqb7hx/EXgO/qzEjGYj1dbl+Ee4pESpsL2Q=; b=Jw+0BUJ5rufisGjRkixIwCDz9GQ7PYNaly2VkvF2iV+f+CgxG1TOUsCsD2ZS/s8v0b PDz653nKn/2FNGay9/hdQXn9TABggx9Nqm9qeaOT/zjtpLLHgHUCTfEyOejQ8+qRASAi LH4k23Q/Td29IHKvroK60sbV8B4vBpszmBmM0hx+m3BCLctOAfqRXYVxuFwNurYwsUqo nfPrCEyAMb4OQRDUi5NXAOuKcL7MGFmyvxJqScBjImPYncqwCn1QurRzNLuGuU6b5OQS IK7h1fAHkxXM70xXGZ1IIjouVXWApV7+fIXsLxPms6CCg16oXnyR5cg0+Cv4pFttq/Ko N2hg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=zKHPxcNU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u32-v6si6607235pgn.488.2018.06.22.09.08.32; Fri, 22 Jun 2018 09:08:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=zKHPxcNU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934094AbeFVQIR (ORCPT + 31 others); Fri, 22 Jun 2018 12:08:17 -0400 Received: from conuserg-12.nifty.com ([210.131.2.79]:30584 "EHLO conuserg-12.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933047AbeFVQIP (ORCPT ); Fri, 22 Jun 2018 12:08:15 -0400 Received: from grover.sesame (FL1-125-199-20-195.osk.mesh.ad.jp [125.199.20.195]) (authenticated) by conuserg-12.nifty.com with ESMTP id w5MG6m5e022587; Sat, 23 Jun 2018 01:06:52 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-12.nifty.com w5MG6m5e022587 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1529683613; bh=TY7lBRRVAqb7hx/EXgO/qzEjGYj1dbl+Ee4pESpsL2Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=zKHPxcNUsCGGVRdBjxmTTYeF0rATg1xiIBNStCDDLBx5T/AyTn33ZLDu4N6NFDelW a02MNy8e++zB9dGR76QbOQIdBzyYvGNN7fkKCEc0IQ76rEWByGkPlsxbGI8j65vBdw 98Gs9AzhPTHBeTgZB69/OdyJlR3MRGgwlf32KxyXZ+WGRmiannGXBE0WmtYxCU6rWx V9FH7WRe0QZTtTPpbMugg3zyR2nsFuRYRVAvtyWEh7xAiDijSuUAnF6SjNE6zRQ1E1 vdViTJLaS4aRQ2GHPPCGhdm+eV3Y6fizF6XkuDBGMrFBjfjZcpZEcacQGqrisR3tOp hwQsoLewV705Q== X-Nifty-SrcIP: [125.199.20.195] From: Masahiro Yamada To: linux-mtd@lists.infradead.org, Boris Brezillon Cc: Rob Herring , Miquel Raynal , Richard Weinberger , Masahiro Yamada , linux-kernel@vger.kernel.org, Marek Vasut , Brian Norris , David Woodhouse Subject: [PATCH v4 4/5] mtd: rawnand: denali_dt: add more clocks based on IP datasheet Date: Sat, 23 Jun 2018 01:06:37 +0900 Message-Id: <1529683598-25783-5-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529683598-25783-1-git-send-email-yamada.masahiro@socionext.com> References: <1529683598-25783-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently, denali_dt.c requires a single anonymous clock, but the Denali User's Guide requires three clocks for this IP: - clk: controller core clock - clk_x: bus interface clock - ecc_clk: clock at which ECC circuitry is run This commit supports these named clocks to represent the real hardware. For the backward compatibility, the driver still accepts a single clock just as before. The clk_x_rate is taken from the clock driver again if the named clock "clk_x" is available. This will happen only for future DT, hence the existing DT files are not affected. Signed-off-by: Masahiro Yamada Reviewed-by: Miquel Raynal Reviewed-by: Richard Weinberger Tested-by: Richard Weinberger --- Changes in v4: None Changes in v3: - Change the patch order so that the bug-fix one comes the first Changes in v2: - Split patches into sensible chunks drivers/mtd/nand/raw/denali_dt.c | 53 ++++++++++++++++++++++++++++++++++------ 1 file changed, 45 insertions(+), 8 deletions(-) -- 2.7.4 Reviewed-by: Boris Brezillon diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index 6b4bd16..afaae37 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -27,7 +27,9 @@ struct denali_dt { struct denali_nand_info denali; - struct clk *clk; + struct clk *clk; /* core clock */ + struct clk *clk_x; /* bus interface clock */ + struct clk *clk_ecc; /* ECC circuit clock */ }; struct denali_dt_data { @@ -115,28 +117,61 @@ static int denali_dt_probe(struct platform_device *pdev) if (IS_ERR(denali->host)) return PTR_ERR(denali->host); - dt->clk = devm_clk_get(dev, NULL); + /* + * A single anonymous clock is supported for the backward compatibility. + * New platforms should support all the named clocks. + */ + dt->clk = devm_clk_get(dev, "nand"); + if (IS_ERR(dt->clk)) + dt->clk = devm_clk_get(dev, NULL); if (IS_ERR(dt->clk)) { dev_err(dev, "no clk available\n"); return PTR_ERR(dt->clk); } + + dt->clk_x = devm_clk_get(dev, "nand_x"); + if (IS_ERR(dt->clk_x)) + dt->clk_x = NULL; + + dt->clk_ecc = devm_clk_get(dev, "ecc"); + if (IS_ERR(dt->clk_ecc)) + dt->clk_ecc = NULL; + ret = clk_prepare_enable(dt->clk); if (ret) return ret; - /* - * Hardcode the clock rate for the backward compatibility. - * This works for both SOCFPGA and UniPhier. - */ - denali->clk_x_rate = 200000000; + ret = clk_prepare_enable(dt->clk_x); + if (ret) + goto out_disable_clk; + + ret = clk_prepare_enable(dt->clk_ecc); + if (ret) + goto out_disable_clk_x; + + if (dt->clk_x) { + denali->clk_x_rate = clk_get_rate(dt->clk_x); + } else { + /* + * Hardcode the clock rates for the backward compatibility. + * This works for both SOCFPGA and UniPhier. + */ + dev_notice(dev, + "necessary clock is missing. default clock rates are used.\n"); + denali->clk_x_rate = 200000000; + } ret = denali_init(denali); if (ret) - goto out_disable_clk; + goto out_disable_clk_ecc; platform_set_drvdata(pdev, dt); return 0; +out_disable_clk_ecc: + clk_disable_unprepare(dt->clk_ecc); +out_disable_clk_x: + clk_disable_unprepare(dt->clk_x); out_disable_clk: clk_disable_unprepare(dt->clk); @@ -148,6 +183,8 @@ static int denali_dt_remove(struct platform_device *pdev) struct denali_dt *dt = platform_get_drvdata(pdev); denali_remove(&dt->denali); + clk_disable_unprepare(dt->clk_ecc); + clk_disable_unprepare(dt->clk_x); clk_disable_unprepare(dt->clk); return 0;