[edk2,edk2-platforms,1/2] Silicon/SynQuacer: add preliminary support for PCIe MMIO32 translation

Message ID 20180626104424.3524-2-ard.biesheuvel@linaro.org
State New
Headers show
Series
  • SynQuacer: enable MMIO translation
Related show

Commit Message

Ard Biesheuvel June 26, 2018, 10:44 a.m.
Add the basic support for enabling PCIe MMIO32 translation on the
SynQuacer, without actually enabling it just yet. It would allow us
to increase the bus range to 255 MB [from 127 MB] and the MMIO32
range to 512 MB or more [from 128 MB], but it is more likely to
cause compatibility issues with code ported from the PC platform.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

---
 Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl                                           | 8 ++++----
 Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h                                                  | 2 ++
 Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c            | 6 ++++--
 Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 2 +-
 4 files changed, 11 insertions(+), 7 deletions(-)

-- 
2.17.1

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Comments

Leif Lindholm June 26, 2018, 2:24 p.m. | #1
On Tue, Jun 26, 2018 at 12:44:23PM +0200, Ard Biesheuvel wrote:
> Add the basic support for enabling PCIe MMIO32 translation on the

> SynQuacer, without actually enabling it just yet. It would allow us

> to increase the bus range to 255 MB [from 127 MB] and the MMIO32

> range to 512 MB or more [from 128 MB], but it is more likely to

> cause compatibility issues with code ported from the PC platform.

> 

> Contributed-under: TianoCore Contribution Agreement 1.1

> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

> ---

>  Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl                                           | 8 ++++----

>  Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h                                                  | 2 ++

>  Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c            | 6 ++++--

>  Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 2 +-

>  4 files changed, 11 insertions(+), 7 deletions(-)

> 

> diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl

> index 51e9d0b22c3d..77d4763d1a85 100644

> --- a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl

> +++ b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl

> @@ -86,14 +86,14 @@ DefinitionBlock ("SsdtPci.aml", "SSDT", 1, "SNI", "SYNQUACR",

>                      SYNQUACER_PCI_SEG0_BUSNUM_RANGE // RangeLength - # of Busses

>                  )

>  

> -                DWordMemory ( // 32-bit BAR Windows

> +                QWordMemory ( // 32-bit BAR Windows

>                      ResourceProducer, PosDecode,

>                      MinFixed, MaxFixed,

>                      Cacheable, ReadWrite,

>                      0x00000000,                         // Granularity

>                      SYNQUACER_PCI_SEG0_MMIO32_MIN,      // Min Base Address

>                      SYNQUACER_PCI_SEG0_MMIO32_MAX,      // Max Base Address

> -                    0x00000000,                         // Translate

> +                    SYNQUACER_PCI_SEG0_MMIO32_XLATE,    // Translate

>                      SYNQUACER_PCI_SEG0_MMIO32_SIZE      // Length

>                  )

>  

> @@ -224,14 +224,14 @@ DefinitionBlock ("SsdtPci.aml", "SSDT", 1, "SNI", "SYNQUACR",

>                      SYNQUACER_PCI_SEG1_BUSNUM_RANGE // RangeLength - # of Busses

>                  )

>  

> -                DWordMemory ( // 32-bit BAR Windows

> +                QWordMemory ( // 32-bit BAR Windows

>                      ResourceProducer, PosDecode,

>                      MinFixed, MaxFixed,

>                      Cacheable, ReadWrite,

>                      0x00000000,                         // Granularity

>                      SYNQUACER_PCI_SEG1_MMIO32_MIN,      // Min Base Address

>                      SYNQUACER_PCI_SEG1_MMIO32_MAX,      // Max Base Address

> -                    0x00000000,                         // Translate

> +                    SYNQUACER_PCI_SEG1_MMIO32_XLATE,    // Translate

>                      SYNQUACER_PCI_SEG1_MMIO32_SIZE      // Length

>                  )

>  

> diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h

> index 950cece13e81..798f59db2a94 100644

> --- a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h

> +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h

> @@ -34,6 +34,7 @@

>  #define SYNQUACER_PCI_SEG0_MMIO32_MIN       0x68000000

>  #define SYNQUACER_PCI_SEG0_MMIO32_MAX       0x6fffffff

>  #define SYNQUACER_PCI_SEG0_MMIO32_SIZE      0x08000000

> +#define SYNQUACER_PCI_SEG0_MMIO32_XLATE     0x0

>  

>  #define SYNQUACER_PCI_SEG0_MMIO64_MIN       0x3e00000000

>  #define SYNQUACER_PCI_SEG0_MMIO64_MAX       0x3effffffff

> @@ -57,6 +58,7 @@

>  #define SYNQUACER_PCI_SEG1_MMIO32_MIN       0x78000000

>  #define SYNQUACER_PCI_SEG1_MMIO32_MAX       0x7fffffff

>  #define SYNQUACER_PCI_SEG1_MMIO32_SIZE      0x08000000

> +#define SYNQUACER_PCI_SEG1_MMIO32_XLATE     0x0

>  

>  #define SYNQUACER_PCI_SEG1_MMIO64_MIN       0x3f00000000

>  #define SYNQUACER_PCI_SEG1_MMIO64_MAX       0x3fffffffff

> diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c

> index 341939876bd3..7c096f0801dd 100644

> --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c

> +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c

> @@ -107,7 +107,8 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = {

>        SYNQUACER_PCI_SEG0_PORTIO_MAX,

>        MAX_UINT64 - SYNQUACER_PCI_SEG0_PORTIO_OFFSET + 1 },   // Io

>      { SYNQUACER_PCI_SEG0_MMIO32_MIN,

> -      SYNQUACER_PCI_SEG0_MMIO32_MAX },      // Mem

> +      SYNQUACER_PCI_SEG0_MMIO32_MAX,

> +      MAX_UINT64 - SYNQUACER_PCI_SEG0_MMIO32_XLATE + 1 },    // Mem


So, this had me scratching my head for a second.
I may get pickier about requring explicitly initializing the
Translation field in future, but for this patch:
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>


>      { SYNQUACER_PCI_SEG0_MMIO64_MIN,

>        SYNQUACER_PCI_SEG0_MMIO64_MAX },      // MemAbove4G

>      { MAX_UINT64, 0x0 },                    // PMem

> @@ -127,7 +128,8 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = {

>        SYNQUACER_PCI_SEG1_PORTIO_MAX,

>        MAX_UINT64 - SYNQUACER_PCI_SEG1_PORTIO_OFFSET + 1 },   // Io

>      { SYNQUACER_PCI_SEG1_MMIO32_MIN,

> -      SYNQUACER_PCI_SEG1_MMIO32_MAX },      // Mem

> +      SYNQUACER_PCI_SEG1_MMIO32_MAX,

> +      MAX_UINT64 - SYNQUACER_PCI_SEG1_MMIO32_XLATE + 1 },    // Mem

>      { SYNQUACER_PCI_SEG1_MMIO64_MIN,

>        SYNQUACER_PCI_SEG1_MMIO64_MAX },      // MemAbove4G

>      { MAX_UINT64, 0x0 },                    // PMem

> diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c

> index 227f9a725ce8..75a663e974e1 100644

> --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c

> +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c

> @@ -322,7 +322,7 @@ PciInitControllerPost (

>  

>    // Region 0: MMIO32 range

>    ConfigureWindow (DbiBase, 0,

> -    RootBridge->Mem.Base,

> +    RootBridge->Mem.Base - RootBridge->Mem.Translation,

>      RootBridge->Mem.Base,

>      RootBridge->Mem.Limit - RootBridge->Mem.Base + 1,

>      IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM |

> -- 

> 2.17.1

> 

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Ard Biesheuvel June 26, 2018, 2:25 p.m. | #2
On 26 June 2018 at 16:24, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> On Tue, Jun 26, 2018 at 12:44:23PM +0200, Ard Biesheuvel wrote:

>> Add the basic support for enabling PCIe MMIO32 translation on the

>> SynQuacer, without actually enabling it just yet. It would allow us

>> to increase the bus range to 255 MB [from 127 MB] and the MMIO32

>> range to 512 MB or more [from 128 MB], but it is more likely to

>> cause compatibility issues with code ported from the PC platform.

>>

>> Contributed-under: TianoCore Contribution Agreement 1.1

>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

>> ---

>>  Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl                                           | 8 ++++----

>>  Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h                                                  | 2 ++

>>  Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c            | 6 ++++--

>>  Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 2 +-

>>  4 files changed, 11 insertions(+), 7 deletions(-)

>>

>> diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl

>> index 51e9d0b22c3d..77d4763d1a85 100644

>> --- a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl

>> +++ b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl

>> @@ -86,14 +86,14 @@ DefinitionBlock ("SsdtPci.aml", "SSDT", 1, "SNI", "SYNQUACR",

>>                      SYNQUACER_PCI_SEG0_BUSNUM_RANGE // RangeLength - # of Busses

>>                  )

>>

>> -                DWordMemory ( // 32-bit BAR Windows

>> +                QWordMemory ( // 32-bit BAR Windows

>>                      ResourceProducer, PosDecode,

>>                      MinFixed, MaxFixed,

>>                      Cacheable, ReadWrite,

>>                      0x00000000,                         // Granularity

>>                      SYNQUACER_PCI_SEG0_MMIO32_MIN,      // Min Base Address

>>                      SYNQUACER_PCI_SEG0_MMIO32_MAX,      // Max Base Address

>> -                    0x00000000,                         // Translate

>> +                    SYNQUACER_PCI_SEG0_MMIO32_XLATE,    // Translate

>>                      SYNQUACER_PCI_SEG0_MMIO32_SIZE      // Length

>>                  )

>>

>> @@ -224,14 +224,14 @@ DefinitionBlock ("SsdtPci.aml", "SSDT", 1, "SNI", "SYNQUACR",

>>                      SYNQUACER_PCI_SEG1_BUSNUM_RANGE // RangeLength - # of Busses

>>                  )

>>

>> -                DWordMemory ( // 32-bit BAR Windows

>> +                QWordMemory ( // 32-bit BAR Windows

>>                      ResourceProducer, PosDecode,

>>                      MinFixed, MaxFixed,

>>                      Cacheable, ReadWrite,

>>                      0x00000000,                         // Granularity

>>                      SYNQUACER_PCI_SEG1_MMIO32_MIN,      // Min Base Address

>>                      SYNQUACER_PCI_SEG1_MMIO32_MAX,      // Max Base Address

>> -                    0x00000000,                         // Translate

>> +                    SYNQUACER_PCI_SEG1_MMIO32_XLATE,    // Translate

>>                      SYNQUACER_PCI_SEG1_MMIO32_SIZE      // Length

>>                  )

>>

>> diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h

>> index 950cece13e81..798f59db2a94 100644

>> --- a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h

>> +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h

>> @@ -34,6 +34,7 @@

>>  #define SYNQUACER_PCI_SEG0_MMIO32_MIN       0x68000000

>>  #define SYNQUACER_PCI_SEG0_MMIO32_MAX       0x6fffffff

>>  #define SYNQUACER_PCI_SEG0_MMIO32_SIZE      0x08000000

>> +#define SYNQUACER_PCI_SEG0_MMIO32_XLATE     0x0

>>

>>  #define SYNQUACER_PCI_SEG0_MMIO64_MIN       0x3e00000000

>>  #define SYNQUACER_PCI_SEG0_MMIO64_MAX       0x3effffffff

>> @@ -57,6 +58,7 @@

>>  #define SYNQUACER_PCI_SEG1_MMIO32_MIN       0x78000000

>>  #define SYNQUACER_PCI_SEG1_MMIO32_MAX       0x7fffffff

>>  #define SYNQUACER_PCI_SEG1_MMIO32_SIZE      0x08000000

>> +#define SYNQUACER_PCI_SEG1_MMIO32_XLATE     0x0

>>

>>  #define SYNQUACER_PCI_SEG1_MMIO64_MIN       0x3f00000000

>>  #define SYNQUACER_PCI_SEG1_MMIO64_MAX       0x3fffffffff

>> diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c

>> index 341939876bd3..7c096f0801dd 100644

>> --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c

>> +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c

>> @@ -107,7 +107,8 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = {

>>        SYNQUACER_PCI_SEG0_PORTIO_MAX,

>>        MAX_UINT64 - SYNQUACER_PCI_SEG0_PORTIO_OFFSET + 1 },   // Io

>>      { SYNQUACER_PCI_SEG0_MMIO32_MIN,

>> -      SYNQUACER_PCI_SEG0_MMIO32_MAX },      // Mem

>> +      SYNQUACER_PCI_SEG0_MMIO32_MAX,

>> +      MAX_UINT64 - SYNQUACER_PCI_SEG0_MMIO32_XLATE + 1 },    // Mem

>

> So, this had me scratching my head for a second.

> I may get pickier about requring explicitly initializing the

> Translation field in future, but for this patch:

> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

>


That field did not exist yet when this code was merged. It was
introduced by Heyi's recent PCI patches.

>>      { SYNQUACER_PCI_SEG0_MMIO64_MIN,

>>        SYNQUACER_PCI_SEG0_MMIO64_MAX },      // MemAbove4G

>>      { MAX_UINT64, 0x0 },                    // PMem

>> @@ -127,7 +128,8 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = {

>>        SYNQUACER_PCI_SEG1_PORTIO_MAX,

>>        MAX_UINT64 - SYNQUACER_PCI_SEG1_PORTIO_OFFSET + 1 },   // Io

>>      { SYNQUACER_PCI_SEG1_MMIO32_MIN,

>> -      SYNQUACER_PCI_SEG1_MMIO32_MAX },      // Mem

>> +      SYNQUACER_PCI_SEG1_MMIO32_MAX,

>> +      MAX_UINT64 - SYNQUACER_PCI_SEG1_MMIO32_XLATE + 1 },    // Mem

>>      { SYNQUACER_PCI_SEG1_MMIO64_MIN,

>>        SYNQUACER_PCI_SEG1_MMIO64_MAX },      // MemAbove4G

>>      { MAX_UINT64, 0x0 },                    // PMem

>> diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c

>> index 227f9a725ce8..75a663e974e1 100644

>> --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c

>> +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c

>> @@ -322,7 +322,7 @@ PciInitControllerPost (

>>

>>    // Region 0: MMIO32 range

>>    ConfigureWindow (DbiBase, 0,

>> -    RootBridge->Mem.Base,

>> +    RootBridge->Mem.Base - RootBridge->Mem.Translation,

>>      RootBridge->Mem.Base,

>>      RootBridge->Mem.Limit - RootBridge->Mem.Base + 1,

>>      IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM |

>> --

>> 2.17.1

>>

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Leif Lindholm June 26, 2018, 2:34 p.m. | #3
On Tue, Jun 26, 2018 at 04:25:46PM +0200, Ard Biesheuvel wrote:
> On 26 June 2018 at 16:24, Leif Lindholm <leif.lindholm@linaro.org> wrote:

> > On Tue, Jun 26, 2018 at 12:44:23PM +0200, Ard Biesheuvel wrote:

> >> Add the basic support for enabling PCIe MMIO32 translation on the

> >> SynQuacer, without actually enabling it just yet. It would allow us

> >> to increase the bus range to 255 MB [from 127 MB] and the MMIO32

> >> range to 512 MB or more [from 128 MB], but it is more likely to

> >> cause compatibility issues with code ported from the PC platform.

> >>

> >> Contributed-under: TianoCore Contribution Agreement 1.1

> >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

> >> ---

> >>  Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl                                           | 8 ++++----

> >>  Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h                                                  | 2 ++

> >>  Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c            | 6 ++++--

> >>  Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 2 +-

> >>  4 files changed, 11 insertions(+), 7 deletions(-)

> >>

> >> diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl

> >> index 51e9d0b22c3d..77d4763d1a85 100644

> >> --- a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl

> >> +++ b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl

> >> @@ -86,14 +86,14 @@ DefinitionBlock ("SsdtPci.aml", "SSDT", 1, "SNI", "SYNQUACR",

> >>                      SYNQUACER_PCI_SEG0_BUSNUM_RANGE // RangeLength - # of Busses

> >>                  )

> >>

> >> -                DWordMemory ( // 32-bit BAR Windows

> >> +                QWordMemory ( // 32-bit BAR Windows

> >>                      ResourceProducer, PosDecode,

> >>                      MinFixed, MaxFixed,

> >>                      Cacheable, ReadWrite,

> >>                      0x00000000,                         // Granularity

> >>                      SYNQUACER_PCI_SEG0_MMIO32_MIN,      // Min Base Address

> >>                      SYNQUACER_PCI_SEG0_MMIO32_MAX,      // Max Base Address

> >> -                    0x00000000,                         // Translate

> >> +                    SYNQUACER_PCI_SEG0_MMIO32_XLATE,    // Translate

> >>                      SYNQUACER_PCI_SEG0_MMIO32_SIZE      // Length

> >>                  )

> >>

> >> @@ -224,14 +224,14 @@ DefinitionBlock ("SsdtPci.aml", "SSDT", 1, "SNI", "SYNQUACR",

> >>                      SYNQUACER_PCI_SEG1_BUSNUM_RANGE // RangeLength - # of Busses

> >>                  )

> >>

> >> -                DWordMemory ( // 32-bit BAR Windows

> >> +                QWordMemory ( // 32-bit BAR Windows

> >>                      ResourceProducer, PosDecode,

> >>                      MinFixed, MaxFixed,

> >>                      Cacheable, ReadWrite,

> >>                      0x00000000,                         // Granularity

> >>                      SYNQUACER_PCI_SEG1_MMIO32_MIN,      // Min Base Address

> >>                      SYNQUACER_PCI_SEG1_MMIO32_MAX,      // Max Base Address

> >> -                    0x00000000,                         // Translate

> >> +                    SYNQUACER_PCI_SEG1_MMIO32_XLATE,    // Translate

> >>                      SYNQUACER_PCI_SEG1_MMIO32_SIZE      // Length

> >>                  )

> >>

> >> diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h

> >> index 950cece13e81..798f59db2a94 100644

> >> --- a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h

> >> +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h

> >> @@ -34,6 +34,7 @@

> >>  #define SYNQUACER_PCI_SEG0_MMIO32_MIN       0x68000000

> >>  #define SYNQUACER_PCI_SEG0_MMIO32_MAX       0x6fffffff

> >>  #define SYNQUACER_PCI_SEG0_MMIO32_SIZE      0x08000000

> >> +#define SYNQUACER_PCI_SEG0_MMIO32_XLATE     0x0

> >>

> >>  #define SYNQUACER_PCI_SEG0_MMIO64_MIN       0x3e00000000

> >>  #define SYNQUACER_PCI_SEG0_MMIO64_MAX       0x3effffffff

> >> @@ -57,6 +58,7 @@

> >>  #define SYNQUACER_PCI_SEG1_MMIO32_MIN       0x78000000

> >>  #define SYNQUACER_PCI_SEG1_MMIO32_MAX       0x7fffffff

> >>  #define SYNQUACER_PCI_SEG1_MMIO32_SIZE      0x08000000

> >> +#define SYNQUACER_PCI_SEG1_MMIO32_XLATE     0x0

> >>

> >>  #define SYNQUACER_PCI_SEG1_MMIO64_MIN       0x3f00000000

> >>  #define SYNQUACER_PCI_SEG1_MMIO64_MAX       0x3fffffffff

> >> diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c

> >> index 341939876bd3..7c096f0801dd 100644

> >> --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c

> >> +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c

> >> @@ -107,7 +107,8 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = {

> >>        SYNQUACER_PCI_SEG0_PORTIO_MAX,

> >>        MAX_UINT64 - SYNQUACER_PCI_SEG0_PORTIO_OFFSET + 1 },   // Io

> >>      { SYNQUACER_PCI_SEG0_MMIO32_MIN,

> >> -      SYNQUACER_PCI_SEG0_MMIO32_MAX },      // Mem

> >> +      SYNQUACER_PCI_SEG0_MMIO32_MAX,

> >> +      MAX_UINT64 - SYNQUACER_PCI_SEG0_MMIO32_XLATE + 1 },    // Mem

> >

> > So, this had me scratching my head for a second.

> > I may get pickier about requring explicitly initializing the

> > Translation field in future, but for this patch:

> > Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

> >

> 

> That field did not exist yet when this code was merged. It was

> introduced by Heyi's recent PCI patches.


Ah, fair enough.
Slightly unfortunate C just silently lets that through though...

/
    Leif

> >>      { SYNQUACER_PCI_SEG0_MMIO64_MIN,

> >>        SYNQUACER_PCI_SEG0_MMIO64_MAX },      // MemAbove4G

> >>      { MAX_UINT64, 0x0 },                    // PMem

> >> @@ -127,7 +128,8 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = {

> >>        SYNQUACER_PCI_SEG1_PORTIO_MAX,

> >>        MAX_UINT64 - SYNQUACER_PCI_SEG1_PORTIO_OFFSET + 1 },   // Io

> >>      { SYNQUACER_PCI_SEG1_MMIO32_MIN,

> >> -      SYNQUACER_PCI_SEG1_MMIO32_MAX },      // Mem

> >> +      SYNQUACER_PCI_SEG1_MMIO32_MAX,

> >> +      MAX_UINT64 - SYNQUACER_PCI_SEG1_MMIO32_XLATE + 1 },    // Mem

> >>      { SYNQUACER_PCI_SEG1_MMIO64_MIN,

> >>        SYNQUACER_PCI_SEG1_MMIO64_MAX },      // MemAbove4G

> >>      { MAX_UINT64, 0x0 },                    // PMem

> >> diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c

> >> index 227f9a725ce8..75a663e974e1 100644

> >> --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c

> >> +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c

> >> @@ -322,7 +322,7 @@ PciInitControllerPost (

> >>

> >>    // Region 0: MMIO32 range

> >>    ConfigureWindow (DbiBase, 0,

> >> -    RootBridge->Mem.Base,

> >> +    RootBridge->Mem.Base - RootBridge->Mem.Translation,

> >>      RootBridge->Mem.Base,

> >>      RootBridge->Mem.Limit - RootBridge->Mem.Base + 1,

> >>      IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM |

> >> --

> >> 2.17.1

> >>

_______________________________________________
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Ard Biesheuvel June 26, 2018, 6:21 p.m. | #4
On 26 June 2018 at 16:34, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> On Tue, Jun 26, 2018 at 04:25:46PM +0200, Ard Biesheuvel wrote:

>> On 26 June 2018 at 16:24, Leif Lindholm <leif.lindholm@linaro.org> wrote:

>> > On Tue, Jun 26, 2018 at 12:44:23PM +0200, Ard Biesheuvel wrote:

>> >> Add the basic support for enabling PCIe MMIO32 translation on the

>> >> SynQuacer, without actually enabling it just yet. It would allow us

>> >> to increase the bus range to 255 MB [from 127 MB] and the MMIO32

>> >> range to 512 MB or more [from 128 MB], but it is more likely to

>> >> cause compatibility issues with code ported from the PC platform.

>> >>

>> >> Contributed-under: TianoCore Contribution Agreement 1.1

>> >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

>> >> ---

>> >>  Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl                                           | 8 ++++----

>> >>  Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h                                                  | 2 ++

>> >>  Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c            | 6 ++++--

>> >>  Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 2 +-

>> >>  4 files changed, 11 insertions(+), 7 deletions(-)

>> >>

>> >> diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl

>> >> index 51e9d0b22c3d..77d4763d1a85 100644

>> >> --- a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl

>> >> +++ b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl

>> >> @@ -86,14 +86,14 @@ DefinitionBlock ("SsdtPci.aml", "SSDT", 1, "SNI", "SYNQUACR",

>> >>                      SYNQUACER_PCI_SEG0_BUSNUM_RANGE // RangeLength - # of Busses

>> >>                  )

>> >>

>> >> -                DWordMemory ( // 32-bit BAR Windows

>> >> +                QWordMemory ( // 32-bit BAR Windows

>> >>                      ResourceProducer, PosDecode,

>> >>                      MinFixed, MaxFixed,

>> >>                      Cacheable, ReadWrite,

>> >>                      0x00000000,                         // Granularity

>> >>                      SYNQUACER_PCI_SEG0_MMIO32_MIN,      // Min Base Address

>> >>                      SYNQUACER_PCI_SEG0_MMIO32_MAX,      // Max Base Address

>> >> -                    0x00000000,                         // Translate

>> >> +                    SYNQUACER_PCI_SEG0_MMIO32_XLATE,    // Translate

>> >>                      SYNQUACER_PCI_SEG0_MMIO32_SIZE      // Length

>> >>                  )

>> >>

>> >> @@ -224,14 +224,14 @@ DefinitionBlock ("SsdtPci.aml", "SSDT", 1, "SNI", "SYNQUACR",

>> >>                      SYNQUACER_PCI_SEG1_BUSNUM_RANGE // RangeLength - # of Busses

>> >>                  )

>> >>

>> >> -                DWordMemory ( // 32-bit BAR Windows

>> >> +                QWordMemory ( // 32-bit BAR Windows

>> >>                      ResourceProducer, PosDecode,

>> >>                      MinFixed, MaxFixed,

>> >>                      Cacheable, ReadWrite,

>> >>                      0x00000000,                         // Granularity

>> >>                      SYNQUACER_PCI_SEG1_MMIO32_MIN,      // Min Base Address

>> >>                      SYNQUACER_PCI_SEG1_MMIO32_MAX,      // Max Base Address

>> >> -                    0x00000000,                         // Translate

>> >> +                    SYNQUACER_PCI_SEG1_MMIO32_XLATE,    // Translate

>> >>                      SYNQUACER_PCI_SEG1_MMIO32_SIZE      // Length

>> >>                  )

>> >>

>> >> diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h

>> >> index 950cece13e81..798f59db2a94 100644

>> >> --- a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h

>> >> +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h

>> >> @@ -34,6 +34,7 @@

>> >>  #define SYNQUACER_PCI_SEG0_MMIO32_MIN       0x68000000

>> >>  #define SYNQUACER_PCI_SEG0_MMIO32_MAX       0x6fffffff

>> >>  #define SYNQUACER_PCI_SEG0_MMIO32_SIZE      0x08000000

>> >> +#define SYNQUACER_PCI_SEG0_MMIO32_XLATE     0x0

>> >>

>> >>  #define SYNQUACER_PCI_SEG0_MMIO64_MIN       0x3e00000000

>> >>  #define SYNQUACER_PCI_SEG0_MMIO64_MAX       0x3effffffff

>> >> @@ -57,6 +58,7 @@

>> >>  #define SYNQUACER_PCI_SEG1_MMIO32_MIN       0x78000000

>> >>  #define SYNQUACER_PCI_SEG1_MMIO32_MAX       0x7fffffff

>> >>  #define SYNQUACER_PCI_SEG1_MMIO32_SIZE      0x08000000

>> >> +#define SYNQUACER_PCI_SEG1_MMIO32_XLATE     0x0

>> >>

>> >>  #define SYNQUACER_PCI_SEG1_MMIO64_MIN       0x3f00000000

>> >>  #define SYNQUACER_PCI_SEG1_MMIO64_MAX       0x3fffffffff

>> >> diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c

>> >> index 341939876bd3..7c096f0801dd 100644

>> >> --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c

>> >> +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c

>> >> @@ -107,7 +107,8 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = {

>> >>        SYNQUACER_PCI_SEG0_PORTIO_MAX,

>> >>        MAX_UINT64 - SYNQUACER_PCI_SEG0_PORTIO_OFFSET + 1 },   // Io

>> >>      { SYNQUACER_PCI_SEG0_MMIO32_MIN,

>> >> -      SYNQUACER_PCI_SEG0_MMIO32_MAX },      // Mem

>> >> +      SYNQUACER_PCI_SEG0_MMIO32_MAX,

>> >> +      MAX_UINT64 - SYNQUACER_PCI_SEG0_MMIO32_XLATE + 1 },    // Mem

>> >

>> > So, this had me scratching my head for a second.

>> > I may get pickier about requring explicitly initializing the

>> > Translation field in future, but for this patch:

>> > Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

>> >

>>

>> That field did not exist yet when this code was merged. It was

>> introduced by Heyi's recent PCI patches.

>

> Ah, fair enough.

> Slightly unfortunate C just silently lets that through though...

>

> /

>     Leif

>


Pushed as 3165d24e0c85..5ed298efba3b

Thanks

>> >>      { SYNQUACER_PCI_SEG0_MMIO64_MIN,

>> >>        SYNQUACER_PCI_SEG0_MMIO64_MAX },      // MemAbove4G

>> >>      { MAX_UINT64, 0x0 },                    // PMem

>> >> @@ -127,7 +128,8 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = {

>> >>        SYNQUACER_PCI_SEG1_PORTIO_MAX,

>> >>        MAX_UINT64 - SYNQUACER_PCI_SEG1_PORTIO_OFFSET + 1 },   // Io

>> >>      { SYNQUACER_PCI_SEG1_MMIO32_MIN,

>> >> -      SYNQUACER_PCI_SEG1_MMIO32_MAX },      // Mem

>> >> +      SYNQUACER_PCI_SEG1_MMIO32_MAX,

>> >> +      MAX_UINT64 - SYNQUACER_PCI_SEG1_MMIO32_XLATE + 1 },    // Mem

>> >>      { SYNQUACER_PCI_SEG1_MMIO64_MIN,

>> >>        SYNQUACER_PCI_SEG1_MMIO64_MAX },      // MemAbove4G

>> >>      { MAX_UINT64, 0x0 },                    // PMem

>> >> diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c

>> >> index 227f9a725ce8..75a663e974e1 100644

>> >> --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c

>> >> +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c

>> >> @@ -322,7 +322,7 @@ PciInitControllerPost (

>> >>

>> >>    // Region 0: MMIO32 range

>> >>    ConfigureWindow (DbiBase, 0,

>> >> -    RootBridge->Mem.Base,

>> >> +    RootBridge->Mem.Base - RootBridge->Mem.Translation,

>> >>      RootBridge->Mem.Base,

>> >>      RootBridge->Mem.Limit - RootBridge->Mem.Base + 1,

>> >>      IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM |

>> >> --

>> >> 2.17.1

>> >>

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Patch

diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl
index 51e9d0b22c3d..77d4763d1a85 100644
--- a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl
+++ b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl
@@ -86,14 +86,14 @@  DefinitionBlock ("SsdtPci.aml", "SSDT", 1, "SNI", "SYNQUACR",
                     SYNQUACER_PCI_SEG0_BUSNUM_RANGE // RangeLength - # of Busses
                 )
 
-                DWordMemory ( // 32-bit BAR Windows
+                QWordMemory ( // 32-bit BAR Windows
                     ResourceProducer, PosDecode,
                     MinFixed, MaxFixed,
                     Cacheable, ReadWrite,
                     0x00000000,                         // Granularity
                     SYNQUACER_PCI_SEG0_MMIO32_MIN,      // Min Base Address
                     SYNQUACER_PCI_SEG0_MMIO32_MAX,      // Max Base Address
-                    0x00000000,                         // Translate
+                    SYNQUACER_PCI_SEG0_MMIO32_XLATE,    // Translate
                     SYNQUACER_PCI_SEG0_MMIO32_SIZE      // Length
                 )
 
@@ -224,14 +224,14 @@  DefinitionBlock ("SsdtPci.aml", "SSDT", 1, "SNI", "SYNQUACR",
                     SYNQUACER_PCI_SEG1_BUSNUM_RANGE // RangeLength - # of Busses
                 )
 
-                DWordMemory ( // 32-bit BAR Windows
+                QWordMemory ( // 32-bit BAR Windows
                     ResourceProducer, PosDecode,
                     MinFixed, MaxFixed,
                     Cacheable, ReadWrite,
                     0x00000000,                         // Granularity
                     SYNQUACER_PCI_SEG1_MMIO32_MIN,      // Min Base Address
                     SYNQUACER_PCI_SEG1_MMIO32_MAX,      // Max Base Address
-                    0x00000000,                         // Translate
+                    SYNQUACER_PCI_SEG1_MMIO32_XLATE,    // Translate
                     SYNQUACER_PCI_SEG1_MMIO32_SIZE      // Length
                 )
 
diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h
index 950cece13e81..798f59db2a94 100644
--- a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h
+++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h
@@ -34,6 +34,7 @@ 
 #define SYNQUACER_PCI_SEG0_MMIO32_MIN       0x68000000
 #define SYNQUACER_PCI_SEG0_MMIO32_MAX       0x6fffffff
 #define SYNQUACER_PCI_SEG0_MMIO32_SIZE      0x08000000
+#define SYNQUACER_PCI_SEG0_MMIO32_XLATE     0x0
 
 #define SYNQUACER_PCI_SEG0_MMIO64_MIN       0x3e00000000
 #define SYNQUACER_PCI_SEG0_MMIO64_MAX       0x3effffffff
@@ -57,6 +58,7 @@ 
 #define SYNQUACER_PCI_SEG1_MMIO32_MIN       0x78000000
 #define SYNQUACER_PCI_SEG1_MMIO32_MAX       0x7fffffff
 #define SYNQUACER_PCI_SEG1_MMIO32_SIZE      0x08000000
+#define SYNQUACER_PCI_SEG1_MMIO32_XLATE     0x0
 
 #define SYNQUACER_PCI_SEG1_MMIO64_MIN       0x3f00000000
 #define SYNQUACER_PCI_SEG1_MMIO64_MAX       0x3fffffffff
diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c
index 341939876bd3..7c096f0801dd 100644
--- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c
+++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c
@@ -107,7 +107,8 @@  PCI_ROOT_BRIDGE mPciRootBridges[] = {
       SYNQUACER_PCI_SEG0_PORTIO_MAX,
       MAX_UINT64 - SYNQUACER_PCI_SEG0_PORTIO_OFFSET + 1 },   // Io
     { SYNQUACER_PCI_SEG0_MMIO32_MIN,
-      SYNQUACER_PCI_SEG0_MMIO32_MAX },      // Mem
+      SYNQUACER_PCI_SEG0_MMIO32_MAX,
+      MAX_UINT64 - SYNQUACER_PCI_SEG0_MMIO32_XLATE + 1 },    // Mem
     { SYNQUACER_PCI_SEG0_MMIO64_MIN,
       SYNQUACER_PCI_SEG0_MMIO64_MAX },      // MemAbove4G
     { MAX_UINT64, 0x0 },                    // PMem
@@ -127,7 +128,8 @@  PCI_ROOT_BRIDGE mPciRootBridges[] = {
       SYNQUACER_PCI_SEG1_PORTIO_MAX,
       MAX_UINT64 - SYNQUACER_PCI_SEG1_PORTIO_OFFSET + 1 },   // Io
     { SYNQUACER_PCI_SEG1_MMIO32_MIN,
-      SYNQUACER_PCI_SEG1_MMIO32_MAX },      // Mem
+      SYNQUACER_PCI_SEG1_MMIO32_MAX,
+      MAX_UINT64 - SYNQUACER_PCI_SEG1_MMIO32_XLATE + 1 },    // Mem
     { SYNQUACER_PCI_SEG1_MMIO64_MIN,
       SYNQUACER_PCI_SEG1_MMIO64_MAX },      // MemAbove4G
     { MAX_UINT64, 0x0 },                    // PMem
diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c
index 227f9a725ce8..75a663e974e1 100644
--- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c
+++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c
@@ -322,7 +322,7 @@  PciInitControllerPost (
 
   // Region 0: MMIO32 range
   ConfigureWindow (DbiBase, 0,
-    RootBridge->Mem.Base,
+    RootBridge->Mem.Base - RootBridge->Mem.Translation,
     RootBridge->Mem.Base,
     RootBridge->Mem.Limit - RootBridge->Mem.Base + 1,
     IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM |