[edk2,edk2-platforms,2/2] Silicon/Socionext/SynQuacer: use single translated MMIO window for PCI1

Message ID 20180626104424.3524-3-ard.biesheuvel@linaro.org
State New
Headers show
Series
  • SynQuacer: enable MMIO translation
Related show

Commit Message

Ard Biesheuvel June 26, 2018, 10:44 a.m.
For testing purposes, reconfigure the second PCI host bridge to only
expose a single MMIO window of 512 MB in size, and map it below 4 GB
on the PCI side (so 32-bit BARs can be allocated from it) and above
4 GB on the CPU side.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

---
 Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl                                | 11 -----------
 Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi                                     | 11 +++++------
 Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h                                       | 20 ++++++++++----------
 Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c |  5 ++---
 4 files changed, 17 insertions(+), 30 deletions(-)

-- 
2.17.1

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Patch

diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl
index 77d4763d1a85..e59d4cf98ebe 100644
--- a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl
+++ b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl
@@ -235,17 +235,6 @@  DefinitionBlock ("SsdtPci.aml", "SSDT", 1, "SNI", "SYNQUACR",
                     SYNQUACER_PCI_SEG1_MMIO32_SIZE      // Length
                 )
 
-                QWordMemory ( // 64-bit BAR Windows
-                    ResourceProducer, PosDecode,
-                    MinFixed, MaxFixed,
-                    Cacheable, ReadWrite,
-                    0x00000000,                         // Granularity
-                    SYNQUACER_PCI_SEG1_MMIO64_MIN,      // Min Base Address
-                    SYNQUACER_PCI_SEG1_MMIO64_MAX,      // Max Base Address
-                    0x00000000,                         // Translate
-                    SYNQUACER_PCI_SEG1_MMIO64_SIZE      // Length
-                )
-
                 DWordIo ( // IO window
                     ResourceProducer,
                     MinFixed,
diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
index 37d642e4b237..57d111c65bc2 100644
--- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
+++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
@@ -478,19 +478,18 @@ 
     pcie1: pcie@70000000 {
         compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
         device_type = "pci";
-        reg = <0x0 0x70000000 0x0 0x7f00000>;
-        bus-range = <0x0 0x7e>;
+        reg = <0x0 0x70000000 0x0 0xff00000>;
+        bus-range = <0x0 0xfe>;
         #address-cells = <3>;
         #size-cells = <2>;
-        ranges = <0x1000000 0x00 0x00000000 0x00 0x77f00000 0x0 0x00010000>,
-                 <0x2000000 0x00 0x78000000 0x00 0x78000000 0x0 0x08000000>,
-                 <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>;
+        ranges = <0x1000000 0x00 0x00000000 0x00 0x7ff00000 0x0 0x00010000>,
+                 <0x2000000 0x3f 0xe0000000 0x00 0x20000000 0x0 0x20000000>;
 
         #interrupt-cells = <0x1>;
         interrupt-map-mask = <0x0 0x0 0x0 0x0>;
         interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
 
-        msi-map = <0x0 &its 0x10000 0x7f00>;
+        msi-map = <0x0 &its 0x10000 0xff00>;
         dma-coherent;
     };
 
diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h
index 798f59db2a94..643c1a581d0a 100644
--- a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h
+++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h
@@ -41,28 +41,28 @@ 
 #define SYNQUACER_PCI_SEG0_MMIO64_SIZE      0x100000000
 
 #define SYNQUACER_PCI_SEG1_CONFIG_BASE      0x70000000
-#define SYNQUACER_PCI_SEG1_CONFIG_SIZE      0x07f00000
+#define SYNQUACER_PCI_SEG1_CONFIG_SIZE      0x0ff00000
 #define SYNQUACER_PCI_SEG1_DBI_BASE         0x583c0000
 #define SYNQUACER_PCI_SEG1_EXS_BASE         0x58380000
 
 #define SYNQUACER_PCI_SEG1_BUSNUM_MIN       0x0
-#define SYNQUACER_PCI_SEG1_BUSNUM_MAX       0x7e
-#define SYNQUACER_PCI_SEG1_BUSNUM_RANGE     0x7f
+#define SYNQUACER_PCI_SEG1_BUSNUM_MAX       0xfe
+#define SYNQUACER_PCI_SEG1_BUSNUM_RANGE     0xff
 
 #define SYNQUACER_PCI_SEG1_PORTIO_MIN       0x0
 #define SYNQUACER_PCI_SEG1_PORTIO_MAX       0xffff
-#define SYNQUACER_PCI_SEG1_PORTIO_MEMBASE   0x77f00000
+#define SYNQUACER_PCI_SEG1_PORTIO_MEMBASE   0x7ff00000
 #define SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE   0x10000
 #define SYNQUACER_PCI_SEG1_PORTIO_OFFSET    0x10000
 
-#define SYNQUACER_PCI_SEG1_MMIO32_MIN       0x78000000
-#define SYNQUACER_PCI_SEG1_MMIO32_MAX       0x7fffffff
-#define SYNQUACER_PCI_SEG1_MMIO32_SIZE      0x08000000
-#define SYNQUACER_PCI_SEG1_MMIO32_XLATE     0x0
+#define SYNQUACER_PCI_SEG1_MMIO32_MIN       0x20000000
+#define SYNQUACER_PCI_SEG1_MMIO32_MAX       0x3fffffff
+#define SYNQUACER_PCI_SEG1_MMIO32_SIZE      0x20000000
+#define SYNQUACER_PCI_SEG1_MMIO32_XLATE     0x3fc0000000
 
 #define SYNQUACER_PCI_SEG1_MMIO64_MIN       0x3f00000000
-#define SYNQUACER_PCI_SEG1_MMIO64_MAX       0x3fffffffff
-#define SYNQUACER_PCI_SEG1_MMIO64_SIZE      0x100000000
+#define SYNQUACER_PCI_SEG1_MMIO64_MAX       0x3fdfffffff
+#define SYNQUACER_PCI_SEG1_MMIO64_SIZE      0xe0000000
 
 #define SYNQUACER_PCI_LOCATION(s,b,d)       (((s) << 16) | ((b) << 8) | (d))
 #define SYNQUACER_PCI_SLOT0_LOCATION        SYNQUACER_PCI_LOCATION(1, 0, 0)
diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c
index 7c096f0801dd..cf8ea6da2095 100644
--- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c
+++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c
@@ -121,7 +121,7 @@  PCI_ROOT_BRIDGE mPciRootBridges[] = {
     TRUE,                                   // DmaAbove4G
     FALSE,                                  // NoExtendedConfigSpace
     FALSE,                                  // ResourceAssigned
-    PCI_ALLOCATION_ATTRIBUTES,              // AllocationAttributes
+    EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM,   // AllocationAttributes
     { SYNQUACER_PCI_SEG1_BUSNUM_MIN,
       SYNQUACER_PCI_SEG1_BUSNUM_MAX },      // Bus
     { SYNQUACER_PCI_SEG1_PORTIO_MIN,
@@ -130,8 +130,7 @@  PCI_ROOT_BRIDGE mPciRootBridges[] = {
     { SYNQUACER_PCI_SEG1_MMIO32_MIN,
       SYNQUACER_PCI_SEG1_MMIO32_MAX,
       MAX_UINT64 - SYNQUACER_PCI_SEG1_MMIO32_XLATE + 1 },    // Mem
-    { SYNQUACER_PCI_SEG1_MMIO64_MIN,
-      SYNQUACER_PCI_SEG1_MMIO64_MAX },      // MemAbove4G
+    { MAX_UINT64, 0x0 },                    // MemAbove4G
     { MAX_UINT64, 0x0 },                    // PMem
     { MAX_UINT64, 0x0 },                    // PMemAbove4G
     (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1]