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[PULL,v2,01/25] target/openrisc: Fix mtspr shadow gprs

Message ID 20180702151023.24532-2-shorne@gmail.com
State Accepted
Commit c3513c836e4c19cd7a2a7f691995fdef587cec72
Headers show
Series [PULL,v2,01/25] target/openrisc: Fix mtspr shadow gprs | expand

Commit Message

Stafford Horne July 2, 2018, 3:09 p.m. UTC 
From: Richard Henderson <richard.henderson@linaro.org>


Missing break when this feature was added in 89e71e873d
("target/openrisc: implement shadow registers").  This was causing
strange issues as we get writes into the translation block jump cache
and other bits of state.

Fixes: 89e71e873d ("target/openrisc: implement shadow registers")
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Stafford Horne <shorne@gmail.com>

---
 target/openrisc/sys_helper.c | 1 +
 1 file changed, 1 insertion(+)

-- 
2.17.0
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Patch

diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index b284064381..2f337363ec 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -98,6 +98,7 @@  void HELPER(mtspr)(CPUOpenRISCState *env,
     case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
         idx = (spr - 1024);
         env->shadow_gpr[idx / 32][idx % 32] = rb;
+        break;
 
     case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
         idx = spr - TO_SPR(1, 512);