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[PULL,v2,09/25] target/openrisc: Exit the TB after l.mtspr

Message ID 20180702151023.24532-10-shorne@gmail.com
State Accepted
Commit 01ec3ec930c90374a8870e99e0da63c17d708d47
Headers show
Series [PULL,v2,01/25] target/openrisc: Fix mtspr shadow gprs | expand

Commit Message

Stafford Horne July 2, 2018, 3:10 p.m. UTC 
From: Richard Henderson <richard.henderson@linaro.org>


A store to SR changes interrupt state, which should return
to the main loop to recognize that state.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Stafford Horne <shorne@gmail.com>

---
 target/openrisc/translate.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

-- 
2.17.0
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Patch

diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index db149986af..59605aacca 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -877,7 +877,22 @@  static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn)
     if (is_user(dc)) {
         gen_illegal_exception(dc);
     } else {
-        TCGv_i32 ti = tcg_const_i32(a->k);
+        TCGv_i32 ti;
+
+        /* For SR, we will need to exit the TB to recognize the new
+         * exception state.  For NPC, in theory this counts as a branch
+         * (although the SPR only exists for use by an ICE).  Save all
+         * of the cpu state first, allowing it to be overwritten.
+         */
+        if (dc->delayed_branch) {
+            tcg_gen_mov_tl(cpu_pc, jmp_pc);
+            tcg_gen_discard_tl(jmp_pc);
+        } else {
+            tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4);
+        }
+        dc->base.is_jmp = DISAS_EXIT;
+
+        ti = tcg_const_i32(a->k);
         gen_helper_mtspr(cpu_env, cpu_R[a->a], cpu_R[a->b], ti);
         tcg_temp_free_i32(ti);
     }