[edk2,edk2-platforms,v2,3/6] Hisilicon/D0x: Fix SetAtuConfig1RW bug

Message ID 20180704075117.7427-4-ming.huang@linaro.org
State Superseded
Headers show
Series
  • Improve D0x platforms and bug fix
Related show

Commit Message

Ming July 4, 2018, 7:51 a.m.
The MemLimit is wrong when the Private->BusLimit equal 0xFF.
This patch fix enumerating device plug in switch cart failed issue.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>

Signed-off-by: Heyi Guo <heyi.guo@linaro.org>

---
 Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
2.17.0

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Patch

diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
index e5f66eaa4a..3f894e8eec 100644
--- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -666,7 +666,7 @@  void SetAtuConfig1RW (
     )
 {
     UINTN RbPciBase = Private->RbPciBar;
-    UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1;
+    UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit, 0x1F, 0x07, 0xFFF);
     UINT64 Cfg1Base = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 2, 0, 0, 0);
 
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);