[1/3,v4] ARM: dts: Modernize the Vexpress PL111 integration

Message ID 20180709075232.30678-1-linus.walleij@linaro.org
State Superseded
Headers show
Series
  • [1/3,v4] ARM: dts: Modernize the Vexpress PL111 integration
Related show

Commit Message

Linus Walleij July 9, 2018, 7:52 a.m.
The Versatile Express was submitted with the actual display
bridges unconnected (but defined in the device tree) and
mock "panels" encoded in the device tree node of the PL111
controller.

This doesn't even remotely describe the actual Versatile
Express hardware. Exploit the SiI9022 bridge by connecting
the PL111 pads to it, making it use EDID or fallback values
to drive the monitor.

The  also has to use the reserved memory through the
CMA pool rather than by open coding a memory region and
remapping it explicitly in the driver. To achieve this,
a reserved-memory node must exist in the root of the
device tree, so we need to pull that out of the
motherboard .dtsi include files, and push it into each
top-level device tree instead.

We do the same manouver for all the Versatile Express
boards, taking into account the different location of the
video RAM depending on which chip select is used on
each platform.

This plays nicely with the new PL111 DRM driver and
follows the standard ways of assigning bridges and
memory pools for graphics.

Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Mali DP Maintainers <malidp@foss.arm.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v3->v4:
- Fix the ARM and ARM64 shared vexpress-v2m-rc1.dtsi
  file address-cells etc so that the ports do not give
  DTC warnings anymore.
- Fixed up the CA53 DTS: use the right chip select base
  at 0x18000000.
- Fixed up the Real-Time Systems Models Virtual Executive
  RTSMv8 AEM VE:
  - Added the I2C interface (whether implemented in the
    emulator or not)
  - Fixed the chip select of the memory node to the right
    memory base 0x18000000.
- Add right address-cells and size-cells to the
  vexpress-v2m.dtsi dvi port as well.
- Create two endpoints for the motherboard and the
  core tile in the vexpress-v2m.dtsi. This is just used
  by the CA9 VExpress. Tested on both QEMU and the
  actual hardware with the DRM driver. This removes the
  last warnings from the DTC.
ChangeLog v2->v3:
- Add some reg = <0>; to the ports to make the DTC happy.
- Add reserved memory node to
  arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
  as well.
ChangeLog v1->v2:
- Fix up the memory address for the -rs1 tiles to 0x18000000
- Drop a bunch of extraneous reg props from the DVI adapter
---
 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi       | 49 +++++----------
 arch/arm/boot/dts/vexpress-v2m.dtsi           | 63 +++++++++----------
 arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts   | 14 +++++
 arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts    | 14 +++++
 arch/arm/boot/dts/vexpress-v2p-ca5s.dts       | 14 +++++
 arch/arm/boot/dts/vexpress-v2p-ca9.dts        | 43 ++++++-------
 arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts    | 14 +++++
 .../boot/dts/arm/rtsm_ve-motherboard.dtsi     | 62 +++++++++---------
 .../boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 14 +++++
 9 files changed, 166 insertions(+), 121 deletions(-)

Comments

Sudeep Holla July 10, 2018, 9:46 a.m. | #1
On 09/07/18 08:52, Linus Walleij wrote:
> The Versatile Express was submitted with the actual display
> bridges unconnected (but defined in the device tree) and
> mock "panels" encoded in the device tree node of the PL111
> controller.
> 
> This doesn't even remotely describe the actual Versatile
> Express hardware. Exploit the SiI9022 bridge by connecting
> the PL111 pads to it, making it use EDID or fallback values
> to drive the monitor.
> 
> The  also has to use the reserved memory through the
> CMA pool rather than by open coding a memory region and
> remapping it explicitly in the driver. To achieve this,
> a reserved-memory node must exist in the root of the
> device tree, so we need to pull that out of the
> motherboard .dtsi include files, and push it into each
> top-level device tree instead.
> 
> We do the same manouver for all the Versatile Express
> boards, taking into account the different location of the
> video RAM depending on which chip select is used on
> each platform.
> 
> This plays nicely with the new PL111 DRM driver and
> follows the standard ways of assigning bridges and
> memory pools for graphics.
> 
> Cc: Sudeep Holla <sudeep.holla@arm.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Liviu Dudau <liviu.dudau@arm.com>
> Cc: Mali DP Maintainers <malidp@foss.arm.com>
> Cc: Robin Murphy <robin.murphy@arm.com>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> ChangeLog v3->v4:
> - Fix the ARM and ARM64 shared vexpress-v2m-rc1.dtsi
>   file address-cells etc so that the ports do not give
>   DTC warnings anymore.

Still get below warnings, not sure if I need to upgrade my DTC ?

vexpress-v2f-1xv7-ca53x2.dtb: Warning (graph_child_address):
/smb@8000000/motherboard/iofpga@3,00000000/i2c@160000/dvi-transmitter@39/ports:
graph node has single child node 'port@0', #address-cells/#size-cells
are not necessary
rtsm_ve-aemv8a.dtb: Warning (graph_child_address):
/smb@8000000/motherboard/iofpga@3,00000000/i2c@160000/dvi-transmitter@39/ports:
graph node has single child node 'port@0', #address-cells/#size-cells
are not necessary

> - Fixed up the CA53 DTS: use the right chip select base
>   at 0x18000000.

I really hate this as it make maintenance difficult, but I don't have
good alternative, so I am fine as it is for now :)

> - Fixed up the Real-Time Systems Models Virtual Executive
>   RTSMv8 AEM VE:
>   - Added the I2C interface (whether implemented in the
>     emulator or not)

It doesn't work. This change is breaking the working CLCD on the models.
I just tested and CLCD driver returns

>   - Fixed the chip select of the memory node to the right
>     memory base 0x18000000.

See, this keeps happening.

Anyways I think you can drop RTSM changes if models don't support I2C
and DVI.

Liviu,

As you deal with DRM drivers and I have no knowledge in that domain,
I want to hear your feedback or Ack/Review ?
Liviu Dudau July 11, 2018, 9:21 a.m. | #2
On Tue, Jul 10, 2018 at 10:46:03AM +0100, Sudeep Holla wrote:
> 
> 
> On 09/07/18 08:52, Linus Walleij wrote:
> > The Versatile Express was submitted with the actual display
> > bridges unconnected (but defined in the device tree) and
> > mock "panels" encoded in the device tree node of the PL111
> > controller.
> > 
> > This doesn't even remotely describe the actual Versatile
> > Express hardware. Exploit the SiI9022 bridge by connecting
> > the PL111 pads to it, making it use EDID or fallback values
> > to drive the monitor.
> > 
> > The  also has to use the reserved memory through the
> > CMA pool rather than by open coding a memory region and
> > remapping it explicitly in the driver. To achieve this,
> > a reserved-memory node must exist in the root of the
> > device tree, so we need to pull that out of the
> > motherboard .dtsi include files, and push it into each
> > top-level device tree instead.
> > 
> > We do the same manouver for all the Versatile Express
> > boards, taking into account the different location of the
> > video RAM depending on which chip select is used on
> > each platform.
> > 
> > This plays nicely with the new PL111 DRM driver and
> > follows the standard ways of assigning bridges and
> > memory pools for graphics.
> > 
> > Cc: Sudeep Holla <sudeep.holla@arm.com>
> > Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > Cc: Liviu Dudau <liviu.dudau@arm.com>
> > Cc: Mali DP Maintainers <malidp@foss.arm.com>
> > Cc: Robin Murphy <robin.murphy@arm.com>
> > Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> > ---
> > ChangeLog v3->v4:
> > - Fix the ARM and ARM64 shared vexpress-v2m-rc1.dtsi
> >   file address-cells etc so that the ports do not give
> >   DTC warnings anymore.
> 
> Still get below warnings, not sure if I need to upgrade my DTC ?
> 
> vexpress-v2f-1xv7-ca53x2.dtb: Warning (graph_child_address):
> /smb@8000000/motherboard/iofpga@3,00000000/i2c@160000/dvi-transmitter@39/ports:
> graph node has single child node 'port@0', #address-cells/#size-cells
> are not necessary
> rtsm_ve-aemv8a.dtb: Warning (graph_child_address):
> /smb@8000000/motherboard/iofpga@3,00000000/i2c@160000/dvi-transmitter@39/ports:
> graph node has single child node 'port@0', #address-cells/#size-cells
> are not necessary
> 
> > - Fixed up the CA53 DTS: use the right chip select base
> >   at 0x18000000.
> 
> I really hate this as it make maintenance difficult, but I don't have
> good alternative, so I am fine as it is for now :)
> 
> > - Fixed up the Real-Time Systems Models Virtual Executive
> >   RTSMv8 AEM VE:
> >   - Added the I2C interface (whether implemented in the
> >     emulator or not)
> 
> It doesn't work. This change is breaking the working CLCD on the models.
> I just tested and CLCD driver returns
> 
> >   - Fixed the chip select of the memory node to the right
> >     memory base 0x18000000.
> 
> See, this keeps happening.
> 
> Anyways I think you can drop RTSM changes if models don't support I2C
> and DVI.
> 
> Liviu,

Hi Sudeep,

> 
> As you deal with DRM drivers and I have no knowledge in that domain,
> I want to hear your feedback or Ack/Review ?

I was testing last week the previous version of the patchset but run
into the issue with my toolchain having the new binutils that generates
invalid code for THUMB2 kernels, so it took me a while to find that one
out.

For a VExpress that has a TC2 CoreTile, the HDLCD driver fails to load
because the DT doesn't have the right "port" node, which is something I
need to fix, but then we need to make sure we can switch outputs to the
CoreTile and that is where I got to until now, due to some other
commitments.

Otherwise, provided Linus has a fix for the issues you've raised, I have
nothing against these patches being merged, so if you need them:

Acked-by: Liviu Dudau <liviu.dudau@arm.com>

Best regards,
Liviu

> 
> -- 
> -- 
> Regards,
> Sudeep
Sudeep Holla July 13, 2018, 9:50 a.m. | #3
On 10/07/18 10:46, Sudeep Holla wrote:
>  
> On 09/07/18 08:52, Linus Walleij wrote:

[...]

> 
> Still get below warnings, not sure if I need to upgrade my DTC ?
> 
> vexpress-v2f-1xv7-ca53x2.dtb: Warning (graph_child_address):
> /smb@8000000/motherboard/iofpga@3,00000000/i2c@160000/dvi-transmitter@39/ports:
> graph node has single child node 'port@0', #address-cells/#size-cells
> are not necessary
> rtsm_ve-aemv8a.dtb: Warning (graph_child_address):
> /smb@8000000/motherboard/iofpga@3,00000000/i2c@160000/dvi-transmitter@39/ports:
> graph node has single child node 'port@0', #address-cells/#size-cells
> are not necessary
> 

Ignore this as it's hard to fix. If you fix this you will get 10 other
warnings elsewhere, not sure why.

[...]

>> - Fixed up the Real-Time Systems Models Virtual Executive
>>   RTSMv8 AEM VE:
>>   - Added the I2C interface (whether implemented in the
>>     emulator or not)
> 
> It doesn't work. This change is breaking the working CLCD on the models.
> I just tested and CLCD driver returns
> 

It even fails to initialize CLCD on my TC2.

clcd-pl11x 1c1f0000.clcd: PL111 designer 41 rev1 at 0x1c1f0000
clcd-pl11x: probe of 1c1f0000.clcd failed with error -2
Robin Murphy July 13, 2018, 11:44 a.m. | #4
On 13/07/18 10:50, Sudeep Holla wrote:
>> It doesn't work. This change is breaking the working CLCD on the models.
>> I just tested and CLCD driver returns
>>
> 
> It even fails to initialize CLCD on my TC2.
> 
> clcd-pl11x 1c1f0000.clcd: PL111 designer 41 rev1 at 0x1c1f0000
> clcd-pl11x: probe of 1c1f0000.clcd failed with error -2

FWIW the same happens on PB-A8; looks like converting to OF graph 
bindings falls foul of the "panel-dpi" check in clcdfb_of_get_mode().

Robin.
Linus Walleij July 16, 2018, 8:19 a.m. | #5
On Tue, Jul 10, 2018 at 11:46 AM Sudeep Holla <sudeep.holla@arm.com> wrote:
> On 09/07/18 08:52, Linus Walleij wrote:

> Still get below warnings, not sure if I need to upgrade my DTC ?
>
> vexpress-v2f-1xv7-ca53x2.dtb: Warning (graph_child_address):
> /smb@8000000/motherboard/iofpga@3,00000000/i2c@160000/dvi-transmitter@39/ports:
> graph node has single child node 'port@0', #address-cells/#size-cells
> are not necessary
> rtsm_ve-aemv8a.dtb: Warning (graph_child_address):
> /smb@8000000/motherboard/iofpga@3,00000000/i2c@160000/dvi-transmitter@39/ports:
> graph node has single child node 'port@0', #address-cells/#size-cells
> are not necessary

Yeah I looked at it as you said I decided to drop the amendments and I'm
just ever more confused.

> > - Fixed up the CA53 DTS: use the right chip select base
> >   at 0x18000000.
>
> I really hate this as it make maintenance difficult, but I don't have
> good alternative, so I am fine as it is for now :)

Yeah :/

I wish I could fix this but the changes are already daunting and scary
as they are without going in and trying to fix how the CMA DMA
allocator does its job as well (I admit I am scared of that code).

> > - Fixed up the Real-Time Systems Models Virtual Executive
> >   RTSMv8 AEM VE:
> >   - Added the I2C interface (whether implemented in the
> >     emulator or not)
>
> It doesn't work. This change is breaking the working CLCD on the models.
> I just tested and CLCD driver returns

Yeah not surprised... with QEMU I had to go in and add the I2C
bridge as it was not modeled.

I think the solution is to add a "simple" panel without bridge
for this as it is properly modeling what the hardware in the
RTSM looks like. Looking into it.

> >   - Fixed the chip select of the memory node to the right
> >     memory base 0x18000000.
>
> See, this keeps happening.

Yeah, I looked them over again and again, it gets wrong because
I put a human to do a machine's job... The chipselect setting is
in a non-obvious place in one file and the base that corresponds
to in a different file and it gets a bit confused.

I hope I have them all right now.

Yours,
Linus Walleij
Linus Walleij July 16, 2018, 8:25 a.m. | #6
On Fri, Jul 13, 2018 at 1:44 PM Robin Murphy <robin.murphy@arm.com> wrote:
> On 13/07/18 10:50, Sudeep Holla wrote:
> >> It doesn't work. This change is breaking the working CLCD on the models.
> >> I just tested and CLCD driver returns
> >>
> >
> > It even fails to initialize CLCD on my TC2.
> >
> > clcd-pl11x 1c1f0000.clcd: PL111 designer 41 rev1 at 0x1c1f0000
> > clcd-pl11x: probe of 1c1f0000.clcd failed with error -2
>
> FWIW the same happens on PB-A8; looks like converting to OF graph
> bindings falls foul of the "panel-dpi" check in clcdfb_of_get_mode().

That is from the old FB drivers, the defconfig changes in patch 2,3
need to be applied in lockstep with this patch. Then it "should work"
(alas I only tested PB-A8 on QEMU, which I modified to hopefully
properly model the DVI bridge).

Yours,
Linus Walleij

Patch

diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
index 4488c8fe213a..a9569d15de41 100644
--- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -43,11 +43,6 @@ 
 				bank-width = <4>;
 			};
 
-			v2m_video_ram: vram@2,00000000 {
-				compatible = "arm,vexpress-vram";
-				reg = <2 0x00000000 0x00800000>;
-			};
-
 			ethernet@2,02000000 {
 				compatible = "smsc,lan9118", "smsc,lan9115";
 				reg = <2 0x02000000 0x10000>;
@@ -223,13 +218,24 @@ 
 				v2m_i2c_dvi: i2c@160000 {
 					compatible = "arm,versatile-i2c";
 					reg = <0x160000 0x1000>;
-
 					#address-cells = <1>;
 					#size-cells = <0>;
 
 					dvi-transmitter@39 {
 						compatible = "sil,sii9022-tpi", "sil,sii9022";
 						reg = <0x39>;
+
+						ports {
+							#address-cells = <1>;
+							#size-cells = <0>;
+
+							port@0 {
+								reg = <0>;
+								dvi_bridge_in: endpoint {
+									remote-endpoint = <&clcd_pads>;
+								};
+							};
+						};
 					};
 
 					dvi-transmitter@60 {
@@ -260,37 +266,16 @@ 
 					interrupts = <14>;
 					clocks = <&v2m_oscclk1>, <&smbclk>;
 					clock-names = "clcdclk", "apb_pclk";
-					memory-region = <&v2m_video_ram>;
-					max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */
+					/* 800x600 16bpp @36MHz works fine */
+					max-memory-bandwidth = <54000000>;
+					memory-region = <&vram>;
 
 					port {
-						v2m_clcd_pads: endpoint {
-							remote-endpoint = <&v2m_clcd_panel>;
+						clcd_pads: endpoint {
+							remote-endpoint = <&dvi_bridge_in>;
 							arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
 						};
 					};
-
-					panel {
-						compatible = "panel-dpi";
-
-						port {
-							v2m_clcd_panel: endpoint {
-								remote-endpoint = <&v2m_clcd_pads>;
-							};
-						};
-
-						panel-timing {
-							clock-frequency = <25175000>;
-							hactive = <640>;
-							hback-porch = <40>;
-							hfront-porch = <24>;
-							hsync-len = <96>;
-							vactive = <480>;
-							vback-porch = <32>;
-							vfront-porch = <11>;
-							vsync-len = <2>;
-						};
-					};
 				};
 			};
 
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
index 4db42f6326a3..fd42e1194179 100644
--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -43,11 +43,6 @@ 
 				bank-width = <4>;
 			};
 
-			v2m_video_ram: vram@3,00000000 {
-				compatible = "arm,vexpress-vram";
-				reg = <3 0x00000000 0x00800000>;
-			};
-
 			ethernet@3,02000000 {
 				compatible = "smsc,lan9118", "smsc,lan9115";
 				reg = <3 0x02000000 0x10000>;
@@ -223,13 +218,37 @@ 
 				v2m_i2c_dvi: i2c@16000 {
 					compatible = "arm,versatile-i2c";
 					reg = <0x16000 0x1000>;
-
 					#address-cells = <1>;
 					#size-cells = <0>;
 
 					dvi-transmitter@39 {
 						compatible = "sil,sii9022-tpi", "sil,sii9022";
 						reg = <0x39>;
+
+						ports {
+							#address-cells = <1>;
+							#size-cells = <0>;
+
+							/*
+							 * Both the core tile and the motherboard routes their output
+							 * pads to this transmitter. The motherboard system controller
+							 * can select one of them as input using a mux register in
+							 * "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is
+							 * the only platform with this specific set-up.
+							 */
+							port@0 {
+								reg = <0>;
+								dvi_bridge_in_ct: endpoint {
+									remote-endpoint = <&clcd_pads_ct>;
+								};
+							};
+							port@1 {
+								reg = <1>;
+								dvi_bridge_in_mb: endpoint {
+									remote-endpoint = <&clcd_pads_mb>;
+								};
+							};
+						};
 					};
 
 					dvi-transmitter@60 {
@@ -253,6 +272,7 @@ 
 					reg-shift = <2>;
 				};
 
+
 				clcd@1f000 {
 					compatible = "arm,pl111", "arm,primecell";
 					reg = <0x1f000 0x1000>;
@@ -260,37 +280,16 @@ 
 					interrupts = <14>;
 					clocks = <&v2m_oscclk1>, <&smbclk>;
 					clock-names = "clcdclk", "apb_pclk";
-					memory-region = <&v2m_video_ram>;
-					max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */
+					/* 800x600 16bpp @36MHz works fine */
+					max-memory-bandwidth = <54000000>;
+					memory-region = <&vram>;
 
 					port {
-						v2m_clcd_pads: endpoint {
-							remote-endpoint = <&v2m_clcd_panel>;
+						clcd_pads_mb: endpoint {
+							remote-endpoint = <&dvi_bridge_in_mb>;
 							arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
 						};
 					};
-
-					panel {
-						compatible = "panel-dpi";
-
-						port {
-							v2m_clcd_panel: endpoint {
-								remote-endpoint = <&v2m_clcd_pads>;
-							};
-						};
-
-						panel-timing {
-							clock-frequency = <25175000>;
-							hactive = <640>;
-							hback-porch = <40>;
-							hfront-porch = <24>;
-							hsync-len = <96>;
-							vactive = <480>;
-							vback-porch = <32>;
-							vfront-porch = <11>;
-							vsync-len = <2>;
-						};
-					};
 				};
 			};
 
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index 3971427a105b..0dc4277d5f8b 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -53,6 +53,20 @@ 
 		reg = <0 0x80000000 0 0x40000000>;
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* Chipselect 2 is physically at 0x18000000 */
+		vram: vram@18000000 {
+			/* 8 MB of designated video RAM */
+			compatible = "shared-dma-pool";
+			reg = <0 0x18000000 0 0x00800000>;
+			no-map;
+		};
+	};
+
 	hdlcd@2b000000 {
 		compatible = "arm,hdlcd";
 		reg = <0 0x2b000000 0 0x1000>;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index ac6b90e9d806..a5136b1adaa2 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -104,6 +104,20 @@ 
 		reg = <0 0x80000000 0 0x40000000>;
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* Chipselect 2 is physically at 0x18000000 */
+		vram: vram@18000000 {
+			/* 8 MB of designated video RAM */
+			compatible = "shared-dma-pool";
+			reg = <0 0x18000000 0 0x00800000>;
+			no-map;
+		};
+	};
+
 	wdt@2a490000 {
 		compatible = "arm,sp805", "arm,primecell";
 		reg = <0 0x2a490000 0 0x1000>;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
index e5b4a7570a01..d5b47d526f9e 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -55,6 +55,20 @@ 
 		reg = <0x80000000 0x40000000>;
 	};
 
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		/* Chipselect 2 is physically at 0x18000000 */
+		vram: vram@18000000 {
+			/* 8 MB of designated video RAM */
+			compatible = "shared-dma-pool";
+			reg = <0x18000000 0x00800000>;
+			no-map;
+		};
+	};
+
 	hdlcd@2a110000 {
 		compatible = "arm,hdlcd";
 		reg = <0x2a110000 0x1000>;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index 7ec3dac1f61d..7f019e0eee84 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -69,6 +69,20 @@ 
 		reg = <0x60000000 0x40000000>;
 	};
 
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		/* Chipselect 3 is physically at 0x4c000000 */
+		vram: vram@4c000000 {
+			/* 8 MB of designated video RAM */
+			compatible = "shared-dma-pool";
+			reg = <0x4c000000 0x00800000>;
+			no-map;
+		};
+	};
+
 	clcd@10020000 {
 		compatible = "arm,pl111", "arm,primecell";
 		reg = <0x10020000 0x1000>;
@@ -76,36 +90,15 @@ 
 		interrupts = <0 44 4>;
 		clocks = <&oscclk1>, <&oscclk2>;
 		clock-names = "clcdclk", "apb_pclk";
-		max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
+		/* 1024x768 16bpp @65MHz */
+		max-memory-bandwidth = <95000000>;
 
 		port {
-			clcd_pads: endpoint {
-				remote-endpoint = <&clcd_panel>;
+			clcd_pads_ct: endpoint {
+				remote-endpoint = <&dvi_bridge_in_ct>;
 				arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
 			};
 		};
-
-		panel {
-			compatible = "panel-dpi";
-
-			port {
-				clcd_panel: endpoint {
-					remote-endpoint = <&clcd_pads>;
-				};
-			};
-
-			panel-timing {
-				clock-frequency = <63500127>;
-				hactive = <1024>;
-				hback-porch = <152>;
-				hfront-porch = <48>;
-				hsync-len = <104>;
-				vactive = <768>;
-				vback-porch = <23>;
-				vfront-porch = <3>;
-				vsync-len = <4>;
-			};
-		};
 	};
 
 	memory-controller@100e0000 {
diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
index 602f63f72c37..97d961461143 100644
--- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
+++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
@@ -78,6 +78,20 @@ 
 		      <0x00000008 0x80000000 0 0x80000000>;
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* Chipselect 2,00000000 is physically at 0x18000000 */
+		vram: vram@18000000 {
+			/* 8 MB of designated video RAM */
+			compatible = "shared-dma-pool";
+			reg = <0x00000000 0x18000000 0 0x00800000>;
+			no-map;
+		};
+	};
+
 	gic: interrupt-controller@2c001000 {
 		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
 		#interrupt-cells = <3>;
diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
index d2dbc3f39263..fd173f9308f5 100644
--- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
+++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
@@ -24,11 +24,6 @@ 
 				bank-width = <4>;
 			};
 
-			v2m_video_ram: vram@2,00000000 {
-				compatible = "arm,vexpress-vram";
-				reg = <2 0x00000000 0x00800000>;
-			};
-
 			ethernet@2,02000000 {
 				compatible = "smsc,lan91c111";
 				reg = <2 0x02000000 0x10000>;
@@ -172,6 +167,31 @@ 
 					clock-names = "timclken1", "timclken2", "apb_pclk";
 				};
 
+				/* DVI I2C bus */
+				v2m_i2c_dvi: i2c@160000 {
+					compatible = "arm,versatile-i2c";
+					reg = <0x160000 0x1000>;
+
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					dvi-transmitter@39 {
+						compatible = "sil,sii9022-tpi", "sil,sii9022";
+						reg = <0x39>;
+
+						ports {
+							#address-cells = <1>;
+							#size-cells = <0>;
+							port@0 {
+								reg = <0>;
+								dvi_bridge_in: endpoint {
+									remote-endpoint = <&clcd_pads>;
+								};
+							};
+						};
+					};
+				};
+
 				rtc@170000 {
 					compatible = "arm,pl031", "arm,primecell";
 					reg = <0x170000 0x1000>;
@@ -187,38 +207,16 @@ 
 					interrupts = <14>;
 					clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
 					clock-names = "clcdclk", "apb_pclk";
-					arm,pl11x,framebuffer = <0x18000000 0x00180000>;
-					memory-region = <&v2m_video_ram>;
-					max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
+					/* 800x600 16bpp @36MHz works fine */
+					max-memory-bandwidth = <54000000>;
+					memory-region = <&vram>;
 
 					port {
-						v2m_clcd_pads: endpoint {
-							remote-endpoint = <&v2m_clcd_panel>;
+						clcd_pads: endpoint {
+							remote-endpoint = <&dvi_bridge_in>;
 							arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
 						};
 					};
-
-					panel {
-						compatible = "panel-dpi";
-
-						port {
-							v2m_clcd_panel: endpoint {
-								remote-endpoint = <&v2m_clcd_pads>;
-							};
-						};
-
-						panel-timing {
-							clock-frequency = <63500127>;
-							hactive = <1024>;
-							hback-porch = <152>;
-							hfront-porch = <48>;
-							hsync-len = <104>;
-							vactive = <768>;
-							vback-porch = <23>;
-							vfront-porch = <3>;
-							vsync-len = <4>;
-						};
-					};
 				};
 
 				virtio-block@130000 {
diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
index 38880380e0fa..8981c3d2ff18 100644
--- a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
+++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
@@ -65,6 +65,20 @@ 
 		reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* Chipselect 2 is physically at 0x18000000 */
+		vram: vram@18000000 {
+			/* 8 MB of designated video RAM */
+			compatible = "shared-dma-pool";
+			reg = <0 0x18000000 0 0x00800000>;
+			no-map;
+		};
+	};
+
 	gic: interrupt-controller@2c001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;