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[203.254.224.24]) by mx.google.com with ESMTP id zs6si13466777pbc.1.2013.01.21.03.29.48; Mon, 21 Jan 2013 03:29:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of amarendra.xt@samsung.com designates 203.254.224.24 as permitted sender) client-ip=203.254.224.24; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of amarendra.xt@samsung.com designates 203.254.224.24 as permitted sender) smtp.mail=amarendra.xt@samsung.com Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MGZ00BJZ3W6RDP0@mailout1.samsung.com>; Mon, 21 Jan 2013 20:29:43 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.122]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 21.04.03918.7A62DF05; Mon, 21 Jan 2013 20:29:43 +0900 (KST) X-AuditID: cbfee61a-b7f7d6d000000f4e-44-50fd26a755ef Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 70.04.03918.6A62DF05; Mon, 21 Jan 2013 20:29:43 +0900 (KST) Received: from chrome-ubuntu.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MGZ0092C3L1A540@mmp2.samsung.com>; Mon, 21 Jan 2013 20:29:42 +0900 (KST) From: Amar To: u-boot@lists.denx.de, jh80.chung@samsung.com Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, afleming@gmail.com, hs@denx.de Subject: [PATCH V5 08/10] SMDK5250: Enable EMMC booting Date: Mon, 21 Jan 2013 06:43:56 -0500 Message-id: <1358768638-14187-9-git-send-email-amarendra.xt@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1358768638-14187-1-git-send-email-amarendra.xt@samsung.com> References: <1358768638-14187-1-git-send-email-amarendra.xt@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrGLMWRmVeSWpSXmKPExsWyRsSkSne52t8Agxs3xS0err/JYjHl8BcW ByaPO9f2sAUwRnHZpKTmZJalFunbJXBlrDh6krHgrVbF5AUvmBsY5yt3MXJySAiYSEx838IE YYtJXLi3ng3EFhJYyihxvD0RpmbTnVMsXYxcQPHpjBIfu88xQzi9TBJ9tx8BZTg42ARUJX4t tgdpEBEwkJj+ZDsriM0sUCMxef4tsAXCAuYSe9cfYQSxWYDK5/9+CNbKK+AhMftRKMQuOYkP ex6xg9icAp4S+//uYYW4x0Ni14L/rCBrJQRus0m8m7iXHWKOgMS3yYfA5kgIyEpsOsAMMUdS 4uCKGywTGIUXMDKsYhRNLUguKE5KzzXUK07MLS7NS9dLzs/dxAgMxdP/nkntYFzZYHGIUYCD UYmHN2PqnwAh1sSy4srcQ4wSHMxKIrw/ZwCFeFMSK6tSi/Lji0pzUosPMSYDLZ/ILCWanA+M k7ySeENjE3NTY1NLIyMzU1PShJXEeRlPPQkQEkhPLEnNTk0tSC2C2cLEwSnVwLiU2VyKZeOS 8/dXLHZoZZeq9LuT9EygPu/3tif+S1kXSh4ydf4i/u6DXMqvD9vXz62++sV9WeGXrqPTlzhv tb0YFqM/pePA6cJJd23+3361RM23sndJh9id7ZFBgc2Ky7Jjq74K/eKUuTupwDLHs/LajG0v +T+rO/JuvenA+33tmwKDrOvMJ7yVWIozEg21mIuKEwGXsfXpiQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrGIsWRmVeSWpSXmKPExsVy+t9jQd3lan8DDFYfYbR4uP4mi8WUw19Y HJg87lzbwxbAGNXAaJORmpiSWqSQmpecn5KZl26r5B0c7xxvamZgqGtoaWGupJCXmJtqq+Ti E6DrlpkDNFtJoSwxpxQoFJBYXKykb4dpQmiIm64FTGOErm9IEFyPkQEaSFjDmLHi6EnGgrda FZMXvGBuYJyv3MXIySEhYCKx6c4pFghbTOLCvfVsXYxcHEIC0xklPnafY4Zwepkk+m4/Aqri 4GATUJX4tdgepEFEwEBi+pPtrCA2s0CNxOT5t5hAbGEBc4m9648wgtgsQOXzfz8Ea+UV8JCY /SgUYpecxIc9j9hBbE4BT4n9f/eAjRECKtm14D/rBEbeBYwMqxhFUwuSC4qT0nMN9YoTc4tL 89L1kvNzNzGCQ/2Z1A7GlQ0WhxgFOBiVeHgzpv4JEGJNLCuuzD3EKMHBrCTC+3MGUIg3JbGy KrUoP76oNCe1+BBjMtBRE5mlRJPzgXGYVxJvaGxibmpsamliYWJmSZqwkjgv46knAUIC6Ykl qdmpqQWpRTBbmDg4pRoYhS8pNXOaSC13O3humWzjlZen3KLtwstata9unjJPLLL+Xsa1d2ne Dh6n0zfXvPr9LVX7vtDZgsbo08w/DeOWFsn0cW9Z15sg3xYxJ+pw4LZ5eU/TGuw/mCvdXtKu v8e45GDT6m891cXs3m3Sm8Kj3n1bcujUt27JG8sznygWfOldvZknOnODEktxRqKhFnNRcSIA 4wQQv7kCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQlV8vBKex0IqABVSEbpiE5w2A1ZUdkgVZGm8k4+HaQ9rvfLILjSK3uZx1QeI4XEahCOtHLb This patch adds support for EMMC booting on SMDK5250. Signed-off-by: Amar Acked-by: Simon Glass --- Changes since V1: 1)Updated spl_boot.c file to maintain irom pointer table instead of using the #define values defined in header file. Changes since V2: 1)Updation of commit message and resubmition of proper patch set. Changes since V3: No change. Changes since V4: 1)The function get_irom_func(int index) has been added to avoid type casting at many places. 2)The changes to file arch/arm/include/asm/arch-exynos/clk.h are included in this patch file. arch/arm/include/asm/arch-exynos/clk.h | 3 ++ board/samsung/smdk5250/clock_init.c | 15 ++++++++++ board/samsung/smdk5250/clock_init.h | 5 ++++ board/samsung/smdk5250/spl_boot.c | 52 ++++++++++++++++++++++++++++++---- 4 files changed, 69 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 1935b0b..a4d5b4e 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -29,6 +29,9 @@ #define VPLL 4 #define BPLL 5 +#define FSYS1_MMC0_DIV_MASK 0xff0f +#define FSYS1_MMC0_DIV_VAL 0x0701 + unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); unsigned long get_i2c_clk(void); diff --git a/board/samsung/smdk5250/clock_init.c b/board/samsung/smdk5250/clock_init.c index c009ae5..154993c 100644 --- a/board/samsung/smdk5250/clock_init.c +++ b/board/samsung/smdk5250/clock_init.c @@ -28,6 +28,7 @@ #include #include #include +#include #include "clock_init.h" #include "setup.h" @@ -664,3 +665,17 @@ void clock_init_dp_clock(void) /* We run DP at 267 Mhz */ setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); } + +/* + * Set clock divisor value for booting from EMMC. + * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz. + */ +void emmc_boot_clk_div_set(void) +{ + struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; + unsigned int div_mmc; + + div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK; + div_mmc |= FSYS1_MMC0_DIV_VAL; + writel(div_mmc, (unsigned int) &clk->div_fsys1); +} diff --git a/board/samsung/smdk5250/clock_init.h b/board/samsung/smdk5250/clock_init.h index f751bcb..20a1d47 100644 --- a/board/samsung/smdk5250/clock_init.h +++ b/board/samsung/smdk5250/clock_init.h @@ -146,4 +146,9 @@ struct mem_timings *clock_get_mem_timings(void); * Initialize clock for the device */ void system_clock_init(void); + +/* + * Set clock divisor value for booting from EMMC. + */ +void emmc_boot_clk_div_set(void); #endif diff --git a/board/samsung/smdk5250/spl_boot.c b/board/samsung/smdk5250/spl_boot.c index d8f3c1e..4ddbd4a 100644 --- a/board/samsung/smdk5250/spl_boot.c +++ b/board/samsung/smdk5250/spl_boot.c @@ -23,15 +23,42 @@ #include #include +#include +#include +#include + +#include "clock_init.h" + +/* Index into irom ptr table */ +enum index { + MMC_INDEX, + EMMC44_INDEX, + EMMC44_END_INDEX, + SPI_INDEX, +}; + +/* IROM Function Pointers Table */ +u32 irom_ptr_table[] = { + [MMC_INDEX] = 0x02020030, /* iROM Function Pointer-SDMMC boot */ + [EMMC44_INDEX] = 0x02020044, /* iROM Function Pointer-EMMC4.4 boot*/ + [EMMC44_END_INDEX] = 0x02020048,/* iROM Function Pointer + -EMMC4.4 end boot operation */ + [SPI_INDEX] = 0x02020058, /* iROM Function Pointer-SPI boot */ + }; + enum boot_mode { BOOT_MODE_MMC = 4, BOOT_MODE_SERIAL = 20, + BOOT_MODE_EMMC = 8, /* EMMC4.4 */ /* Boot based on Operating Mode pin settings */ BOOT_MODE_OM = 32, BOOT_MODE_USB, /* Boot using USB download */ }; - typedef u32 (*spi_copy_func_t)(u32 offset, u32 nblock, u32 dst); +void *get_irom_func(int index) +{ + return (void *) *(u32 *)irom_ptr_table[index]; +} /* * Copy U-boot from mmc to RAM: @@ -40,23 +67,36 @@ enum boot_mode { */ void copy_uboot_to_ram(void) { - spi_copy_func_t spi_copy; enum boot_mode bootmode; - u32 (*copy_bl2)(u32, u32, u32); - + u32 (*spi_copy)(u32 offset, u32 nblock, u32 dst); + u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst); + u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst); + void (*end_bootop_from_emmc)(void); + /* read Operation Mode ststus register to find the bootmode */ bootmode = readl(EXYNOS5_POWER_BASE) & OM_STAT; switch (bootmode) { case BOOT_MODE_SERIAL: - spi_copy = *(spi_copy_func_t *)EXYNOS_COPY_SPI_FNPTR_ADDR; + spi_copy = get_irom_func(SPI_INDEX); spi_copy(SPI_FLASH_UBOOT_POS, CONFIG_BL2_SIZE, CONFIG_SYS_TEXT_BASE); break; case BOOT_MODE_MMC: - copy_bl2 = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR; + copy_bl2 = get_irom_func(MMC_INDEX); copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); break; + case BOOT_MODE_EMMC: + /* Set the FSYS1 clock divisor value for EMMC boot */ + emmc_boot_clk_div_set(); + + copy_bl2_from_emmc = get_irom_func(EMMC44_INDEX); + end_bootop_from_emmc = get_irom_func(EMMC44_END_INDEX); + + copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); + end_bootop_from_emmc(); + break; + default: break; }