From patchwork Mon Jul 9 06:19:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 141542 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp2284701ljj; Sun, 8 Jul 2018 23:20:30 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfZ+O1qqkeFEolxc8TemLqFRh2crth1Ku74tc6I8ueAYFsjQYdmrOpAG0InHxaqu17YNuiR X-Received: by 2002:a17:902:7892:: with SMTP id q18-v6mr19609221pll.331.1531117230643; Sun, 08 Jul 2018 23:20:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531117230; cv=none; d=google.com; s=arc-20160816; b=sDA/iNiY4Zl0mmOCdJMg2LNrsKKH6Y9kz5m6mgHgJ7JjujKJYyU9/WZQGK3bzH6Q3c yrvwqzG6KLmmhDW51iHi0T0GQivO6BCdj54GNOBZniEmpALGW4Fjqy2dVK/BTOjTjeGy tvdKsbPn7dP4NHrN6lOp6MUQcTn9HNaWXMT5WZWWMfgejd7IXdVe8wAmHBs0oJiAHntD yUrob9mly5+3F2/49jc11zkzkUU2kvHhnH1i9pCHIp5ObN2hDpqlvZx8yFNQeluYr7Zg 17+PswEJtZBimsy5Uba3xmHgteH1tnfgT1sjOpdwZBSqRKtFyG8LppCemxsgtBrOyyOY sJmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=7PpITgi6fdERLhs4O9mtVr3fIEnVh6BJV8kHzLns5ek=; b=s+XUPq6AkOfQE782qtSbB+woTNFopIDnem9MTG0gg/24Pdix+9I0VWjx41fzOmiga/ kuNTnD+tRn2e3R9BihrhDgAdsywJEalLcSrtctGCwmz3FZkkSe3LV/M8zSp9knxzzEif KS/Qm9SC9BJzX2Q5uE99c7LbNXL+pvB+ZxMqU8A8teCvsQf/shEvqSS5omiBx8P2gqtw eTb2LYt3+ZGp1N86QuKLtE7sMVrYcQ5tGuxFteMdNxCdqdVNSjA1VOqoioCSGAvRvKBe JfG8n2WB1cgDuw7b7nhvf8Z4RdB+G23KObiLMhYWhTq1renLTjoa76uACKdZL0KUQb/F 5Y+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@kernel.org header.s=default header.b=BK+PqZFb; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k20-v6si13108647pgb.115.2018.07.08.23.20.30; Sun, 08 Jul 2018 23:20:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@kernel.org header.s=default header.b=BK+PqZFb; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753938AbeGIGU2 (ORCPT + 13 others); Mon, 9 Jul 2018 02:20:28 -0400 Received: from mail.kernel.org ([198.145.29.99]:45422 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754623AbeGIGUS (ORCPT ); Mon, 9 Jul 2018 02:20:18 -0400 Received: from localhost.localdomain (unknown [106.201.46.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 36F61208E3; Mon, 9 Jul 2018 06:20:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1531117214; bh=hbXEjmygzjPBSVObJiIro+7rf/uoG9UZvmd8cbLXrSU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BK+PqZFbyodzPVkkR0zZGoF15ddK9eLbArWfislxTC+zAdubhTcVWSCKepIBSvqTx c2k+MX+RKqnJYrgm7iFuBR4HYU9u0Hv3L4YgKvQJMPRkqR1deo3QlbgSdeZ6MSWTZb z/MhXEWBepvACcuYho9jQiONx2xO9ijG5KotOO0c= From: Vinod Koul To: linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Bjorn Andersson , Matt Mackall , Herbert Xu , Arnd Bergmann , linux-arm-msm@vger.kernel.org, Stephen Boyd , Timur Tabi , Jeffrey Hugo , Vinod Koul Subject: [PATCH v5 3/6] crypto: Add Qcom prng driver Date: Mon, 9 Jul 2018 11:49:22 +0530 Message-Id: <20180709061925.20276-4-vkoul@kernel.org> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180709061925.20276-1-vkoul@kernel.org> References: <20180709061925.20276-1-vkoul@kernel.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This ports the Qcom prng from older hw_random driver. No change of functionality and move from hw_random to crypto APIs is done. Signed-off-by: Vinod Koul --- drivers/crypto/Kconfig | 11 +++ drivers/crypto/Makefile | 1 + drivers/crypto/qcom-rng.c | 208 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 220 insertions(+) create mode 100644 drivers/crypto/qcom-rng.c -- 2.14.4 -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Reviewed-by: Linus Walleij diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 43cccf6aff61..b8d9e71e550a 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -585,6 +585,17 @@ config CRYPTO_DEV_QCE hardware. To compile this driver as a module, choose M here. The module will be called qcrypto. +config CRYPTO_DEV_QCOM_RNG + tristate "Qualcomm Randon Number Generator Driver" + depends on ARCH_QCOM || COMPILE_TEST + select CRYPTO_RNG + help + This driver provides support for the Random Number + Generator hardware found on Qualcomm SoCs. + + To compile this driver as a module, choose M here. the + module will be called qcom-rng. If unsure, say N. + config CRYPTO_DEV_VMX bool "Support for VMX cryptographic acceleration instructions" depends on PPC64 && VSX diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index 7ae87b4f6c8d..3602875c4f80 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_CRYPTO_DEV_PICOXCELL) += picoxcell_crypto.o obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += amcc/ obj-$(CONFIG_CRYPTO_DEV_QAT) += qat/ obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/ +obj-$(CONFIG_CRYPTO_DEV_QCOM_RNG) += qcom-rng.o obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rockchip/ obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o diff --git a/drivers/crypto/qcom-rng.c b/drivers/crypto/qcom-rng.c new file mode 100644 index 000000000000..53e1d276e05e --- /dev/null +++ b/drivers/crypto/qcom-rng.c @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017-18 Linaro Limited +// +// Based on msm-rng.c and downstream driver + +#include +#include +#include +#include +#include +#include + +/* Device specific register offsets */ +#define PRNG_DATA_OUT 0x0000 +#define PRNG_STATUS 0x0004 +#define PRNG_LFSR_CFG 0x0100 +#define PRNG_CONFIG 0x0104 + +/* Device specific register masks and config values */ +#define PRNG_LFSR_CFG_MASK 0x0000ffff +#define PRNG_LFSR_CFG_CLOCKS 0x0000dddd +#define PRNG_CONFIG_HW_ENABLE BIT(1) +#define PRNG_STATUS_DATA_AVAIL BIT(0) + +#define WORD_SZ 4 + +struct qcom_rng { + struct mutex lock; + void __iomem *base; + struct clk *clk; +}; + +struct qcom_rng_ctx { + struct qcom_rng *rng; +}; + +static struct qcom_rng *qcom_rng_dev; + +static int qcom_rng_read(struct qcom_rng *rng, u8 *data, unsigned int max) +{ + unsigned int currsize = 0; + u32 val; + + /* read random data from hardware */ + do { + val = readl_relaxed(rng->base + PRNG_STATUS); + if (!(val & PRNG_STATUS_DATA_AVAIL)) + break; + + val = readl_relaxed(rng->base + PRNG_DATA_OUT); + if (!val) + break; + + if ((max - currsize) >= WORD_SZ) { + memcpy(data, &val, WORD_SZ); + data += WORD_SZ; + currsize += WORD_SZ; + } else { + /* copy only remaining bytes */ + memcpy(data, &val, max - currsize); + break; + } + } while (currsize < max); + + return currsize; +} + +static int qcom_rng_generate(struct crypto_rng *tfm, + const u8 *src, unsigned int slen, + u8 *dstn, unsigned int dlen) +{ + struct qcom_rng_ctx *ctx = crypto_rng_ctx(tfm); + struct qcom_rng *rng = ctx->rng; + int ret; + + ret = clk_prepare_enable(rng->clk); + if (ret) + return ret; + + mutex_lock(&rng->lock); + + ret = qcom_rng_read(rng, dstn, dlen); + + mutex_unlock(&rng->lock); + clk_disable_unprepare(rng->clk); + + return 0; +} + +static int qcom_rng_seed(struct crypto_rng *tfm, const u8 *seed, + unsigned int slen) +{ + return 0; +} + +static int qcom_rng_enable(struct qcom_rng *rng) +{ + u32 val; + int ret; + + ret = clk_prepare_enable(rng->clk); + if (ret) + return ret; + + /* Enable PRNG only if it is not already enabled */ + val = readl_relaxed(rng->base + PRNG_CONFIG); + if (val & PRNG_CONFIG_HW_ENABLE) + goto already_enabled; + + val = readl_relaxed(rng->base + PRNG_LFSR_CFG); + val &= ~PRNG_LFSR_CFG_MASK; + val |= PRNG_LFSR_CFG_CLOCKS; + writel(val, rng->base + PRNG_LFSR_CFG); + + val = readl_relaxed(rng->base + PRNG_CONFIG); + val |= PRNG_CONFIG_HW_ENABLE; + writel(val, rng->base + PRNG_CONFIG); + +already_enabled: + clk_disable_unprepare(rng->clk); + + return 0; +} + +static int qcom_rng_init(struct crypto_tfm *tfm) +{ + struct qcom_rng_ctx *ctx = crypto_tfm_ctx(tfm); + + ctx->rng = qcom_rng_dev; + + return qcom_rng_enable(ctx->rng); +} + +static struct rng_alg qcom_rng_alg = { + .generate = qcom_rng_generate, + .seed = qcom_rng_seed, + .seedsize = 0, + .base = { + .cra_name = "stdrng", + .cra_driver_name = "qcom-rng", + .cra_flags = CRYPTO_ALG_TYPE_RNG, + .cra_priority = 300, + .cra_ctxsize = sizeof(struct qcom_rng_ctx), + .cra_module = THIS_MODULE, + .cra_init = qcom_rng_init, + } +}; + +static int qcom_rng_probe(struct platform_device *pdev) +{ + struct resource *res; + struct qcom_rng *rng; + int ret; + + rng = devm_kzalloc(&pdev->dev, sizeof(*rng), GFP_KERNEL); + if (!rng) + return -ENOMEM; + + platform_set_drvdata(pdev, rng); + mutex_init(&rng->lock); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + rng->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(rng->base)) + return PTR_ERR(rng->base); + + rng->clk = devm_clk_get(&pdev->dev, "core"); + if (IS_ERR(rng->clk)) + return PTR_ERR(rng->clk); + + qcom_rng_dev = rng; + ret = crypto_register_rng(&qcom_rng_alg); + if (ret) { + dev_err(&pdev->dev, "Register crypto rng failed: %d\n", ret); + qcom_rng_dev = NULL; + } + + return ret; +} + +static int qcom_rng_remove(struct platform_device *pdev) +{ + crypto_unregister_rng(&qcom_rng_alg); + + qcom_rng_dev = NULL; + + return 0; +} + +static const struct of_device_id qcom_rng_of_match[] = { + { .compatible = "qcom,prng" }, + {} +}; +MODULE_DEVICE_TABLE(of, qcom_rng_of_match); + +static struct platform_driver qcom_rng_driver = { + .probe = qcom_rng_probe, + .remove = qcom_rng_remove, + .driver = { + .name = KBUILD_MODNAME, + .of_match_table = of_match_ptr(qcom_rng_of_match), + } +}; +module_platform_driver(qcom_rng_driver); + +MODULE_ALIAS("platform:" KBUILD_MODNAME); +MODULE_DESCRIPTION("Qualcomm random number generator driver"); +MODULE_LICENSE("GPL v2");