| Message ID | 1531962803-25477-1-git-send-email-yamada.masahiro@socionext.com |
|---|---|
| State | Accepted |
| Commit | 4a610fada193057c97c1b23016ef119f98459b22 |
| Headers | show |
| Series | mtd: nand: denali: correct buffer alignment for DMA transfer | expand |
2018-07-19 10:13 GMT+09:00 Masahiro Yamada <yamada.masahiro@socionext.com>: > The NAND framework makes sure to pass in the buffer with at least > chip->buf_align alignment. Currently, the Denali NAND driver only > requests 16 byte alignment. This causes unaligned cache operations > for the DMA transfer. > > [Error Example] > > => nand read 81000010 0 1000 > > NAND read: device 0 offset 0x0, size 0x1000 > CACHE: Misaligned operation at range [81000010, 81001010] > CACHE: Misaligned operation at range [81000010, 81001010] > CACHE: Misaligned operation at range [81000010, 81001010] > CACHE: Misaligned operation at range [81000010, 81001010] > 4096 bytes read: OK > > Reported-by: Marek Vasut <marex@denx.de> > Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> > --- Applied to u-boot-uniphier. > drivers/mtd/nand/denali.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c > index 6266c8a..7302c37 100644 > --- a/drivers/mtd/nand/denali.c > +++ b/drivers/mtd/nand/denali.c > @@ -1270,7 +1270,7 @@ int denali_init(struct denali_nand_info *denali) > denali->dma_avail = 1; > > if (denali->dma_avail) { > - chip->buf_align = 16; > + chip->buf_align = ARCH_DMA_MINALIGN; > if (denali->caps & DENALI_CAP_DMA_64BIT) > denali->setup_dma = denali_setup_dma64; > else > -- > 2.7.4 > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 6266c8a..7302c37 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -1270,7 +1270,7 @@ int denali_init(struct denali_nand_info *denali) denali->dma_avail = 1; if (denali->dma_avail) { - chip->buf_align = 16; + chip->buf_align = ARCH_DMA_MINALIGN; if (denali->caps & DENALI_CAP_DMA_64BIT) denali->setup_dma = denali_setup_dma64; else
The NAND framework makes sure to pass in the buffer with at least chip->buf_align alignment. Currently, the Denali NAND driver only requests 16 byte alignment. This causes unaligned cache operations for the DMA transfer. [Error Example] => nand read 81000010 0 1000 NAND read: device 0 offset 0x0, size 0x1000 CACHE: Misaligned operation at range [81000010, 81001010] CACHE: Misaligned operation at range [81000010, 81001010] CACHE: Misaligned operation at range [81000010, 81001010] CACHE: Misaligned operation at range [81000010, 81001010] 4096 bytes read: OK Reported-by: Marek Vasut <marex@denx.de> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> --- drivers/mtd/nand/denali.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)