Message ID | 20180803101943.23722-1-peter.maydell@linaro.org |
---|---|
State | Superseded |
Headers | show |
Series | hw/intc/apic: Switch away from old_mmio | expand |
On 08/03/2018 07:19 AM, Peter Maydell wrote: > Switch the apic away from using the old_mmio MemoryRegionOps > accessor functions. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > I think this is the last old_mmio user. We can clean up the > core code once all the on-list patches get into master. > --- > hw/intc/apic.c | 42 ++++++++++++++++++------------------------ > 1 file changed, 18 insertions(+), 24 deletions(-) > > diff --git a/hw/intc/apic.c b/hw/intc/apic.c > index 6fda52b86cf..97ffdd820f2 100644 > --- a/hw/intc/apic.c > +++ b/hw/intc/apic.c > @@ -650,31 +650,17 @@ static void apic_timer(void *opaque) > apic_timer_update(s, s->next_time); > } > > -static uint32_t apic_mem_readb(void *opaque, hwaddr addr) > -{ > - return 0; > -} > - > -static uint32_t apic_mem_readw(void *opaque, hwaddr addr) > -{ > - return 0; > -} > - > -static void apic_mem_writeb(void *opaque, hwaddr addr, uint32_t val) > -{ > -} > - > -static void apic_mem_writew(void *opaque, hwaddr addr, uint32_t val) > -{ > -} > - > -static uint32_t apic_mem_readl(void *opaque, hwaddr addr) > +static uint64_t apic_mem_read(void *opaque, hwaddr addr, unsigned size) > { > DeviceState *dev; > APICCommonState *s; > uint32_t val; > int index; > > + if (size < 4) { > + return 0; > + } > + > dev = cpu_get_current_apic(); > if (!dev) { > return 0; > @@ -765,11 +751,17 @@ static void apic_send_msi(MSIMessage *msi) > apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); > } > > -static void apic_mem_writel(void *opaque, hwaddr addr, uint32_t val) > +static void apic_mem_write(void *opaque, hwaddr addr, uint64_t val, > + unsigned size) > { > DeviceState *dev; > APICCommonState *s; > int index = (addr >> 4) & 0xff; > + > + if (size < 4) { > + return; > + } > + > if (addr > 0xfff || !index) { > /* MSI and MMIO APIC are at the same memory location, > * but actually not on the global bus: MSI is on PCI bus > @@ -880,10 +872,12 @@ static void apic_post_load(APICCommonState *s) > } > > static const MemoryRegionOps apic_io_ops = { > - .old_mmio = { > - .read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, }, > - .write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, }, > - }, > + .read = apic_mem_read, > + .write = apic_mem_write, > + .impl.min_access_size = 1, > + .impl.max_access_size = 4, > + .valid.min_access_size = 1, > + .valid.max_access_size = 4, > .endianness = DEVICE_NATIVE_ENDIAN, > }; > >
On 3 August 2018 at 11:19, Peter Maydell <peter.maydell@linaro.org> wrote: > Switch the apic away from using the old_mmio MemoryRegionOps > accessor functions. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > I think this is the last old_mmio user. We can clean up the > core code once all the on-list patches get into master. > --- > hw/intc/apic.c | 42 ++++++++++++++++++------------------------ > 1 file changed, 18 insertions(+), 24 deletions(-) > Pinging the x86 maintainers -- this patch has been reviewed, can you take it into your tree, please? thanks -- PMM
On 03/08/2018 12:19, Peter Maydell wrote: > Switch the apic away from using the old_mmio MemoryRegionOps > accessor functions. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > I think this is the last old_mmio user. We can clean up the > core code once all the on-list patches get into master. > --- > hw/intc/apic.c | 42 ++++++++++++++++++------------------------ > 1 file changed, 18 insertions(+), 24 deletions(-) > > diff --git a/hw/intc/apic.c b/hw/intc/apic.c > index 6fda52b86cf..97ffdd820f2 100644 > --- a/hw/intc/apic.c > +++ b/hw/intc/apic.c > @@ -650,31 +650,17 @@ static void apic_timer(void *opaque) > apic_timer_update(s, s->next_time); > } > > -static uint32_t apic_mem_readb(void *opaque, hwaddr addr) > -{ > - return 0; > -} > - > -static uint32_t apic_mem_readw(void *opaque, hwaddr addr) > -{ > - return 0; > -} > - > -static void apic_mem_writeb(void *opaque, hwaddr addr, uint32_t val) > -{ > -} > - > -static void apic_mem_writew(void *opaque, hwaddr addr, uint32_t val) > -{ > -} > - > -static uint32_t apic_mem_readl(void *opaque, hwaddr addr) > +static uint64_t apic_mem_read(void *opaque, hwaddr addr, unsigned size) > { > DeviceState *dev; > APICCommonState *s; > uint32_t val; > int index; > > + if (size < 4) { > + return 0; > + } > + > dev = cpu_get_current_apic(); > if (!dev) { > return 0; > @@ -765,11 +751,17 @@ static void apic_send_msi(MSIMessage *msi) > apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); > } > > -static void apic_mem_writel(void *opaque, hwaddr addr, uint32_t val) > +static void apic_mem_write(void *opaque, hwaddr addr, uint64_t val, > + unsigned size) > { > DeviceState *dev; > APICCommonState *s; > int index = (addr >> 4) & 0xff; > + > + if (size < 4) { > + return; > + } > + > if (addr > 0xfff || !index) { > /* MSI and MMIO APIC are at the same memory location, > * but actually not on the global bus: MSI is on PCI bus > @@ -880,10 +872,12 @@ static void apic_post_load(APICCommonState *s) > } > > static const MemoryRegionOps apic_io_ops = { > - .old_mmio = { > - .read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, }, > - .write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, }, > - }, > + .read = apic_mem_read, > + .write = apic_mem_write, > + .impl.min_access_size = 1, > + .impl.max_access_size = 4, > + .valid.min_access_size = 1, > + .valid.max_access_size = 4, > .endianness = DEVICE_NATIVE_ENDIAN, > }; > > Queued, thanks. Paolo
diff --git a/hw/intc/apic.c b/hw/intc/apic.c index 6fda52b86cf..97ffdd820f2 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -650,31 +650,17 @@ static void apic_timer(void *opaque) apic_timer_update(s, s->next_time); } -static uint32_t apic_mem_readb(void *opaque, hwaddr addr) -{ - return 0; -} - -static uint32_t apic_mem_readw(void *opaque, hwaddr addr) -{ - return 0; -} - -static void apic_mem_writeb(void *opaque, hwaddr addr, uint32_t val) -{ -} - -static void apic_mem_writew(void *opaque, hwaddr addr, uint32_t val) -{ -} - -static uint32_t apic_mem_readl(void *opaque, hwaddr addr) +static uint64_t apic_mem_read(void *opaque, hwaddr addr, unsigned size) { DeviceState *dev; APICCommonState *s; uint32_t val; int index; + if (size < 4) { + return 0; + } + dev = cpu_get_current_apic(); if (!dev) { return 0; @@ -765,11 +751,17 @@ static void apic_send_msi(MSIMessage *msi) apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); } -static void apic_mem_writel(void *opaque, hwaddr addr, uint32_t val) +static void apic_mem_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) { DeviceState *dev; APICCommonState *s; int index = (addr >> 4) & 0xff; + + if (size < 4) { + return; + } + if (addr > 0xfff || !index) { /* MSI and MMIO APIC are at the same memory location, * but actually not on the global bus: MSI is on PCI bus @@ -880,10 +872,12 @@ static void apic_post_load(APICCommonState *s) } static const MemoryRegionOps apic_io_ops = { - .old_mmio = { - .read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, }, - .write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, }, - }, + .read = apic_mem_read, + .write = apic_mem_write, + .impl.min_access_size = 1, + .impl.max_access_size = 4, + .valid.min_access_size = 1, + .valid.max_access_size = 4, .endianness = DEVICE_NATIVE_ENDIAN, };
Switch the apic away from using the old_mmio MemoryRegionOps accessor functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- I think this is the last old_mmio user. We can clean up the core code once all the on-list patches get into master. --- hw/intc/apic.c | 42 ++++++++++++++++++------------------------ 1 file changed, 18 insertions(+), 24 deletions(-) -- 2.17.1