diff mbox series

[07/11] target/arm: Fix offset for LD1R instructions

Message ID 20180809034033.10579-8-richard.henderson@linaro.org
State Superseded
Headers show
Series target/arm: sve linux-user patches | expand

Commit Message

Richard Henderson Aug. 9, 2018, 3:40 a.m. UTC
The immediate should be scaled by the size of the memory reference,
not the size of the elements into which it is loaded.

Cc: qemu-stable@nongnu.org (3.0.1)
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/translate-sve.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

-- 
2.17.1

Comments

Laurent Desnogues Aug. 9, 2018, 5:28 a.m. UTC | #1
On Thu, Aug 9, 2018 at 5:40 AM, Richard Henderson
<richard.henderson@linaro.org> wrote:
> The immediate should be scaled by the size of the memory reference,

> not the size of the elements into which it is loaded.

>

> Cc: qemu-stable@nongnu.org (3.0.1)

> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>


Laurent

> ---

>  target/arm/translate-sve.c | 3 ++-

>  1 file changed, 2 insertions(+), 1 deletion(-)

>

> diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c

> index 9e63b5f8e5..f635822a61 100644

> --- a/target/arm/translate-sve.c

> +++ b/target/arm/translate-sve.c

> @@ -4819,6 +4819,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn)

>      unsigned vsz = vec_full_reg_size(s);

>      unsigned psz = pred_full_reg_size(s);

>      unsigned esz = dtype_esz[a->dtype];

> +    unsigned msz = dtype_msz(a->dtype);

>      TCGLabel *over = gen_new_label();

>      TCGv_i64 temp;

>

> @@ -4842,7 +4843,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn)

>

>      /* Load the data.  */

>      temp = tcg_temp_new_i64();

> -    tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << esz);

> +    tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << msz);

>      tcg_gen_qemu_ld_i64(temp, temp, get_mem_index(s),

>                          s->be_data | dtype_mop[a->dtype]);

>

> --

> 2.17.1

>
diff mbox series

Patch

diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 9e63b5f8e5..f635822a61 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -4819,6 +4819,7 @@  static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn)
     unsigned vsz = vec_full_reg_size(s);
     unsigned psz = pred_full_reg_size(s);
     unsigned esz = dtype_esz[a->dtype];
+    unsigned msz = dtype_msz(a->dtype);
     TCGLabel *over = gen_new_label();
     TCGv_i64 temp;
 
@@ -4842,7 +4843,7 @@  static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn)
 
     /* Load the data.  */
     temp = tcg_temp_new_i64();
-    tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << esz);
+    tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << msz);
     tcg_gen_qemu_ld_i64(temp, temp, get_mem_index(s),
                         s->be_data | dtype_mop[a->dtype]);