diff mbox series

[05/10] target/arm: Implement AArch32 HCR and HCR2

Message ID 20180814124254.5229-6-peter.maydell@linaro.org
State Superseded
Headers show
Series target/arm: Some pieces of support for 32-bit Hyp mode | expand

Commit Message

Peter Maydell Aug. 14, 2018, 12:42 p.m. UTC 
The AArch32 HCR and HCR2 registers alias HCR_EL2
bits [31:0] and [63:32]; implement them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 target/arm/helper.c | 39 +++++++++++++++++++++++++++++++++++----
 1 file changed, 35 insertions(+), 4 deletions(-)

-- 
2.18.0

Comments

Edgar E. Iglesias Aug. 14, 2018, 2:52 p.m. UTC | #1 
On Tue, Aug 14, 2018 at 01:42:49PM +0100, Peter Maydell wrote:
> The AArch32 HCR and HCR2 registers alias HCR_EL2

> bits [31:0] and [63:32]; implement them.


Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>



> 

> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

> ---

>  target/arm/helper.c | 39 +++++++++++++++++++++++++++++++++++----

>  1 file changed, 35 insertions(+), 4 deletions(-)

> 

> diff --git a/target/arm/helper.c b/target/arm/helper.c

> index b6412fe9d1f..9701e413859 100644

> --- a/target/arm/helper.c

> +++ b/target/arm/helper.c

> @@ -3754,11 +3754,15 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {

>        .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,

>        .access = PL2_RW,

>        .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },

> -    { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,

> +    { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,

>        .type = ARM_CP_NO_RAW,

>        .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,

>        .access = PL2_RW,

> -      .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },

> +      .type = ARM_CP_CONST, .resetvalue = 0 },

> +    { .name = "HCR2", .state = ARM_CP_STATE_AA32,

> +      .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,

> +      .access = PL2_RW,

> +      .type = ARM_CP_CONST, .resetvalue = 0 },

>      { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,

>        .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,

>        .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },

> @@ -3872,10 +3876,26 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)

>       * HCR_PTW forbids certain page-table setups

>       * HCR_DC Disables stage1 and enables stage2 translation

>       */

> -    if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {

> +    if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {

>          tlb_flush(CPU(cpu));

>      }

> -    raw_write(env, ri, value);

> +    env->cp15.hcr_el2 = value;

> +}

> +

> +static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri,

> +                          uint64_t value)

> +{

> +    /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */

> +    value = deposit64(env->cp15.hcr_el2, 32, 32, value);

> +    hcr_write(env, NULL, value);

> +}

> +

> +static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri,

> +                         uint64_t value)

> +{

> +    /* Handle HCR write, i.e. write to low half of HCR_EL2 */

> +    value = deposit64(env->cp15.hcr_el2, 0, 32, value);

> +    hcr_write(env, NULL, value);

>  }

>  

>  static const ARMCPRegInfo el2_cp_reginfo[] = {

> @@ -3883,6 +3903,17 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {

>        .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,

>        .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),

>        .writefn = hcr_write },

> +    { .name = "HCR", .state = ARM_CP_STATE_AA32,

> +      .type = ARM_CP_ALIAS,

> +      .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,

> +      .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),

> +      .writefn = hcr_writelow },

> +    { .name = "HCR2", .state = ARM_CP_STATE_AA32,

> +      .type = ARM_CP_ALIAS,

> +      .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,

> +      .access = PL2_RW,

> +      .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2),

> +      .writefn = hcr_writehigh },

>      { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,

>        .type = ARM_CP_ALIAS,

>        .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,

> -- 

> 2.18.0

>
Luc Michel Aug. 16, 2018, 8:55 a.m. UTC | #2 
On 8/14/18 2:42 PM, Peter Maydell wrote:
> The AArch32 HCR and HCR2 registers alias HCR_EL2

> bits [31:0] and [63:32]; implement them.

> 

> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

> ---

>  target/arm/helper.c | 39 +++++++++++++++++++++++++++++++++++----

>  1 file changed, 35 insertions(+), 4 deletions(-)

> 

> diff --git a/target/arm/helper.c b/target/arm/helper.c

> index b6412fe9d1f..9701e413859 100644

> --- a/target/arm/helper.c

> +++ b/target/arm/helper.c

> @@ -3754,11 +3754,15 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {

>        .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,

>        .access = PL2_RW,

>        .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },

> -    { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,

> +    { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,

>        .type = ARM_CP_NO_RAW,

>        .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,

>        .access = PL2_RW,

> -      .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },

> +      .type = ARM_CP_CONST, .resetvalue = 0 },

> +    { .name = "HCR2", .state = ARM_CP_STATE_AA32,

> +      .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,

> +      .access = PL2_RW,

> +      .type = ARM_CP_CONST, .resetvalue = 0 },

As for HACTLR2, shouldn't we avoid defining HCR2 for ARMv7?

>      { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,

>        .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,

>        .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },

> @@ -3872,10 +3876,26 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)

>       * HCR_PTW forbids certain page-table setups

>       * HCR_DC Disables stage1 and enables stage2 translation

>       */

> -    if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {

> +    if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {

>          tlb_flush(CPU(cpu));

>      }

> -    raw_write(env, ri, value);

> +    env->cp15.hcr_el2 = value;

> +}

> +

> +static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri,

> +                          uint64_t value)

> +{

> +    /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */

> +    value = deposit64(env->cp15.hcr_el2, 32, 32, value);

> +    hcr_write(env, NULL, value);

> +}

> +

> +static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri,

> +                         uint64_t value)

> +{

> +    /* Handle HCR write, i.e. write to low half of HCR_EL2 */

> +    value = deposit64(env->cp15.hcr_el2, 0, 32, value);

> +    hcr_write(env, NULL, value);

>  }

>  

>  static const ARMCPRegInfo el2_cp_reginfo[] = {

> @@ -3883,6 +3903,17 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {

>        .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,

>        .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),

>        .writefn = hcr_write },

> +    { .name = "HCR", .state = ARM_CP_STATE_AA32,

> +      .type = ARM_CP_ALIAS,

> +      .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,

> +      .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),

> +      .writefn = hcr_writelow },

> +    { .name = "HCR2", .state = ARM_CP_STATE_AA32,

> +      .type = ARM_CP_ALIAS,

> +      .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,

> +      .access = PL2_RW,

> +      .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2),

> +      .writefn = hcr_writehigh },

Also here. This one could actually be problematic as it allows ARMv7 to
write the upper 32-bits of HCR, since HCR_MASK in hcr_write() is greater
than UINT32_MAX.

-- 
Luc

>      { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,

>        .type = ARM_CP_ALIAS,

>        .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,

>
Peter Maydell Aug. 16, 2018, 9:02 a.m. UTC | #3 
On 16 August 2018 at 09:55, Luc Michel <luc.michel@greensocs.com> wrote:
> On 8/14/18 2:42 PM, Peter Maydell wrote:

>> The AArch32 HCR and HCR2 registers alias HCR_EL2

>> bits [31:0] and [63:32]; implement them.

>>

>> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

>> ---

>>  target/arm/helper.c | 39 +++++++++++++++++++++++++++++++++++----

>>  1 file changed, 35 insertions(+), 4 deletions(-)

>>

>> diff --git a/target/arm/helper.c b/target/arm/helper.c

>> index b6412fe9d1f..9701e413859 100644

>> --- a/target/arm/helper.c

>> +++ b/target/arm/helper.c

>> @@ -3754,11 +3754,15 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {

>>        .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,

>>        .access = PL2_RW,

>>        .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },

>> -    { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,

>> +    { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,

>>        .type = ARM_CP_NO_RAW,

>>        .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,

>>        .access = PL2_RW,

>> -      .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },

>> +      .type = ARM_CP_CONST, .resetvalue = 0 },

>> +    { .name = "HCR2", .state = ARM_CP_STATE_AA32,

>> +      .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,

>> +      .access = PL2_RW,

>> +      .type = ARM_CP_CONST, .resetvalue = 0 },

> As for HACTLR2, shouldn't we avoid defining HCR2 for ARMv7?


Yes. I was working off the v8 register list and should have
cross-checked what was present in v7.

thanks
-- PMM
diff mbox series

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index b6412fe9d1f..9701e413859 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3754,11 +3754,15 @@  static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
       .access = PL2_RW,
       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
-    { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
+    { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
       .type = ARM_CP_NO_RAW,
       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
       .access = PL2_RW,
-      .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
+      .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "HCR2", .state = ARM_CP_STATE_AA32,
+      .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
+      .access = PL2_RW,
+      .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -3872,10 +3876,26 @@  static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
      * HCR_PTW forbids certain page-table setups
      * HCR_DC Disables stage1 and enables stage2 translation
      */
-    if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
+    if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
         tlb_flush(CPU(cpu));
     }
-    raw_write(env, ri, value);
+    env->cp15.hcr_el2 = value;
+}
+
+static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri,
+                          uint64_t value)
+{
+    /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
+    value = deposit64(env->cp15.hcr_el2, 32, 32, value);
+    hcr_write(env, NULL, value);
+}
+
+static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri,
+                         uint64_t value)
+{
+    /* Handle HCR write, i.e. write to low half of HCR_EL2 */
+    value = deposit64(env->cp15.hcr_el2, 0, 32, value);
+    hcr_write(env, NULL, value);
 }
 
 static const ARMCPRegInfo el2_cp_reginfo[] = {
@@ -3883,6 +3903,17 @@  static const ARMCPRegInfo el2_cp_reginfo[] = {
       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
       .writefn = hcr_write },
+    { .name = "HCR", .state = ARM_CP_STATE_AA32,
+      .type = ARM_CP_ALIAS,
+      .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
+      .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
+      .writefn = hcr_writelow },
+    { .name = "HCR2", .state = ARM_CP_STATE_AA32,
+      .type = ARM_CP_ALIAS,
+      .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
+      .access = PL2_RW,
+      .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2),
+      .writefn = hcr_writehigh },
     { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
       .type = ARM_CP_ALIAS,
       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,