[Linaro-uefi,edk2-platforms,v3,06/36] Hisilicon/D06: Add OemMiscLibD06

Message ID 20180816121239.44129-7-ming.huang@linaro.org
State New
Headers show
Series
  • Untitled series #14036
Related show

Commit Message

Ming Huang Aug. 16, 2018, 12:12 p.m.
This library include BoardFeatureD06.c and OemMiscLibD06.c c file,
use for several modules like PciHostBridgeLib and Smbios.
Enlarge macro PCIEDEVICE_REPORT_MAX for D06.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>
---
 Platform/Hisilicon/D06/D06.dsc                                          |     1 +
 Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf          |    47 +
 Silicon/Hisilicon/Include/Library/OemMiscLib.h                          |     6 +-
 Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c          |   432 +
 Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c            |   119 +
 Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06Strings.uni |    64 +
 v2/v2-0000-cover-letter.patch                                           |   316 +
 v2/v2-0001-Silicon-Hisilicon-Modify-the-MRC-interface-for-ot.patch      |   553 +
 v2/v2-0002-Silicon-Hisilicon-Separate-PlatformArch.h.patch              |    64 +
 v2/v2-0003-Silicon-Hisilicon-Acpi-Move-some-macro-to-Platfor.patch      |   168 +
 v2/v2-0004-Silicon-Hisilicon-D0x-Move-dimm-size-definition-t.patch      |    57 +
 v2/v2-0005-Silicon-Hisilicon-D0x-Move-RAS-macro-to-PlatformA.patch      |    68 +
 v2/v2-0006-Hisilicon-D0x-Move-CustomData.Fv-to-common-path-o.patch      |    45 +
 v2/v2-0007-Hisilicon-D0x-Move-IpmiCmdLib-to-common-path-of-H.patch      |    45 +
 v2/v2-0008-Hisilicon-D0x-Unify-FlashFvbDxe-driver.patch                 |   170 +
 v2/v2-0009-Hisilicon-D0X-Rename-the-global-variable-gDS3231R.patch      |   142 +
 v2/v2-0010-Hisilicon-D06-Add-several-base-file-for-D06.patch            |  1160 +++
 v2/v2-0011-Platform-Hisilicon-D06-Add-M41T83RealTimeClockLib.patch      |   818 ++
 v2/v2-0012-Platform-Hisilicon-D06-Add-edk2-non-osi-component.patch      |   149 +
 v2/v2-0013-Hisilicon-D06-Add-OemMiscLibD06.patch                        |   751 ++
 v2/v2-0014-Silicon-Hisilicon-D06-Wait-for-all-disk-ready.patch          |   132 +
 v2/v2-0015-Silicon-Hisilicon-Acpi-Unify-HisiAcipPlatformDxe.patch       |   126 +
 v2/v2-0016-Hisilicon-D06-Add-Debug-Serial-Port-Init-Driver.patch        |   172 +
 v2/v2-0017-Hisilicon-D06-Add-ACPI-Tables-for-D06.patch                  | 10864 ++++++++++++++++++++
 v2/v2-0018-Hisilicon-D06-Add-Hi1620OemConfigUiLib.patch                 |  2268 ++++
 v2/v2-0019-Silicon-Hisilicon-D06-Stop-watchdog.patch                    |   125 +
 v2/v2-0020-Hisilicon-I2C-Modify-I2CLib.c-for-coding-style.patch         |  1161 +++
 v2/v2-0021-Silicon-Hisilicon-I2C-Refactor-I2C-library.patch             |   302 +
 v2/v2-0022-Silicon-Hisilicon-D06-Fix-I2C-enable-fail-issue-f.patch      |    55 +
 v2/v2-0023-Silicon-Hisilicon-D06-Add-I2C-delay-for-HNS-auto-.patch      |    80 +
 v2/v2-0024-Hisilicon-I2C-Fix-a-typo-issue.patch                         |    43 +
 v2/v2-0025-Silicon-Hisilicon-D06-Optimize-HNS-config-CDR-pos.patch      |    44 +
 v2/v2-0026-Silicon-Hisilicon-Setup-Add-Setup-Item-EnableGOP.patch       |    73 +
 v2/v2-0027-Hisilicon-Hi1620-Add-ACPI-PPTT-table.patch                   |   701 ++
 v2/v2-0028-Platform-Hisilicon-D06-Enable-ACPI-PPTT.patch                |    41 +
 v2/v2-0029-Platform-Hisilicon-D06-Add-OemNicLib.patch                   |   647 ++
 v2/v2-0030-Platform-Hisilicon-D06-Add-OemNicConfig2P-Driver.patch       |   204 +
 v2/v2-0031-Hisilicon-D0x-Update-SMBIOS-type9-info.patch                 |   325 +
 v2/v2-0032-Platform-Hisilicon-D06-Add-EarlyConfigPeim-peim.patch        |   227 +
 v2/v2-0033-Platform-Hisilicon-D06-Add-PciHostBridgeLib.patch            |   716 ++
 v2/v2-0034-Hisilicon-D06-add-apei-driver.patch                          |  2508 +++++
 v2/v2-0035-Silicon-Hisilicon-D06-Add-some-Lpc-macro-to-LpcLi.patch      |    85 +
 v2/v2-0036-Platform-Hisilicon-D06-Add-capsule-upgrade-suppor.patch      |   434 +
 v2/v2-0037-Silicon-Hisilicon-D06-Modify-for-close-slave-core.patch      |    33 +
 v2/v2-0038-Silicon-Hisilicon-D06-Add-I2C-Bus-Exception-handl.patch      |    38 +
 v2/v2-0039-Silicon-Hisilicon-Setup-Support-SPCR-table-switch.patch      |    84 +
 v2/v2-0040-Silicon-Hisilicon-setup-Support-SMMU-switch.patch            |   124 +
 v2/v2-0041-Hisilicon-D06-Add-PciPlatformLib.patch                       |   141 +
 v2/v2-0042-Hisilicon-D06-Add-edk2-non-osi-Shell-components.patch        |    74 +
 v2/v2-0043-Platform-Hisilicon-D0x-Update-version-string-to-1.patch      |    62 +
 50 files changed, 27063 insertions(+), 1 deletion(-)

Patch

diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
index 94454569f6..9ca7160dad 100644
--- a/Platform/Hisilicon/D06/D06.dsc
+++ b/Platform/Hisilicon/D06/D06.dsc
@@ -70,6 +70,7 @@ 
 
   TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
   RealTimeClockLib|Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf
+  OemMiscLib|Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
   OemAddressMapLib|Platform/Hisilicon/D06/Library/OemAddressMapD06/OemAddressMapD06.inf
   PlatformSysCtrlLib|Silicon/Hisilicon/Hi1620/Library/PlatformSysCtrlLibHi1620/PlatformSysCtrlLibHi1620.inf
 
diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
new file mode 100644
index 0000000000..8f68f7cec5
--- /dev/null
+++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
@@ -0,0 +1,47 @@ 
+#/** @file
+#
+#    Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2018, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = OemMiscLib
+  FILE_GUID                      = 3002911C-C160-4C46-93BB-782846673EEA
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = OemMiscLib
+
+[Sources.common]
+  BoardFeatureD06.c
+  BoardFeatureD06Strings.uni
+  OemMiscLibD06.c
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  PcdLib
+  SerdesLib
+  TimerLib
+
+[Ppis]
+  gEfiPeiReadOnlyVariable2PpiGuid   ## SOMETIMES_CONSUMES
+
+[Pcd]
+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
+  gHisiTokenSpaceGuid.PcdIsMPBoot
+  gHisiTokenSpaceGuid.PcdSocketMask
+  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
diff --git a/Silicon/Hisilicon/Include/Library/OemMiscLib.h b/Silicon/Hisilicon/Include/Library/OemMiscLib.h
index 87cb498dd7..efecb9aa77 100644
--- a/Silicon/Hisilicon/Include/Library/OemMiscLib.h
+++ b/Silicon/Hisilicon/Include/Library/OemMiscLib.h
@@ -22,7 +22,11 @@ 
 #include <PlatformArch.h>
 #include <Library/I2CLib.h>
 
-#define PCIEDEVICE_REPORT_MAX      4
+#define PCIEDEVICE_REPORT_MAX      8
+#define MAX_PROCESSOR_SOCKETS      MAX_SOCKET
+#define MAX_MEMORY_CHANNELS        MAX_CHANNEL
+#define MAX_DIMM_PER_CHANNEL       MAX_DIMM
+
 typedef struct _REPORT_PCIEDIDVID2BMC{
     UINTN   Bus;
     UINTN   Device;
diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c
new file mode 100644
index 0000000000..7e3f2e2a0e
--- /dev/null
+++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c
@@ -0,0 +1,432 @@ 
+/** @file
+*
+*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2018, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <IndustryStandard/SmBios.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HiiLib.h>
+#include <Library/I2CLib.h>
+#include <Library/IoLib.h>
+#include <Library/OemMiscLib.h>
+#include <Library/SerdesLib.h>
+#include <Protocol/Smbios.h>
+
+#include <PlatformArch.h>
+
+I2C_DEVICE gRtcDevice = {
+  .Socket = 0,
+  .Port = 5,
+  .DeviceType = DEVICE_TYPE_SPD,
+  .SlaveDeviceAddress = 0x68
+};
+
+SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] =
+{
+  {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+
+SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] =
+{
+  {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+
+SERDES_PARAM gSerdesParamNA = {
+  .Hilink0Mode = EmHilink0Hccs1X8Width16,
+  .Hilink1Mode = EmHilink1Hccs0X8Width16,
+  .Hilink2Mode = EmHilink2Pcie2X8,
+  .Hilink3Mode = 0x0,
+  .Hilink4Mode = 0xF,
+  .Hilink5Mode = EmHilink5Sas1X4,
+  .Hilink6Mode = 0x0,
+  .UseSsc      = 0,
+};
+
+SERDES_PARAM gSerdesParamNB = {
+  .Hilink0Mode = EmHilink0Pcie1X8,
+  .Hilink1Mode = EmHilink1Pcie0X8,
+  .Hilink2Mode = EmHilink2Sas0X8,
+  .Hilink3Mode = 0x0,
+  .Hilink4Mode = 0xF,
+  .Hilink5Mode = EmHilink5Pcie2X2Pcie3X2,
+  .Hilink6Mode = 0xF,
+  .UseSsc      = 0,
+};
+
+SERDES_PARAM gSerdesParamS1NA = {
+  .Hilink0Mode = EmHilink0Hccs1X8Width16,
+  .Hilink1Mode = EmHilink1Hccs0X8Width16,
+  .Hilink2Mode = EmHilink2Pcie2X8,
+  .Hilink3Mode = 0x0,
+  .Hilink4Mode = 0xF,
+  .Hilink5Mode = EmHilink5Sas1X4,
+  .Hilink6Mode = 0x0,
+  .UseSsc      = 0,
+};
+
+SERDES_PARAM gSerdesParamS1NB = {
+  .Hilink0Mode = EmHilink0Pcie1X8,
+  .Hilink1Mode = EmHilink1Pcie0X8,
+  .Hilink2Mode = EmHilink2Sas0X8,
+  .Hilink3Mode = 0x0,
+  .Hilink4Mode = 0xF,
+  .Hilink5Mode = EmHilink5Pcie2X2Pcie3X2,
+  .Hilink6Mode = 0xF,
+  .UseSsc      = 0,
+};
+
+
+EFI_STATUS
+OemGetSerdesParam (
+  OUT SERDES_PARAM *ParamA,
+  OUT SERDES_PARAM *ParamB,
+  IN  UINT32       SocketId
+ )
+{
+  if (NULL == ParamA) {
+    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
+    return EFI_INVALID_PARAMETER;
+  } if (NULL == ParamB) {
+    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (0 == SocketId) {
+    (VOID) CopyMem (ParamA, &gSerdesParamNA, sizeof (*ParamA));
+    (VOID) CopyMem (ParamB, &gSerdesParamNB, sizeof (*ParamB));
+  } else {
+    (VOID) CopyMem (ParamA, &gSerdesParamS1NA, sizeof (*ParamA));
+    (VOID) CopyMem (ParamB, &gSerdesParamS1NB, sizeof (*ParamB));
+  }
+
+  return EFI_SUCCESS;
+}
+
+VOID
+OemPcieResetAndOffReset (
+  VOID
+  )
+{
+  return;
+}
+
+SMBIOS_TABLE_TYPE9 gPcieSlotInfo[] = {
+  // PCIe0 Slot 1
+  {
+    {                                       // Hdr
+        EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
+        0,                                  // Length,
+        0                                   // Handle
+    },
+    1,                                      // SlotDesignation
+    SlotTypePciExpressX16,                  // SlotType
+    SlotDataBusWidth16X,                    // SlotDataBusWidth
+    SlotUsageAvailable,                     // SlotUsage
+    SlotLengthOther,                        // SlotLength
+    0x0001,                                 // SlotId
+    {                                       // SlotCharacteristics1
+        0,                                  // CharacteristicsUnknown  :1;
+        0,                                  // Provides50Volts         :1;
+        0,                                  // Provides33Volts         :1;
+        0,                                  // SharedSlot              :1;
+        0,                                  // PcCard16Supported       :1;
+        0,                                  // CardBusSupported        :1;
+        0,                                  // ZoomVideoSupported      :1;
+        0                                   // ModemRingResumeSupported:1;
+    },
+    {                                       // SlotCharacteristics2
+        0,                                  // PmeSignalSupported      :1;
+        0,                                  // HotPlugDevicesSupported :1;
+        0,                                  // SmbusSignalSupported    :1;
+        0                                   // Reserved                :5;
+    },
+    0x00,                                   // SegmentGroupNum
+    0x00,                                   // BusNum
+    0                                       // DevFuncNum
+  },
+  {
+      {                                       // Hdr
+          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
+          0,                                  // Length,
+          0                                   // Handle
+      },
+      1,                                      // SlotDesignation
+      SlotTypePciExpressX8,                   // SlotType
+      SlotDataBusWidth8X,                     // SlotDataBusWidth
+      SlotUsageAvailable,                     // SlotUsage
+      SlotLengthOther,                        // SlotLength
+      0x0002,                                 // SlotId
+      {                                       // SlotCharacteristics1
+          0,                                  // CharacteristicsUnknown  :1;
+          0,                                  // Provides50Volts         :1;
+          0,                                  // Provides33Volts         :1;
+          0,                                  // SharedSlot              :1;
+          0,                                  // PcCard16Supported       :1;
+          0,                                  // CardBusSupported        :1;
+          0,                                  // ZoomVideoSupported      :1;
+          0                                   // ModemRingResumeSupported:1;
+      },
+      {                                       // SlotCharacteristics2
+          0,                                  // PmeSignalSupported      :1;
+          0,                                  // HotPlugDevicesSupported :1;
+          0,                                  // SmbusSignalSupported    :1;
+          0                                   // Reserved                :5;
+      },
+      0x00,                                   // SegmentGroupNum
+      0x00,                                   // BusNum
+      0                                       // DevFuncNum
+  },
+  {
+      {                                       // Hdr
+          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
+          0,                                  // Length,
+          0                                   // Handle
+      },
+      1,                                      // SlotDesignation
+      SlotTypePciExpressX8,                   // SlotType
+      SlotDataBusWidth8X,                     // SlotDataBusWidth
+      SlotUsageAvailable,                     // SlotUsage
+      SlotLengthOther,                        // SlotLength
+      0x0003,                                 // SlotId
+      {                                       // SlotCharacteristics1
+          0,                                  // CharacteristicsUnknown  :1;
+          0,                                  // Provides50Volts         :1;
+          0,                                  // Provides33Volts         :1;
+          0,                                  // SharedSlot              :1;
+          0,                                  // PcCard16Supported       :1;
+          0,                                  // CardBusSupported        :1;
+          0,                                  // ZoomVideoSupported      :1;
+          0                                   // ModemRingResumeSupported:1;
+      },
+      {                                       // SlotCharacteristics2
+          0,                                  // PmeSignalSupported      :1;
+          0,                                  // HotPlugDevicesSupported :1;
+          0,                                  // SmbusSignalSupported    :1;
+          0                                   // Reserved                :5;
+      },
+      0x00,                                   // SegmentGroupNum
+      0x00,                                   // BusNum
+      0                                       // DevFuncNum
+  },
+
+
+  {
+      {                                       // Hdr
+          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
+          0,                                  // Length,
+          0                                   // Handle
+      },
+      1,                                      // SlotDesignation
+      SlotTypePciExpressX8,                   // SlotType
+      SlotDataBusWidth8X,                     // SlotDataBusWidth
+      SlotUsageAvailable,                     // SlotUsage
+      SlotLengthOther,                        // SlotLength
+      0x0004,                                 // SlotId
+      {                                       // SlotCharacteristics1
+          0,                                  // CharacteristicsUnknown  :1;
+          0,                                  // Provides50Volts         :1;
+          0,                                  // Provides33Volts         :1;
+          0,                                  // SharedSlot              :1;
+          0,                                  // PcCard16Supported       :1;
+          0,                                  // CardBusSupported        :1;
+          0,                                  // ZoomVideoSupported      :1;
+          0                                   // ModemRingResumeSupported:1;
+      },
+      {                                       // SlotCharacteristics2
+          0,                                  // PmeSignalSupported      :1;
+          0,                                  // HotPlugDevicesSupported :1;
+          0,                                  // SmbusSignalSupported    :1;
+          0                                   // Reserved                :5;
+      },
+      0x00,                                   // SegmentGroupNum
+      0x00,                                   // BusNum
+      0                                       // DevFuncNum
+  },
+
+  {
+      {                                       // Hdr
+          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
+          0,                                  // Length,
+          0                                   // Handle
+      },
+      1,                                      // SlotDesignation
+      SlotTypePciExpressX16,                  // SlotType
+      SlotDataBusWidth16X,                    // SlotDataBusWidth
+      SlotUsageAvailable,                     // SlotUsage
+      SlotLengthOther,                        // SlotLength
+      0x0005,                                 // SlotId
+      {                                       // SlotCharacteristics1
+          0,                                  // CharacteristicsUnknown  :1;
+          0,                                  // Provides50Volts         :1;
+          0,                                  // Provides33Volts         :1;
+          0,                                  // SharedSlot              :1;
+          0,                                  // PcCard16Supported       :1;
+          0,                                  // CardBusSupported        :1;
+          0,                                  // ZoomVideoSupported      :1;
+          0                                   // ModemRingResumeSupported:1;
+      },
+      {                                       // SlotCharacteristics2
+          0,                                  // PmeSignalSupported      :1;
+          0,                                  // HotPlugDevicesSupported :1;
+          0,                                  // SmbusSignalSupported    :1;
+          0                                   // Reserved                :5;
+      },
+      0x00,                                   // SegmentGroupNum
+      0x00,                                   // BusNum
+      0                                       // DevFuncNum
+  },
+  {
+      {                                       // Hdr
+          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
+          0,                                  // Length,
+          0                                   // Handle
+      },
+      1,                                      // SlotDesignation
+      SlotTypePciExpressX8,                   // SlotType
+      SlotDataBusWidth8X,                     // SlotDataBusWidth
+      SlotUsageAvailable,                     // SlotUsage
+      SlotLengthOther,                        // SlotLength
+      0x0006,                                 // SlotId
+      {                                       // SlotCharacteristics1
+          0,                                  // CharacteristicsUnknown  :1;
+          0,                                  // Provides50Volts         :1;
+          0,                                  // Provides33Volts         :1;
+          0,                                  // SharedSlot              :1;
+          0,                                  // PcCard16Supported       :1;
+          0,                                  // CardBusSupported        :1;
+          0,                                  // ZoomVideoSupported      :1;
+          0                                   // ModemRingResumeSupported:1;
+      },
+      {                                       // SlotCharacteristics2
+          0,                                  // PmeSignalSupported      :1;
+          0,                                  // HotPlugDevicesSupported :1;
+          0,                                  // SmbusSignalSupported    :1;
+          0                                   // Reserved                :5;
+      },
+      0x00,                                   // SegmentGroupNum
+      0x00,                                   // BusNum
+      0                                       // DevFuncNum
+  },
+  {
+      {                                       // Hdr
+          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
+          0,                                  // Length,
+          0                                   // Handle
+      },
+      1,                                      // SlotDesignation
+      SlotTypePciExpressX8,                   // SlotType
+      SlotDataBusWidth8X,                     // SlotDataBusWidth
+      SlotUsageAvailable,                     // SlotUsage
+      SlotLengthOther,                        // SlotLength
+      0x0007,                                 // SlotId
+      {                                       // SlotCharacteristics1
+          0,                                  // CharacteristicsUnknown  :1;
+          0,                                  // Provides50Volts         :1;
+          0,                                  // Provides33Volts         :1;
+          0,                                  // SharedSlot              :1;
+          0,                                  // PcCard16Supported       :1;
+          0,                                  // CardBusSupported        :1;
+          0,                                  // ZoomVideoSupported      :1;
+          0                                   // ModemRingResumeSupported:1;
+      },
+      {                                       // SlotCharacteristics2
+          0,                                  // PmeSignalSupported      :1;
+          0,                                  // HotPlugDevicesSupported :1;
+          0,                                  // SmbusSignalSupported    :1;
+          0                                   // Reserved                :5;
+      },
+      0x00,                                   // SegmentGroupNum
+      0x00,                                   // BusNum
+      0                                       // DevFuncNum
+  },
+  {
+      {                                       // Hdr
+          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
+          0,                                  // Length,
+          0                                   // Handle
+      },
+      1,                                      // SlotDesignation
+      SlotTypePciExpressX8,                   // SlotType
+      SlotDataBusWidth8X,                     // SlotDataBusWidth
+      SlotUsageAvailable,                     // SlotUsage
+      SlotLengthOther,                        // SlotLength
+      0x0008,                                 // SlotId
+      {                                       // SlotCharacteristics1
+          0,                                  // CharacteristicsUnknown  :1;
+          0,                                  // Provides50Volts         :1;
+          0,                                  // Provides33Volts         :1;
+          0,                                  // SharedSlot              :1;
+          0,                                  // PcCard16Supported       :1;
+          0,                                  // CardBusSupported        :1;
+          0,                                  // ZoomVideoSupported      :1;
+          0                                   // ModemRingResumeSupported:1;
+      },
+      {                                       // SlotCharacteristics2
+          0,                                  // PmeSignalSupported      :1;
+          0,                                  // HotPlugDevicesSupported :1;
+          0,                                  // SmbusSignalSupported    :1;
+          0                                   // Reserved                :5;
+      },
+      0x00,                                   // SegmentGroupNum
+      0x00,                                   // BusNum
+      0                                       // DevFuncNum
+  },
+
+  };
+
+UINT8
+OemGetPcieSlotNumber (
+  VOID
+  )
+{
+  return sizeof (gPcieSlotInfo) / sizeof (SMBIOS_TABLE_TYPE9);
+}
+
+EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = {
+  {{STRING_TOKEN(STR_LEMON_C10_DIMM_000), STRING_TOKEN(STR_LEMON_C10_DIMM_001)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_010), STRING_TOKEN(STR_LEMON_C10_DIMM_011)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_020), STRING_TOKEN(STR_LEMON_C10_DIMM_021)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_030), STRING_TOKEN(STR_LEMON_C10_DIMM_031)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_040), STRING_TOKEN(STR_LEMON_C10_DIMM_041)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_050), STRING_TOKEN(STR_LEMON_C10_DIMM_051)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_060), STRING_TOKEN(STR_LEMON_C10_DIMM_061)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_070), STRING_TOKEN(STR_LEMON_C10_DIMM_071)}},
+
+  {{STRING_TOKEN(STR_LEMON_C10_DIMM_100), STRING_TOKEN(STR_LEMON_C10_DIMM_101)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_110), STRING_TOKEN(STR_LEMON_C10_DIMM_111)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_120), STRING_TOKEN(STR_LEMON_C10_DIMM_121)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_130), STRING_TOKEN(STR_LEMON_C10_DIMM_131)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_140), STRING_TOKEN(STR_LEMON_C10_DIMM_141)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_150), STRING_TOKEN(STR_LEMON_C10_DIMM_151)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_160), STRING_TOKEN(STR_LEMON_C10_DIMM_161)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_170), STRING_TOKEN(STR_LEMON_C10_DIMM_171)}}
+};
+
+EFI_HII_HANDLE
+EFIAPI
+OemGetPackages (
+  VOID
+  )
+{
+  return HiiAddPackages (
+           &gEfiCallerIdGuid,
+           NULL,
+           OemMiscLibStrings,
+           NULL,
+           NULL
+           );
+}
+
+
diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c
new file mode 100644
index 0000000000..95521752ff
--- /dev/null
+++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c
@@ -0,0 +1,119 @@ 
+/** @file
+*
+*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2018, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <PlatformArch.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/LpcLib.h>
+#include <Library/OemAddressMapLib.h>
+#include <Library/OemMiscLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PlatformSysCtrlLib.h>
+#include <Library/SerdesLib.h>
+#include <Library/SerialPortLib.h>
+#include <Library/TimerLib.h>
+
+REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {
+  {67,0,0,0},
+  {225,0,0,3},
+  {0xFFFF,0xFFFF,0xFFFF,0xFFFF},
+  {0xFFFF,0xFFFF,0xFFFF,0xFFFF}
+};
+
+// Right now we only support 1P
+BOOLEAN
+OemIsSocketPresent (
+  UINTN Socket
+  )
+{
+  UINT32 SocketMask = PcdGet32 (PcdSocketMask);
+  return (BOOLEAN)((SocketMask & (1 << Socket)) ? TRUE : FALSE);
+}
+
+
+UINTN
+OemGetSocketNumber (
+  VOID
+  )
+{
+  if(!OemIsMpBoot ()) {
+    return 1;
+  }
+
+  return MAX_PROCESSOR_SOCKETS;
+}
+
+
+UINTN
+OemGetDdrChannel (
+  VOID
+  )
+{
+  return MAX_MEMORY_CHANNELS;
+}
+
+
+UINTN
+OemGetDimmSlot (
+  UINTN Socket,
+  UINTN Channel
+  )
+{
+  return MAX_DIMM_PER_CHANNEL;
+}
+
+
+BOOLEAN
+OemIsMpBoot (
+  VOID
+  )
+{
+  return PcdGet32 (PcdIsMPBoot);
+}
+
+VOID
+OemLpcInit (
+  VOID
+  )
+{
+  LpcInit ();
+  return;
+}
+
+UINT32
+OemIsWarmBoot (
+  VOID
+  )
+{
+  return 0;
+}
+
+VOID
+OemBiosSwitch (
+  UINT32 Master
+  )
+{
+  (VOID)Master;
+  return;
+}
+
+BOOLEAN
+OemIsNeedDisableExpanderBuffer (
+  VOID
+  )
+{
+  return TRUE;
+}
diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06Strings.uni b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06Strings.uni
new file mode 100644
index 0000000000..046fa05dff
--- /dev/null
+++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06Strings.uni
@@ -0,0 +1,64 @@ 
+// *++
+//
+// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// --*/
+
+/=#
+
+#langdef en-US "English"
+
+//
+// Begin English Language Strings
+//
+#string STR_MEMORY_SUBCLASS_UNKNOWN    #language en-US  "Unknown"
+
+//
+// DIMM Device Locator strings
+
+// D06
+#string STR_LEMON_C10_DIMM_000     #language en-US "J5"
+#string STR_LEMON_C10_DIMM_001     #language en-US "J6"
+#string STR_LEMON_C10_DIMM_010     #language en-US "J7"
+#string STR_LEMON_C10_DIMM_011     #language en-US "J8"
+#string STR_LEMON_C10_DIMM_020     #language en-US "J9"
+#string STR_LEMON_C10_DIMM_021     #language en-US "J10"
+#string STR_LEMON_C10_DIMM_030     #language en-US "J11"
+#string STR_LEMON_C10_DIMM_031     #language en-US "J12"
+#string STR_LEMON_C10_DIMM_040     #language en-US "J13"
+#string STR_LEMON_C10_DIMM_041     #language en-US "J14"
+#string STR_LEMON_C10_DIMM_050     #language en-US "J15"
+#string STR_LEMON_C10_DIMM_051     #language en-US "J16"
+#string STR_LEMON_C10_DIMM_060     #language en-US "J17"
+#string STR_LEMON_C10_DIMM_061     #language en-US "J18"
+#string STR_LEMON_C10_DIMM_070     #language en-US "J19"
+#string STR_LEMON_C10_DIMM_071     #language en-US "J20"
+#string STR_LEMON_C10_DIMM_100     #language en-US "J21"
+#string STR_LEMON_C10_DIMM_101     #language en-US "J22"
+#string STR_LEMON_C10_DIMM_110     #language en-US "J23"
+#string STR_LEMON_C10_DIMM_111     #language en-US "J24"
+#string STR_LEMON_C10_DIMM_120     #language en-US "J25"
+#string STR_LEMON_C10_DIMM_121     #language en-US "J26"
+#string STR_LEMON_C10_DIMM_130     #language en-US "J27"
+#string STR_LEMON_C10_DIMM_131     #language en-US "J28"
+#string STR_LEMON_C10_DIMM_140     #language en-US "J29"
+#string STR_LEMON_C10_DIMM_141     #language en-US "J30"
+#string STR_LEMON_C10_DIMM_150     #language en-US "J31"
+#string STR_LEMON_C10_DIMM_151     #language en-US "J32"
+#string STR_LEMON_C10_DIMM_160     #language en-US "J33"
+#string STR_LEMON_C10_DIMM_161     #language en-US "J34"
+#string STR_LEMON_C10_DIMM_170     #language en-US "J35"
+#string STR_LEMON_C10_DIMM_171     #language en-US "J36"
+
+//
+// End English Language Strings
+//
+
diff --git a/v2/v2-0000-cover-letter.patch b/v2/v2-0000-cover-letter.patch
new file mode 100644
index 0000000000..b2fe3e351f
--- /dev/null
+++ b/v2/v2-0000-cover-letter.patch
@@ -0,0 +1,316 @@ 
+From 7181548f40616d5086dba15cc557703e517e9c50 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Tue, 14 Aug 2018 16:06:00 +0800
+Subject: [PATCH edk2-platforms v2 00/43] Upload for D06 platform 
+
+The major features of this patchset include:
+1 D06 source code;
+2 Unify some D0x modules;
+
+This patch set is base on pcihostbridage-v2.
+For compiling D06, add below hunk to edk2-platforms.config
+[d06]
+LONGNAME=HiSilicon D06
+DSC=Platform/Hisilicon/D06/D06.dsc
+ARCH=AARCH64
+
+Code can also be found in github: https://github.com/hisilicon/OpenPlatformPkg.git
+branch: d06-platform-v2
+
+
+Heyi Guo (3):
+  Hisilicon/D06: Add Debug Serial Port Init Driver
+  Hisilicon/Hi1620: Add ACPI PPTT table
+  Platform/Hisilicon/D06: Enable ACPI PPTT
+
+Luqi Jiang (1):
+  Hisilicon/D06: add apei driver
+
+Ming Huang (32):
+  Silicon/Hisilicon: Modify the MRC interface for other module
+  Silicon/Hisilicon: Separate PlatformArch.h
+  Silicon/Hisilicon/Acpi: Move some macro to PlatformArch.h
+  Hisilicon/D0x: Move CustomData.Fv to common path of Hisilicon
+  Hisilicon/D0x: Move IpmiCmdLib to common path of Hisilicon
+  Hisilicon/D0x: Unify FlashFvbDxe driver
+  Hisilicon/D0X: Rename the global variable gDS3231RtcDevice
+  Hisilicon/D06: Add several base file for D06
+  Platform/Hisilicon/D06: Add M41T83RealTimeClockLib
+  Platform/Hisilicon/D06: Add edk2-non-osi components for D06
+  Hisilicon/D06: Add OemMiscLibD06
+  Silicon/Hisilicon/D06: Wait for all disk ready
+  Silicon/Hisilicon/Acpi: Unify HisiAcipPlatformDxe
+  Hisilicon/D06: Add ACPI Tables for D06
+  Silicon/Hisilicon/D06: Stop watchdog
+  Hisilicon/I2C: Modify I2CLib.c for coding style
+  Silicon/Hisilicon/I2C: Refactor I2C library
+  Silicon/Hisilicon/D06: Fix I2C enable fail issue for D06
+  Silicon/Hisilicon/D06: Add I2C delay for HNS auto config
+  Hisilicon/I2C: Fix a typo issue
+  Platform/Hisilicon/D06: Add OemNicLib
+  Platform/Hisilicon/D06: Add OemNicConfig2P Driver
+  Platform/Hisilicon/D06: Add EarlyConfigPeim peim
+  Platform/Hisilicon/D06: Add PciHostBridgeLib
+  Silicon/Hisilicon/D06: Add some Lpc macro to LpcLib.h
+  Platform/Hisilicon/D06: Add capsule upgrade support
+  Silicon/Hisilicon/D06: Add I2C Bus Exception handle function
+  Silicon/Hisilicon/Setup: Support SPCR table switch
+  Silicon/Hisilicon/setup: Support SMMU switch
+  Hisilicon/D06: Add PciPlatformLib
+  Hisilicon/D06: Add edk2-non-osi Shell components
+  Platform/Hisilicon/D0x: Update version string to 18.08
+
+Sun Yuanchen (3):
+  Silicon/Hisilicon/D0x: Move dimm size definition to PlatformArch.h
+  Silicon/Hisilicon/D0x: Move RAS macro to PlatformArch.h
+  Hisilicon/D0x: Update SMBIOS type9 info
+
+Yang XinYi (2):
+  Hisilicon/D06: Add Hi1620OemConfigUiLib
+  Silicon/Hisilicon/Setup: Add Setup Item "EnableGOP"
+
+ZhenYao (1):
+  Silicon/Hisilicon/D06: Modify for close slave core clock.
+
+shaochangliang (1):
+  Silicon/Hisilicon/D06: Optimize HNS config CDR post time
+
+ Platform/Hisilicon/D06/D06.dec                |   29 +
+ Silicon/Hisilicon/HisiPkg.dec                 |    6 +
+ Platform/Hisilicon/D03/D03.dsc                |    4 +-
+ Platform/Hisilicon/D05/D05.dsc                |    4 +-
+ Platform/Hisilicon/D06/D06.dsc                |  490 ++++
+ Platform/Hisilicon/D03/D03.fdf                |    8 +-
+ Platform/Hisilicon/D05/D05.fdf                |    8 +-
+ Platform/Hisilicon/D06/D06.fdf                |  444 ++++
+ .../OemMiscLib2P/OemMiscLib2PHi1610.inf       |    1 +
+ .../Library/OemMiscLibD05/OemMiscLibD05.inf   |    1 +
+ .../OemNicConfig2PHi1620/OemNicConfig2P.inf   |   43 +
+ .../SystemFirmwareDescriptor.inf              |   50 +
+ .../EarlyConfigPeim/EarlyConfigPeimD06.inf    |   50 +
+ .../Library/OemMiscLibD06/OemMiscLibD06.inf   |   51 +
+ .../D06/Library/OemNicLib/OemNicLib.inf       |   35 +
+ .../PciHostBridgeLib/PciHostBridgeLib.inf     |   36 +
+ .../Drivers/FlashFvbDxe/FlashFvbDxe.inf       |    7 +-
+ .../HisiAcpiPlatformDxe/AcpiPlatformDxe.inf   |    3 +-
+ .../ProcessorSubClassDxe.inf                  |    2 +
+ .../Hisilicon/Hi1620/Drivers/Apei/Apei.inf    |   64 +
+ .../Pl011DebugSerialPortInitDxe.inf           |   48 +
+ .../Hi1620AcpiTables/AcpiTablesHi1620.inf     |   59 +
+ .../Hi1620OemConfigUiLib/OemConfigUiLib.inf   |   68 +
+ .../Hi1620PciPlatformLib.inf                  |   30 +
+ Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf        |   48 +
+ .../M41T83RealTimeClockLib.inf                |   46 +
+ .../PlatformBootManagerLib.inf                |    4 +
+ .../OemNicConfig2PHi1620/OemNicConfig.h       |   25 +
+ .../Hisilicon/D06/Include/Library/CpldD06.h   |   39 +
+ .../Smbios/MemorySubClassDxe/MemorySubClass.h |    2 -
+ .../Hi1610/Hi1610AcpiTables/Hi1610Platform.h  |   27 +-
+ .../Hisilicon/Hi1610/Include/PlatformArch.h   |   71 +
+ .../Hi1616/D05AcpiTables/Hi1616Platform.h     |   24 +-
+ .../Hisilicon/Hi1616/Include/PlatformArch.h   |   71 +
+ Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.h  |   41 +
+ .../Hisilicon/Hi1620/Drivers/Apei/Bert/bert.h |   43 +
+ .../Hisilicon/Hi1620/Drivers/Apei/Einj/einj.h |  146 ++
+ .../Hi1620/Drivers/Apei/ErrorSource/Ghes.h    |  110 +
+ .../Hisilicon/Hi1620/Drivers/Apei/Erst/erst.h |  146 ++
+ .../Hisilicon/Hi1620/Drivers/Apei/Hest/hest.h |   59 +
+ .../Hi1620/Drivers/Apei/OemApeiHi1620.h       |   43 +
+ .../Hi1620/Hi1620AcpiTables/Hi1620Platform.h  |   27 +
+ .../Hi1620/Hi1620OemConfigUiLib/OemConfig.h   |  142 ++
+ .../Hi1620/Hi1620OemConfigUiLib/OemConfigUi.h |   64 +
+ .../Hi1620/Include/Library/SerdesLib.h        |   85 +
+ .../Hisilicon/Hi1620/Include/PlatformArch.h   |   67 +
+ Silicon/Hisilicon/Hi1620/Pptt/Pptt.h          |   68 +
+ .../Hisilicon/Include/Library/AcpiNextLib.h   |   31 +-
+ .../Hisilicon/Include/Library/HwMemInitLib.h  |  356 +--
+ .../Hisilicon/Include/Library/IpmiCmdLib.h    |   16 +
+ Silicon/Hisilicon/Include/Library/LpcLib.h    |   51 +-
+ .../Include/Library/OemAddressMapLib.h        |    8 +
+ .../Hisilicon/Include/Library/OemConfigData.h |   85 +
+ .../Hisilicon/Include/Library/OemMiscLib.h    |    9 +-
+ Silicon/Hisilicon/Include/Library/OemNicLib.h |   57 +
+ .../Include/Library/PlatformSysCtrlLib.h      |    6 +
+ Silicon/Hisilicon/Include/PlatformArch.h      |   35 -
+ Silicon/Hisilicon/Library/I2CLib/I2CHw.h      |    9 +-
+ .../M41T83RealTimeClock.h                     |  158 ++
+ .../DS3231RealTimeClockLib.c                  |    8 +-
+ .../OemMiscLib2P/BoardFeature2PHi1610.c       |    2 +-
+ .../Library/OemMiscLib2P/OemMiscLib2PHi1610.c |   24 +
+ .../Library/OemMiscLibD05/BoardFeatureD05.c   |    2 +-
+ .../D05/Library/OemMiscLibD05/OemMiscLibD05.c |   27 +-
+ .../OemNicConfig2PHi1620/OemNicConfig2P.c     |   71 +
+ .../SystemFirmwareDescriptorPei.c             |   70 +
+ .../D06/EarlyConfigPeim/EarlyConfigPeimD06.c  |  107 +
+ .../Library/OemMiscLibD06/BoardFeatureD06.c   |  432 ++++
+ .../D06/Library/OemMiscLibD06/OemMiscLibD06.c |  222 ++
+ .../D06/Library/OemNicLib/OemNicLib.c         |  570 +++++
+ .../PciHostBridgeLib/PciHostBridgeLib.c       |  635 ++++++
+ .../Drivers/FlashFvbDxe/FlashFvbDxe.c         |   22 +-
+ .../HisiAcpiPlatformDxe/UpdateAcpiTable.c     |  118 +-
+ .../Smbios/AddSmbiosType9/AddSmbiosType9.c    |   14 +-
+ .../Smbios/MemorySubClassDxe/MemorySubClass.c |   26 +-
+ Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.c  |  108 +
+ .../Hisilicon/Hi1620/Drivers/Apei/Bert/bert.c |   92 +
+ .../Hisilicon/Hi1620/Drivers/Apei/Einj/einj.c |  349 +++
+ .../Hi1620/Drivers/Apei/ErrorSource/Ghes.c    |  330 +++
+ .../Hisilicon/Hi1620/Drivers/Apei/Erst/erst.c |  374 ++++
+ .../Hisilicon/Hi1620/Drivers/Apei/Hest/hest.c |  119 +
+ .../Hi1620/Drivers/Apei/OemApeiHi1620.c       |  337 +++
+ .../Pl011DebugSerialPortInitDxe.c             |   64 +
+ .../Hi1620/Hi1620OemConfigUiLib/OemConfig.c   |  364 +++
+ .../Hi1620PciPlatformLib.c                    |   67 +
+ Silicon/Hisilicon/Hi1620/Pptt/Pptt.c          |  543 +++++
+ .../DS3231RealTimeClockLib.c                  |    8 +-
+ Silicon/Hisilicon/Library/I2CLib/I2CLib.c     |  975 ++++----
+ .../M41T83RealTimeClockLib.c                  |  564 +++++
+ .../PlatformBootManagerLib/PlatformBm.c       |   65 +
+ .../SystemFirmwareUpdateConfig.ini            |   46 +
+ .../SystemFirmwareDescriptor.aslc             |   81 +
+ .../OemMiscLibD06/BoardFeatureD06Strings.uni  |   64 +
+ .../Hi1620/Hi1620AcpiTables/Dsdt/CPU.asl      |  409 ++++
+ .../Hi1620/Hi1620AcpiTables/Dsdt/Com.asl      |   30 +
+ .../Hi1620AcpiTables/Dsdt/DsdtHi1620.asl      |   35 +
+ .../Hi1620AcpiTables/Dsdt/Hi1620Apei.asl      |   93 +
+ .../Hi1620AcpiTables/Dsdt/Hi1620Ged.asl       |   58 +
+ .../Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl      | 1459 ++++++++++++
+ .../Hi1620AcpiTables/Dsdt/Hi1620Mctp.asl      |   41 +
+ .../Hi1620AcpiTables/Dsdt/Hi1620Pci.asl       | 1216 ++++++++++
+ .../Hi1620AcpiTables/Dsdt/Hi1620Power.asl     |   28 +
+ .../Hi1620AcpiTables/Dsdt/Hi1620Rde.asl       |   47 +
+ .../Hi1620AcpiTables/Dsdt/Hi1620Sec.asl       |   57 +
+ .../Dsdt/Hi1620Socip4_i2c100k.asl             |  249 +++
+ .../Dsdt/Hi1620Socip4_i2c400k.asl             |  249 +++
+ .../Hi1620AcpiTables/Dsdt/LpcUart_clk.asl     |   49 +
+ .../Hi1620AcpiTables/Dsdt/Pv680UncorePmu.asl  | 1658 ++++++++++++++
+ .../Hi1620/Hi1620AcpiTables/Dsdt/ipmi.asl     |   49 +
+ .../Hi1620/Hi1620AcpiTables/Facs.aslc         |   67 +
+ .../Hi1620/Hi1620AcpiTables/Fadt.aslc         |   91 +
+ .../Hi1620/Hi1620AcpiTables/Gtdt.aslc         |   86 +
+ .../Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc   |   86 +
+ .../Hi1620/Hi1620AcpiTables/Hi1620Iort.asl    | 1989 +++++++++++++++++
+ .../Hi1620AcpiTables/Hi1620IortNoSmmu.asl     | 1736 ++++++++++++++
+ .../Hi1620/Hi1620AcpiTables/Hi1620Mcfg.aslc   |   64 +
+ .../Hi1620/Hi1620AcpiTables/Hi1620Slit.aslc   |   64 +
+ .../Hi1620/Hi1620AcpiTables/Hi1620Spcr.aslc   |   81 +
+ .../Hi1620/Hi1620AcpiTables/Hi1620Srat.aslc   |  166 ++
+ .../Hi1620/Hi1620AcpiTables/MadtHi1620.aslc   |  375 ++++
+ .../Hi1620OemConfigUiLib/MemoryConfig.hfr     |  154 ++
+ .../Hi1620OemConfigUiLib/MemoryConfig.uni     |  103 +
+ .../Hi1620OemConfigUiLib/MiscConfig.hfr       |   48 +
+ .../Hi1620OemConfigUiLib/MiscConfig.uni       |   27 +
+ .../Hi1620OemConfigUiLib/OemConfigUiLib.uni   |   24 +
+ .../OemConfigUiLibStrings.uni                 |   42 +
+ .../Hi1620OemConfigUiLib/OemConfigVfr.Vfr     |   89 +
+ .../Hi1620OemConfigUiLib/PcieConfig.hfr       |  219 ++
+ .../PcieConfigStrings.uni                     |  111 +
+ .../Hi1620OemConfigUiLib/PciePortConfig.hfr   |  167 ++
+ .../Hi1620/Hi1620OemConfigUiLib/RasConfig.hfr |  172 ++
+ .../Hi1620/Hi1620OemConfigUiLib/RasConfig.uni |   85 +
+ .../Hi1620OemConfigUiLib/iBMCConfig.hfr       |   81 +
+ .../Hi1620OemConfigUiLib/iBMCConfig.uni       |   34 +
+ 134 files changed, 21578 insertions(+), 970 deletions(-)
+ create mode 100644 Platform/Hisilicon/D06/D06.dec
+ create mode 100644 Platform/Hisilicon/D06/D06.dsc
+ create mode 100644 Platform/Hisilicon/D06/D06.fdf
+ create mode 100644 Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.inf
+ create mode 100644 Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
+ create mode 100644 Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf
+ create mode 100644 Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
+ create mode 100644 Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.inf
+ create mode 100644 Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.inf
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.inf
+ create mode 100644 Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.inf
+ create mode 100644 Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf
+ create mode 100644 Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf
+ create mode 100644 Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig.h
+ create mode 100644 Platform/Hisilicon/D06/Include/Library/CpldD06.h
+ create mode 100644 Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
+ create mode 100644 Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Bert/bert.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Einj/einj.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/ErrorSource/Ghes.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Erst/erst.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Hest/hest.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/OemApeiHi1620.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Platform.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUi.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Include/PlatformArch.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Pptt/Pptt.h
+ create mode 100644 Silicon/Hisilicon/Include/Library/OemConfigData.h
+ create mode 100644 Silicon/Hisilicon/Include/Library/OemNicLib.h
+ delete mode 100644 Silicon/Hisilicon/Include/PlatformArch.h
+ create mode 100644 Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClock.h
+ create mode 100644 Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.c
+ create mode 100644 Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
+ create mode 100644 Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c
+ create mode 100644 Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c
+ create mode 100644 Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c
+ create mode 100644 Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c
+ create mode 100644 Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.c
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.c
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Bert/bert.c
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Einj/einj.c
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/ErrorSource/Ghes.c
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Erst/erst.c
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Hest/hest.c
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/OemApeiHi1620.c
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.c
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c
+ create mode 100644 Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.c
+ create mode 100644 Silicon/Hisilicon/Hi1620/Pptt/Pptt.c
+ create mode 100644 Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.c
+ create mode 100644 Platform/Hisilicon/D06/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
+ create mode 100644 Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
+ create mode 100644 Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06Strings.uni
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/CPU.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Com.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/DsdtHi1620.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Apei.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Ged.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mctp.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Power.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Rde.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Sec.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c100k.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c400k.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/LpcUart_clk.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Pv680UncorePmu.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/ipmi.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Facs.aslc
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Fadt.aslc
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Gtdt.aslc
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Mcfg.aslc
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Slit.aslc
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Spcr.aslc
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Srat.aslc
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/MadtHi1620.aslc
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MemoryConfig.hfr
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MemoryConfig.uni
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.hfr
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.uni
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.uni
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLibStrings.uni
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.Vfr
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PciePortConfig.hfr
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/RasConfig.hfr
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/RasConfig.uni
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/iBMCConfig.hfr
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/iBMCConfig.uni
+
+-- 
+2.17.0
+
diff --git a/v2/v2-0001-Silicon-Hisilicon-Modify-the-MRC-interface-for-ot.patch b/v2/v2-0001-Silicon-Hisilicon-Modify-the-MRC-interface-for-ot.patch
new file mode 100644
index 0000000000..92d1dc2682
--- /dev/null
+++ b/v2/v2-0001-Silicon-Hisilicon-Modify-the-MRC-interface-for-ot.patch
@@ -0,0 +1,553 @@ 
+From 7305eac29491a482f4de3875e85486842ca3a389 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Fri, 20 Jul 2018 17:49:43 +0800
+Subject: [PATCH edk2-platforms v2 01/43] Silicon/Hisilicon: Modify the MRC
+ interface for other module
+
+This patch is to unify D0x. Add pGBL_INTERFACE struct define
+and remove useless interfece. Replace DMRC pGblData with pGblInterface;
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Silicon/Hisilicon/Include/Library/HwMemInitLib.h                    | 356 ++++----------------
+ Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c     |   4 +-
+ Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.c |  26 +-
+ 3 files changed, 78 insertions(+), 308 deletions(-)
+
+diff --git a/Silicon/Hisilicon/Include/Library/HwMemInitLib.h b/Silicon/Hisilicon/Include/Library/HwMemInitLib.h
+index 2663cad836..e1310e854c 100644
+--- a/Silicon/Hisilicon/Include/Library/HwMemInitLib.h
++++ b/Silicon/Hisilicon/Include/Library/HwMemInitLib.h
+@@ -50,48 +50,6 @@ typedef enum {
+     DDR_FREQ_MAX
+ } DDR_FREQUENCY_INDEX;
+ 
+-typedef struct _DDR_FREQ_TCK
+-{
+-    UINT32      ddrFreq;
+-    UINT32      ddrCk;
+-}DDR_FREQ_TCK;
+-
+-typedef struct _GBL_CFG{
+-
+-
+-}GBL_CFG;
+-
+-typedef struct _GBL_VAR{
+-
+-
+-}GBL_VAR;
+-
+-typedef struct _GBL_NVDATA{
+-
+-
+-}GBL_NVDATA;
+-
+-typedef struct _GOBAL {
+-    const GBL_CFG Config;  // constant input data
+-    GBL_VAR       Variable;    // variable, volatile data
+-    GBL_NVDATA    NvData;  // variable, non-volatile data for S3, warm boot path
+-    UINT32        PreBootFailed;
+-}GOBAL, *PGOBAL;
+-
+-struct DDR_RANK {
+-    BOOLEAN     Status;
+-    UINT16      RttNom;
+-    UINT16      RttPark;
+-    UINT16      RttWr;
+-    UINT16      MR0;
+-    UINT16      MR1;
+-    UINT16      MR2;
+-    UINT16      MR3;
+-    UINT16      MR4;
+-    UINT16      MR5;
+-    UINT16      MR6[9];
+-};
+-
+ struct baseMargin {
+   INT16 n;
+   INT16 p;
+@@ -101,171 +59,7 @@ struct rankMargin {
+   struct baseMargin rank[MAX_CHANNEL][MAX_RANK_CH];
+ };
+ 
+-typedef struct _DDR_DIMM{
+-    BOOLEAN     Status;
+-    UINT8       mapout;
+-    UINT8       DramType;           //Byte 2
+-    UINT8       ModuleType;         //Byte 3
+-    UINT8       ExtendModuleType;
+-    UINT8       SDRAMCapacity;      //Byte 4
+-    UINT8       BankNum;
+-    UINT8       BGNum;              //Byte 4 For DDR4
+-    UINT8       RowBits;            //Byte 5
+-    UINT8       ColBits;            //Byte 5
+-    UINT8       SpdVdd;             //Byte 6
+-    UINT8       DramWidth;          //Byte 7
+-    UINT8       RankNum;            //Byte 7
+-    UINT8       PrimaryBusWidth;    //Byte 8
+-    UINT8       ExtensionBusWidth;  //Byte 8
+-    UINT32      Mtb;
+-    UINT32      Ftb;
+-    UINT32      minTck;
+-    UINT8       MtbDividend;
+-    UINT8       MtbDivsor;
+-    UINT8       nCL;
+-    UINT32      nRCD;
+-    UINT32      nRP;
+-    UINT8       SPDftb;
+-    UINT8       SpdMinTCK;
+-    UINT8       SpdMinTCKFtb;
+-    UINT8       SpdMaxTCK;
+-    UINT8       SpdMinTCL;
+-    UINT8       SpdMinTCLFtb;
+-    UINT8       SpdMinTWR;
+-    UINT8       SpdMinTRCD;
+-    UINT8       SpdMinTRCDFtb;
+-    UINT8       SpdMinTRRD;
+-    UINT8       SpdMinTRRDL;
+-    UINT16      SpdMinTRAS;
+-    UINT16      SpdMinTRC;
+-    UINT16      SpdMinTRCFtb;
+-    UINT16      SpdMinTRFC;
+-    UINT8       SpdMinTWTR;
+-    UINT8       SpdMinTRTP;
+-    UINT8       SpdMinTAA;
+-    UINT8       SpdMinTAAFtb;
+-    UINT8       SpdMinTFAW;
+-    UINT8       SpdMinTRP;
+-    UINT8       SpdMinTRPFtb;
+-    UINT8       SpdMinTCCDL;
+-    UINT8       SpdMinTCCDLFtb;
+-    UINT8       SpdAddrMap;
+-    UINT8       SpdModuleAttr;
+-
+-    UINT8       SpdModPart[SPD_MODULE_PART];         // Module Part Number
+-    UINT8       SpdModPartDDR4[SPD_MODULE_PART_DDR4];     // Module Part Number DDR4
+-    UINT16      SpdMMfgId;              // Module Mfg Id from SPD
+-    UINT16      SpdRMId;              // Register Manufacturer Id
+-    UINT16      SpdMMDate;              // Module Manufacturing Date
+-    UINT32      SpdSerialNum;
+-    UINT16      DimmSize;
+-    UINT16      DimmSpeed;
+-    UINT32      RankSize;
+-    UINT8       SpdMirror; //Denote the dram address mapping is standard mode or mirrored mode
+-    struct DDR_RANK  Rank[MAX_RANK_DIMM];
+-}DDR_DIMM;
+-
+-typedef struct {
+-    UINT32      ddrcTiming0;
+-    UINT32      ddrcTiming1;
+-    UINT32      ddrcTiming2;
+-    UINT32      ddrcTiming3;
+-    UINT32      ddrcTiming4;
+-    UINT32      ddrcTiming5;
+-    UINT32      ddrcTiming6;
+-    UINT32      ddrcTiming7;
+-    UINT32      ddrcTiming8;
+-}DDRC_TIMING;
+-
+-typedef struct _MARGIN_RESULT{
+-    UINT32 OptimalDramVref[12];
+-    UINT32 optimalPhyVref[18];
+-}MARGIN_RESULT;
+-
+-typedef struct _DDR_Channel{
+-    BOOLEAN     Status;
+-    UINT8       CurrentDimmNum;
+-    UINT8       CurrentRankNum;
+-    UINT16      RankPresent;
+-    UINT8       DramType;
+-    UINT8       DramWidth;
+-    UINT8       ModuleType;
+-    UINT32      MemSize;
+-    UINT32      tck;
+-    UINT32      ratio;
+-    UINT32      CLSupport;
+-    UINT32      minTck;
+-    UINT32      taref;
+-    UINT32      nAA;
+-    UINT32      nAOND;
+-    UINT32      nCKE;
+-    UINT32      nCL;
+-    UINT32      nCCDL;
+-    UINT32      nCKSRX;
+-    UINT32      nCKSRE;
+-    UINT32      nCCDNSW;
+-    UINT32      nCCDNSR;
+-    UINT32      nFAW;
+-    UINT32      nMRD;
+-    UINT32      nMOD;
+-    UINT32      nRCD;
+-    UINT32      nRRD;
+-    UINT32      nRRDL;
+-    UINT32      nRAS;
+-    UINT32      nRC;
+-    UINT32      nRFC;
+-    UINT32      nRFCAB;
+-    UINT32      nRTP;
+-    UINT32      nRTW;
+-    UINT32      nRP;
+-    UINT32      nSRE;
+-    UINT32      nWL;
+-    UINT32      nWR;
+-    UINT32      nWTR;
+-    UINT32      nWTRL;
+-    UINT32      nXARD;
+-    UINT32      nZQPRD;
+-    UINT32      nZQINIT;
+-    UINT32      nZQCS;
+-    UINT8       cwl;  //tWL?
+-    UINT8       pl;     //parity latency
+-    UINT8       wr_pre_2t_en;
+-    UINT8       rd_pre_2t_en;
+-    UINT8       cmd_2t_en;
+-    UINT8       parity_en;
+-    UINT8       wr_dbi_en;
+-    UINT8       wr_dm_en;
+-    UINT8       ddr4_crc_en;
+-    UINT16      emrs0;
+-    UINT16      emrs1;
+-    UINT16      emrs1Wr;
+-    UINT16      emrs2;
+-    UINT16      emrs3;
+-    UINT16      emrs4;
+-    UINT16      emrs5;
+-    UINT16      emrs5Wr;
+-    UINT16      emrs6;
+-    UINT16      emrs7;
+-    UINT8       phy_rddata_set;
+-    UINT8       phyif_tim_rdcs;
+-    UINT8       phyif_tim_rden;
+-    UINT8       phyif_tim_wden;
+-    UINT8       phyif_tim_wdda;
+-    UINT8       phyif_tim_wdcs;
+-    UINT8       per_cs_training_en;
+-    UINT32      phyRdDataEnIeDly;
+-    UINT32      phyPadCalConfig;
+-    UINT32      phyDqsFallRiseDelay;
+-    UINT32      ddrcCfgDfiLat0;
+-    UINT32      ddrcCfgDfiLat1;
+-    UINT32      parityLatency;
+-    UINT32      dimm_parity_en;
+-    DDRC_TIMING ddrcTiming;
+-    DDR_DIMM    Dimm[MAX_DIMM];
+-    MARGIN_RESULT sMargin;
+-}DDR_CHANNEL;
+-
+-typedef struct _NVRAM_RANK{
++typedef struct _NVRAM_RANK_DATA {
+     UINT16      MR0;
+     UINT16      MR1;
+     UINT16      MR2;
+@@ -273,15 +67,15 @@ typedef struct _NVRAM_RANK{
+     UINT16      MR4;
+     UINT16      MR5;
+     UINT16      MR6[9];
+-}NVRAM_RANK;
++} NVRAM_RANK_DATA;
+ 
+-typedef struct _NVRAM_DIMM{
+-    NVRAM_RANK      Rank[MAX_RANK_DIMM];
+-}NVRAM_DIMM;
++typedef struct _NVRAM_DIMM_DATA {
++    NVRAM_RANK_DATA      Rank[MAX_RANK_DIMM];
++} NVRAM_DIMM_DATA;
+ 
+ 
+-typedef struct _NVRAM_CHANNEL{
+-    NVRAM_DIMM      Dimm[MAX_DIMM];
++typedef struct _NVRAM_CHANNEL_DATA {
++    NVRAM_DIMM_DATA      Dimm[MAX_DIMM];
+     UINT32          DDRC_CFG_ECC;
+     UINT32          DDRC_CFG_WORKMODE;
+     UINT32          DDRC_CFG_WORKMODE1;
+@@ -325,94 +119,70 @@ typedef struct _NVRAM_CHANNEL{
+     UINT32          DDRC_CFG_DDRPHY;
+     UINT32          Config[24];
+     BOOLEAN         Status;
+-}NVRAM_CHANNEL;
++} NVRAM_CHANNEL_DATA;
+ 
+-typedef struct _NVRAM{
+-    UINT32          NvramCrc;
+-    NVRAM_CHANNEL   Channel[MAX_SOCKET][MAX_CHANNEL];
+-    UINT32          DdrFreqIdx;
++typedef struct _NVRAM_DATA {
++    UINT32              NvramCrc;
++    NVRAM_CHANNEL_DATA  Channel[MAX_SOCKET][MAX_CHANNEL];
++    UINT32              DdrFreqIdx;
+ 
+-}NVRAM;
++} NVRAM_DATA;
+ 
+-typedef struct _MEMORY{
+-    UINT8           Config0;
+-    UINT8           marginTest;
+-    UINT8           Config1[5];
+-    UINT8           ErrorBypass; //register of spd mirror mode
+-    UINT32          Config2;
+-}MEMORY;
++struct DDR_RANK_DATA {
++    BOOLEAN     Enabled;
++};
+ 
+-typedef struct _NUMAINFO{
++typedef struct _DDR_DIMM_DATA {
++    BOOLEAN         Enabled;
++    UINT8           DramType;           //Byte 2
++    UINT8           ModuleType;         //Byte 3
++    UINT8           BankNum;            //Byte 4
++    UINT8           RowBits;            //Byte 5
++    UINT8           ColBits;            //Byte 5
++    UINT8           SpdVdd;             //Byte 6
++    UINT8           RankNum;            //Byte 7
++    UINT8           PrimaryBusWidth;    //Byte 8
++    UINT8           ExtensionBusWidth;  //Byte 8
++    UINT8           SpdModPart[SPD_MODULE_PART];                // Module Part Number
++    UINT8           SpdModPartDDR4[SPD_MODULE_PART_DDR4];       // Module Part Number DDR4
++    UINT16          SpdMMfgId;              // Module Mfg Id from SPD
++    UINT32          SpdSerialNum;
++    UINT32          RankSize;
++    UINT16          DimmSize;
++    UINT16          DimmSpeed;
++    UINT16          SpdMMDate;
++    struct DDR_RANK_DATA    Rank[MAX_RANK_DIMM];
++} DDR_DIMM_DATA;
++
++typedef struct _DDR_CHANNEL_DATA {
++    BOOLEAN         Enabled;
++    DDR_DIMM_DATA   Dimm[MAX_DIMM];
++    UINT8           CurrentDimmNum;
++} DDR_CHANNEL_DATA;
++
++typedef struct _MEMORY_DATA {
++    UINT8           RascBypass;
++} MEMORY_DATA;
++
++typedef struct _NUMAINFO_DATA {
+     UINT8           NodeId;
+     UINT64          Base;
+     UINT64          Length;
+     UINT32          ScclInterleaveEn;
+-}NUMAINFO;
+-
+-
+-typedef struct _GBL_DATA
+-{
+-    DDR_CHANNEL Channel[MAX_SOCKET][MAX_CHANNEL];
+-    UINT8       DramType;
+-    UINT8       CurrentDimmNum;
+-    UINT8       CurrentRankNum;
+-    UINT8       MaxSPCNum;
+-    UINT32      Freq;
+-    UINT32      SpdTckMtb;
+-    UINT32      SpdTckFtb;
+-    UINT32      SpdTck;
+-    UINT32      Tck;
+-    UINT32      DdrFreqIdx;
+-    UINT32      DevParaFreqIdx; //Maximum frequency of DDR device
+-    UINT32      MemSize;
+-    UINT32      EccEn;
+-
+-    BOOLEAN     SetupExist;
+-    UINT8       warmReset;
+-    UINT8       needColdReset;
+-
+-    UINT8       cl;
+-    UINT8       cwl;
+-    UINT8       pl;
+-    UINT8       wr_pre_2t_en;
+-    UINT8       rd_pre_2t_en;
+-    UINT8       cmd_2t_en;
+-    UINT8       ddr4_parity_en;
+-    UINT8       wr_dbi_en;
+-    UINT8       wr_dm_en;
+-    UINT8       ddr4_crc_en;
+-    UINT16      emrs0;
+-    UINT16      emrs1;
+-    UINT16      emrs2;
+-    UINT16      emrs3;
+-    UINT16      emrs4;
+-    UINT16      emrs5;
+-    UINT16      emrs6;
+-    UINT16      emrs7;
+-    UINT8       phy_rddata_set;
+-    UINT8       phyif_tim_rdcs;
+-    UINT8       phyif_tim_rden;
+-    UINT8       phyif_tim_wden;
+-    UINT8       phyif_tim_wdda;
+-    UINT8       phyif_tim_wdcs;
+-    UINT8       dimm_trtr;
+-    UINT8       dimm_twtw;
+-    UINT8       rnk_trtr;
+-    UINT8       rnk_twtw;
+-    UINT8       rnk_trtw;
+-    UINT8       rnk_twtr;
+-    UINT8       per_cs_training_en;
+-    UINT8       scale;
+-    UINT8       ddrFreq;
+-    UINT8       debugNeed;
+-    UINT8       ddr3OdtEnable;
+-    double      fprd;
+-    BOOLEAN     chipIsEc;
+-    NVRAM       nvram;
+-    MEMORY      mem;
+-    NUMAINFO    NumaInfo[MAX_SOCKET][MAX_NUM_PER_TYPE];
+-
+-}GBL_DATA, *pGBL_DATA;
++} NUMAINFO_DATA;
++
++
++typedef struct _GBL_DATA_INTERFACE {
++    DDR_CHANNEL_DATA        Channel[MAX_SOCKET][MAX_CHANNEL];
++    UINT32                  DdrFreqIdx;
++    UINT32                  Freq;
++    UINT32                  EccEn;
++    UINT32                  MemSize;
++    BOOLEAN                 SetupExist;
++    NVRAM_DATA              NvRamData;
++    MEMORY_DATA             MemData;
++    NUMAINFO_DATA           NumaInfo[MAX_SOCKET][MAX_NUM_PER_TYPE];
++} GBL_INTERFACE;
+ 
+ typedef union {
+     struct {
+diff --git a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c
+index 7d06fccc2b..f5869841dc 100644
+--- a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c
++++ b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c
+@@ -56,7 +56,7 @@ UpdateSrat (
+   UINT8               Skt = 0;
+   UINTN               Index = 0;
+   VOID                *HobList;
+-  GBL_DATA            *Gbl_Data;
++  GBL_INTERFACE       *Gbl_Data;
+   UINTN               Base;
+   UINTN               Size;
+   UINT8               NodeId;
+@@ -69,7 +69,7 @@ UpdateSrat (
+   if (HobList == NULL) {
+     return EFI_UNSUPPORTED;
+   }
+-  Gbl_Data = (GBL_DATA*)GetNextGuidHob(&gHisiEfiMemoryMapGuid, HobList);
++  Gbl_Data = (GBL_INTERFACE*)GetNextGuidHob(&gHisiEfiMemoryMapGuid, HobList);
+   if (Gbl_Data == NULL) {
+     DEBUG((DEBUG_ERROR, "Get next Guid HOb fail.\n"));
+     return EFI_NOT_FOUND;
+diff --git a/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.c b/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.c
+index da714c9e22..7d3005eb14 100644
+--- a/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.c
++++ b/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.c
+@@ -45,7 +45,7 @@ SmbiosGetManufacturer (
+ 
+ VOID
+ SmbiosGetPartNumber (
+-  IN pGBL_DATA          pGblData,
++  IN GBL_INTERFACE      *pGblData,
+   IN UINT8              Skt,
+   IN UINT8              Ch,
+   IN UINT8              Dimm,
+@@ -78,7 +78,7 @@ SmbiosGetPartNumber (
+ 
+ VOID
+ SmbiosGetSerialNumber (
+-  IN pGBL_DATA          pGblData,
++  IN GBL_INTERFACE      *pGblData,
+   IN UINT8              Skt,
+   IN UINT8              Ch,
+   IN UINT8              Dimm,
+@@ -96,14 +96,14 @@ SmbiosGetSerialNumber (
+ 
+ BOOLEAN
+ IsDimmPresent (
+-  IN  pGBL_DATA          pGblData,
++  IN  GBL_INTERFACE      *pGblData,
+   IN  UINT8              Skt,
+   IN  UINT8              Ch,
+   IN  UINT8              Dimm
+ )
+ {
+-    if (pGblData->Channel[Skt][Ch].Status == FALSE ||
+-          pGblData->Channel[Skt][Ch].Dimm[Dimm].Status == FALSE)
++    if (pGblData->Channel[Skt][Ch].Enabled == FALSE ||
++        pGblData->Channel[Skt][Ch].Dimm[Dimm].Enabled == FALSE)
+     {
+         return FALSE;
+     }
+@@ -115,7 +115,7 @@ IsDimmPresent (
+ 
+ UINT8
+ SmbiosGetMemoryType (
+-  IN  pGBL_DATA          pGblData,
++  IN  GBL_INTERFACE      *pGblData,
+   IN  UINT8              Skt,
+   IN  UINT8              Ch,
+   IN  UINT8              Dimm
+@@ -146,7 +146,7 @@ SmbiosGetMemoryType (
+ 
+ VOID
+ SmbiosGetTypeDetail (
+-  IN  pGBL_DATA             pGblData,
++  IN  GBL_INTERFACE         *pGblData,
+   IN  UINT8                 Skt,
+   IN  UINT8                 Ch,
+   IN  UINT8                 Dimm,
+@@ -186,7 +186,7 @@ SmbiosGetTypeDetail (
+ 
+ VOID
+ SmbiosGetDimmVoltageInfo (
+-  IN     pGBL_DATA             pGblData,
++  IN     GBL_INTERFACE         *pGblData,
+   IN     UINT8                 Skt,
+   IN     UINT8                 Ch,
+   IN     UINT8                 Dimm,
+@@ -281,7 +281,7 @@ SmbiosGetPartitionWidth (
+ 
+ EFI_STATUS
+ SmbiosAddType16Table (
+-  IN  pGBL_DATA          pGblData,
++  IN  GBL_INTERFACE      *pGblData,
+   OUT EFI_SMBIOS_HANDLE  *MemArraySmbiosHandle
+   )
+ {
+@@ -345,7 +345,7 @@ SmbiosAddType16Table (
+ 
+ EFI_STATUS
+ SmbiosAddType19Table (
+-  IN pGBL_DATA          pGblData,
++  IN GBL_INTERFACE      *pGblData,
+   IN EFI_SMBIOS_HANDLE  MemArraySmbiosHandle
+   )
+ {
+@@ -397,7 +397,7 @@ SmbiosAddType19Table (
+ 
+ EFI_STATUS
+ SmbiosAddType17Table (
+-  IN pGBL_DATA          pGblData,
++  IN GBL_INTERFACE      *pGblData,
+   IN UINT8              Skt,
+   IN UINT8              Ch,
+   IN UINT8              Dimm,
+@@ -692,7 +692,7 @@ MemorySubClassEntryPoint(
+     EFI_STATUS                      Status;
+     EFI_SMBIOS_PROTOCOL             *Smbios;
+     EFI_HOB_GUID_TYPE               *GuidHob;
+-    pGBL_DATA                       pGblData;
++    GBL_INTERFACE                   *pGblData;
+     EFI_SMBIOS_HANDLE               MemArraySmbiosHandle;
+     UINT8                           Skt, Ch, Dimm;
+ 
+@@ -702,7 +702,7 @@ MemorySubClassEntryPoint(
+         DEBUG((EFI_D_ERROR, "Could not get MemoryMap Guid hob.  %r\n"));
+         return EFI_NOT_FOUND;
+     }
+-    pGblData = (pGBL_DATA) GET_GUID_HOB_DATA(GuidHob);
++    pGblData = (GBL_INTERFACE*) GET_GUID_HOB_DATA(GuidHob);
+ 
+     //
+     // Locate dependent protocols
+-- 
+2.17.0
+
diff --git a/v2/v2-0002-Silicon-Hisilicon-Separate-PlatformArch.h.patch b/v2/v2-0002-Silicon-Hisilicon-Separate-PlatformArch.h.patch
new file mode 100644
index 0000000000..aa06d87e4e
--- /dev/null
+++ b/v2/v2-0002-Silicon-Hisilicon-Separate-PlatformArch.h.patch
@@ -0,0 +1,64 @@ 
+From 8f222866142663d081addf168aa3b10ea42566c4 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Fri, 20 Jul 2018 17:57:11 +0800
+Subject: [PATCH edk2-platforms v2 02/43] Silicon/Hisilicon: Separate
+ PlatformArch.h
+
+As the macro of PlatformArch.h is platform specific, so separate
+PlatformArch.h to Hi1610,Hi1616 for unifying D0x.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Silicon/Hisilicon/{ => Hi1610}/Include/PlatformArch.h |  0
+ Silicon/Hisilicon/Hi1616/Include/PlatformArch.h       | 35 ++++++++++++++++++++
+ 2 files changed, 35 insertions(+)
+
+diff --git a/Silicon/Hisilicon/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
+similarity index 100%
+rename from Silicon/Hisilicon/Include/PlatformArch.h
+rename to Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
+diff --git a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
+new file mode 100644
+index 0000000000..bf0994a5e9
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
+@@ -0,0 +1,35 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++
++
++#ifndef _PLATFORM_ARCH_H_
++#define _PLATFORM_ARCH_H_
++
++#define MAX_SOCKET      2
++#define MAX_DIE         4
++#define MAX_DDRC        2
++#define MAX_NODE        (MAX_SOCKET * MAX_DIE)
++#define MAX_CHANNEL     4
++#define MAX_DIMM        3
++#define MAX_RANK_CH     12
++#define MAX_RANK_DIMM   4
++// Max NUMA node number for each node type
++#define MAX_NUM_PER_TYPE 8
++
++#define S1_BASE               0x40000000000
++
++#endif
++
+-- 
+2.17.0
+
diff --git a/v2/v2-0003-Silicon-Hisilicon-Acpi-Move-some-macro-to-Platfor.patch b/v2/v2-0003-Silicon-Hisilicon-Acpi-Move-some-macro-to-Platfor.patch
new file mode 100644
index 0000000000..0dabbeae39
--- /dev/null
+++ b/v2/v2-0003-Silicon-Hisilicon-Acpi-Move-some-macro-to-Platfor.patch
@@ -0,0 +1,168 @@ 
+From 443c705936b3526f80994d8220a7c51b10b38420 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Sat, 11 Aug 2018 15:14:10 +0800
+Subject: [PATCH edk2-platforms v2 03/43] Silicon/Hisilicon/Acpi: Move some
+ macro to PlatformArch.h
+
+ARM_ACPI_HEADER is used by a unify module in HwPkg,
+so move some macro to PlatformArch.h for unify D0x.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h | 27 +++-----------------
+ Silicon/Hisilicon/Hi1610/Include/PlatformArch.h            | 24 +++++++++++++++++
+ Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h    | 24 +----------------
+ Silicon/Hisilicon/Hi1616/Include/PlatformArch.h            | 23 +++++++++++++++++
+ 4 files changed, 51 insertions(+), 47 deletions(-)
+
+diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h
+index 5a95b02055..28546bea99 100644
+--- a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h
++++ b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h
+@@ -1,8 +1,8 @@
+ /** @file
+ *
+ *  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+-*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+-*  Copyright (c) 2015, Linaro Limited. All rights reserved.
++*  Copyright (c) 2015-2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2015-2018, Linaro Limited. All rights reserved.
+ *
+ *  This program and the accompanying materials
+ *  are licensed and made available under the terms and conditions of the BSD License
+@@ -20,28 +20,7 @@
+ #ifndef _HI1610_PLATFORM_H_
+ #define _HI1610_PLATFORM_H_
+ 
+-//
+-// ACPI table information used to initialize tables.
+-//
+-#define EFI_ACPI_ARM_OEM_ID           'H','I','S','I',' ',' '   // OEMID 6 bytes long
+-#define EFI_ACPI_ARM_OEM_TABLE_ID     SIGNATURE_64('H','I','P','0','6',' ',' ',' ') // OEM table id 8 bytes long
+-#define EFI_ACPI_ARM_OEM_REVISION     0x00000000
+-#define EFI_ACPI_ARM_CREATOR_ID       SIGNATURE_32('I','N','T','L')
+-#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
+-
+-// A macro to initialise the common header part of EFI ACPI tables as defined by
+-// EFI_ACPI_DESCRIPTION_HEADER structure.
+-#define ARM_ACPI_HEADER(Signature, Type, Revision) {              \
+-    Signature,                      /* UINT32  Signature */       \
+-    sizeof (Type),                  /* UINT32  Length */          \
+-    Revision,                       /* UINT8   Revision */        \
+-    0,                              /* UINT8   Checksum */        \
+-    { EFI_ACPI_ARM_OEM_ID },        /* UINT8   OemId[6] */        \
+-    EFI_ACPI_ARM_OEM_TABLE_ID,      /* UINT64  OemTableId */      \
+-    EFI_ACPI_ARM_OEM_REVISION,      /* UINT32  OemRevision */     \
+-    EFI_ACPI_ARM_CREATOR_ID,        /* UINT32  CreatorId */       \
+-    EFI_ACPI_ARM_CREATOR_REVISION   /* UINT32  CreatorRevision */ \
+-  }
++#include <../Include/PlatformArch.h>
+ 
+ #define HI1610_WATCHDOG_COUNT  2
+ 
+diff --git a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
+index 45995c5893..8e5913447c 100644
+--- a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
++++ b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
+@@ -31,5 +31,29 @@
+ 
+ #define S1_BASE               0x40000000000
+ 
++
++//
++// ACPI table information used to initialize tables.
++//
++#define EFI_ACPI_ARM_OEM_ID           'H','I','S','I',' ',' '   // OEMID 6 bytes long
++#define EFI_ACPI_ARM_OEM_TABLE_ID     SIGNATURE_64 ('H','I','P','0','6',' ',' ',' ') // OEM table id 8 bytes long
++#define EFI_ACPI_ARM_OEM_REVISION     0x00000000
++#define EFI_ACPI_ARM_CREATOR_ID       SIGNATURE_32 ('I','N','T','L')
++#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
++
++// A macro to initialise the common header part of EFI ACPI tables as defined by
++// EFI_ACPI_DESCRIPTION_HEADER structure.
++#define ARM_ACPI_HEADER(Signature, Type, Revision) {            \
++  Signature,                      /* UINT32  Signature */       \
++  sizeof (Type),                  /* UINT32  Length */          \
++  Revision,                       /* UINT8   Revision */        \
++  0,                              /* UINT8   Checksum */        \
++  { EFI_ACPI_ARM_OEM_ID },        /* UINT8   OemId[6] */        \
++  EFI_ACPI_ARM_OEM_TABLE_ID,      /* UINT64  OemTableId */      \
++  EFI_ACPI_ARM_OEM_REVISION,      /* UINT32  OemRevision */     \
++  EFI_ACPI_ARM_CREATOR_ID,        /* UINT32  CreatorId */       \
++  EFI_ACPI_ARM_CREATOR_REVISION   /* UINT32  CreatorRevision */ \
++  }
++
+ #endif
+ 
+diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
+index ad73aa2668..04f9e34a14 100644
+--- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
++++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
+@@ -21,29 +21,7 @@
+ #define _HI1610_PLATFORM_H_
+ 
+ #include <IndustryStandard/Acpi.h>
+-
+-//
+-// ACPI table information used to initialize tables.
+-//
+-#define EFI_ACPI_ARM_OEM_ID           'H','I','S','I',' ',' '   // OEMID 6 bytes long
+-#define EFI_ACPI_ARM_OEM_TABLE_ID     SIGNATURE_64('H','I','P','0','7',' ',' ',' ') // OEM table id 8 bytes long
+-#define EFI_ACPI_ARM_OEM_REVISION     0x00000000
+-#define EFI_ACPI_ARM_CREATOR_ID       SIGNATURE_32('I','N','T','L')
+-#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
+-
+-// A macro to initialise the common header part of EFI ACPI tables as defined by
+-// EFI_ACPI_DESCRIPTION_HEADER structure.
+-#define ARM_ACPI_HEADER(Signature, Type, Revision) {              \
+-    Signature,                      /* UINT32  Signature */       \
+-    sizeof (Type),                  /* UINT32  Length */          \
+-    Revision,                       /* UINT8   Revision */        \
+-    0,                              /* UINT8   Checksum */        \
+-    { EFI_ACPI_ARM_OEM_ID },        /* UINT8   OemId[6] */        \
+-    EFI_ACPI_ARM_OEM_TABLE_ID,      /* UINT64  OemTableId */      \
+-    EFI_ACPI_ARM_OEM_REVISION,      /* UINT32  OemRevision */     \
+-    EFI_ACPI_ARM_CREATOR_ID,        /* UINT32  CreatorId */       \
+-    EFI_ACPI_ARM_CREATOR_REVISION   /* UINT32  CreatorRevision */ \
+-  }
++#include <../Include/PlatformArch.h>
+ 
+ #define HI1616_WATCHDOG_COUNT  2
+ #define HI1616_GIC_STRUCTURE_COUNT  64
+diff --git a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
+index bf0994a5e9..24167d1633 100644
+--- a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
++++ b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
+@@ -31,5 +31,28 @@
+ 
+ #define S1_BASE               0x40000000000
+ 
++//
++// ACPI table information used to initialize tables.
++//
++#define EFI_ACPI_ARM_OEM_ID           'H','I','S','I',' ',' '   // OEMID 6 bytes long
++#define EFI_ACPI_ARM_OEM_TABLE_ID     SIGNATURE_64 ('H','I','P','0','7',' ',' ',' ') // OEM table id 8 bytes long
++#define EFI_ACPI_ARM_OEM_REVISION     0x00000000
++#define EFI_ACPI_ARM_CREATOR_ID       SIGNATURE_32 ('I','N','T','L')
++#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
++
++// A macro to initialise the common header part of EFI ACPI tables as defined by
++// EFI_ACPI_DESCRIPTION_HEADER structure.
++#define ARM_ACPI_HEADER(Signature, Type, Revision) {            \
++  Signature,                      /* UINT32  Signature */       \
++  sizeof (Type),                  /* UINT32  Length */          \
++  Revision,                       /* UINT8   Revision */        \
++  0,                              /* UINT8   Checksum */        \
++  { EFI_ACPI_ARM_OEM_ID },        /* UINT8   OemId[6] */        \
++  EFI_ACPI_ARM_OEM_TABLE_ID,      /* UINT64  OemTableId */      \
++  EFI_ACPI_ARM_OEM_REVISION,      /* UINT32  OemRevision */     \
++  EFI_ACPI_ARM_CREATOR_ID,        /* UINT32  CreatorId */       \
++  EFI_ACPI_ARM_CREATOR_REVISION   /* UINT32  CreatorRevision */ \
++  }
++
+ #endif
+ 
+-- 
+2.17.0
+
diff --git a/v2/v2-0004-Silicon-Hisilicon-D0x-Move-dimm-size-definition-t.patch b/v2/v2-0004-Silicon-Hisilicon-D0x-Move-dimm-size-definition-t.patch
new file mode 100644
index 0000000000..2176607cfb
--- /dev/null
+++ b/v2/v2-0004-Silicon-Hisilicon-D0x-Move-dimm-size-definition-t.patch
@@ -0,0 +1,57 @@ 
+From 62503a986ac8cc1222edfff18f6d611c9091e915 Mon Sep 17 00:00:00 2001
+From: Sun Yuanchen <sunyuanchen@huawei.com>
+Date: Fri, 29 Jun 2018 15:16:39 +0800
+Subject: [PATCH edk2-platforms v2 04/43] Silicon/Hisilicon/D0x: Move dimm size
+ definition to PlatformArch.h
+
+Unify MemorySubClassDxe by Moving dimm size macro definition
+to PlatformArch.h
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Sun Yuanchen <sunyuanchen@huawei.com>
+---
+ Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.h | 2 --
+ Silicon/Hisilicon/Hi1610/Include/PlatformArch.h                     | 1 +
+ Silicon/Hisilicon/Hi1616/Include/PlatformArch.h                     | 1 +
+ 3 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.h b/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.h
+index c35ce39d61..0c201b4870 100644
+--- a/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.h
++++ b/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.h
+@@ -44,8 +44,6 @@
+ 
+ extern UINT8 MemorySubClassStrings[];
+ 
+-#define MAX_DIMM_SIZE       32  // In GB
+-
+ struct SPD_JEDEC_MANUFACTURER
+ {
+     UINT8  MfgIdLSB;
+diff --git a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
+index 8e5913447c..2ff076901e 100644
+--- a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
++++ b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
+@@ -26,6 +26,7 @@
+ #define MAX_DIMM        3
+ #define MAX_RANK_CH     12
+ #define MAX_RANK_DIMM   4
++#define MAX_DIMM_SIZE   32  // In GB
+ // Max NUMA node number for each node type
+ #define MAX_NUM_PER_TYPE 8
+ 
+diff --git a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
+index 24167d1633..60a60593be 100644
+--- a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
++++ b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
+@@ -26,6 +26,7 @@
+ #define MAX_DIMM        3
+ #define MAX_RANK_CH     12
+ #define MAX_RANK_DIMM   4
++#define MAX_DIMM_SIZE   32  // In GB
+ // Max NUMA node number for each node type
+ #define MAX_NUM_PER_TYPE 8
+ 
+-- 
+2.17.0
+
diff --git a/v2/v2-0005-Silicon-Hisilicon-D0x-Move-RAS-macro-to-PlatformA.patch b/v2/v2-0005-Silicon-Hisilicon-D0x-Move-RAS-macro-to-PlatformA.patch
new file mode 100644
index 0000000000..c4285bacab
--- /dev/null
+++ b/v2/v2-0005-Silicon-Hisilicon-D0x-Move-RAS-macro-to-PlatformA.patch
@@ -0,0 +1,68 @@ 
+From a36aa321b03a58b090f1cdbf54363a0f0bca40e6 Mon Sep 17 00:00:00 2001
+From: Sun Yuanchen <sunyuanchen@huawei.com>
+Date: Tue, 3 Jul 2018 18:14:59 +0800
+Subject: [PATCH edk2-platforms v2 05/43] Silicon/Hisilicon/D0x: Move RAS macro
+ to PlatformArch.h
+
+Move some RAS macros definition to PlatformArch.h for
+unifying D0x
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Sun Yuanchen <sunyuanchen@huawei.com>
+---
+ Silicon/Hisilicon/Hi1610/Include/PlatformArch.h |  9 +++++++--
+ Silicon/Hisilicon/Hi1616/Include/PlatformArch.h | 12 ++++++++++++
+ 2 files changed, 19 insertions(+), 2 deletions(-)
+
+diff --git a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
+index 2ff076901e..f39ae0748c 100644
+--- a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
++++ b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
+@@ -1,7 +1,7 @@
+ /** @file
+ *
+-*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+-*  Copyright (c) 2015, Linaro Limited. All rights reserved.
++*  Copyright (c) 2015 - 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2015 - 2018, Linaro Limited. All rights reserved.
+ *
+ *  This program and the accompanying materials
+ *  are licensed and made available under the terms and conditions of the BSD License
+@@ -32,6 +32,11 @@
+ 
+ #define S1_BASE               0x40000000000
+ 
++#define RASC_BASE                (0x5000)
++/* configuration register for Rank statistical information */
++#define RASC_CFG_INFOIDX_REG     (RASC_BASE + 0x5C)
++/* configuration register for Sparing level */
++#define RASC_CFG_SPLVL_REG       (RASC_BASE + 0xB8)
+ 
+ //
+ // ACPI table information used to initialize tables.
+diff --git a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
+index 60a60593be..e02e4bdabd 100644
+--- a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
++++ b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
+@@ -30,6 +30,18 @@
+ // Max NUMA node number for each node type
+ #define MAX_NUM_PER_TYPE 8
+ 
++#define RASC_BASE                (0x5000)
++/* configuration register for Rank statistical information */
++#define RASC_CFG_INFOIDX_REG     (RASC_BASE + 0x5C)
++/* configuration register for Sparing level */
++#define RASC_CFG_SPLVL_REG       (RASC_BASE + 0xB8)
++
++// for acpi
++#define NODE_IN_SOCKET                                  2
++#define CORE_NUM_PER_SOCKET                             32
++#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT        10
++#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT       8
++
+ #define S1_BASE               0x40000000000
+ 
+ //
+-- 
+2.17.0
+
diff --git a/v2/v2-0006-Hisilicon-D0x-Move-CustomData.Fv-to-common-path-o.patch b/v2/v2-0006-Hisilicon-D0x-Move-CustomData.Fv-to-common-path-o.patch
new file mode 100644
index 0000000000..04b2bb9a35
--- /dev/null
+++ b/v2/v2-0006-Hisilicon-D0x-Move-CustomData.Fv-to-common-path-o.patch
@@ -0,0 +1,45 @@ 
+From b9b60c7ac88cad3d1d568c80b72ae2c0cc31caaa Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Sun, 5 Aug 2018 21:58:57 +0800
+Subject: [PATCH edk2-platforms v2 06/43] Hisilicon/D0x: Move CustomData.Fv to
+ common path of Hisilicon
+
+The CustomData.Fv is moved to Platform/Hisilicon in edk2-non-osi,
+so update D0x fdf to reflect this.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Platform/Hisilicon/D03/D03.fdf | 2 +-
+ Platform/Hisilicon/D05/D05.fdf | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf
+index cf11aeccc8..4591f7b5b1 100644
+--- a/Platform/Hisilicon/D03/D03.fdf
++++ b/Platform/Hisilicon/D03/D03.fdf
+@@ -113,7 +113,7 @@ DATA = {
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ 
+ 0x002F0000|0x00010000
+-FILE = Platform/Hisilicon/D03/CustomData.Fv
++FILE = Platform/Hisilicon/D0x-CustomData.Fv
+ 
+ ################################################################################
+ #
+diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
+index 701804360e..6227607ffe 100644
+--- a/Platform/Hisilicon/D05/D05.fdf
++++ b/Platform/Hisilicon/D05/D05.fdf
+@@ -113,7 +113,7 @@ DATA = {
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ 
+ 0x002F0000|0x00010000
+-FILE = Platform/Hisilicon/D03/CustomData.Fv
++FILE = Platform/Hisilicon/D0x-CustomData.Fv
+ 
+ ################################################################################
+ #
+-- 
+2.17.0
+
diff --git a/v2/v2-0007-Hisilicon-D0x-Move-IpmiCmdLib-to-common-path-of-H.patch b/v2/v2-0007-Hisilicon-D0x-Move-IpmiCmdLib-to-common-path-of-H.patch
new file mode 100644
index 0000000000..e9a44875e5
--- /dev/null
+++ b/v2/v2-0007-Hisilicon-D0x-Move-IpmiCmdLib-to-common-path-of-H.patch
@@ -0,0 +1,45 @@ 
+From 28d55a316e744b645be9c123d63a1f94880498c9 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Tue, 7 Aug 2018 23:01:10 +0800
+Subject: [PATCH edk2-platforms v2 07/43] Hisilicon/D0x: Move IpmiCmdLib to
+ common path of Hisilicon
+
+The IpmiCmdLib is moved to Silicon/Hisilicon in edk2-non-osi,
+so update D0x dsc to reflect this.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Platform/Hisilicon/D03/D03.dsc | 2 +-
+ Platform/Hisilicon/D05/D05.dsc | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc
+index 38548a0f23..c12790ba59 100644
+--- a/Platform/Hisilicon/D03/D03.dsc
++++ b/Platform/Hisilicon/D03/D03.dsc
+@@ -38,7 +38,7 @@
+   I2CLib|Silicon/Hisilicon/Library/I2CLib/I2CLib.inf
+   TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+ 
+-  IpmiCmdLib|Silicon/Hisilicon/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf
++  IpmiCmdLib|Silicon/Hisilicon/Library/IpmiCmdLib/IpmiCmdLib.inf
+ 
+   NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+   DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
+index f2bbf27639..94d386582e 100644
+--- a/Platform/Hisilicon/D05/D05.dsc
++++ b/Platform/Hisilicon/D05/D05.dsc
+@@ -41,7 +41,7 @@
+   I2CLib|Silicon/Hisilicon/Library/I2CLib/I2CLib.inf
+   TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+ 
+-  IpmiCmdLib|Silicon/Hisilicon/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf
++  IpmiCmdLib|Silicon/Hisilicon/Library/IpmiCmdLib/IpmiCmdLib.inf
+ 
+   NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+   DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+-- 
+2.17.0
+
diff --git a/v2/v2-0008-Hisilicon-D0x-Unify-FlashFvbDxe-driver.patch b/v2/v2-0008-Hisilicon-D0x-Unify-FlashFvbDxe-driver.patch
new file mode 100644
index 0000000000..e40ec75c44
--- /dev/null
+++ b/v2/v2-0008-Hisilicon-D0x-Unify-FlashFvbDxe-driver.patch
@@ -0,0 +1,170 @@ 
+From 88f30696ccd1a22e7cbd776fae01d30bd63a46fb Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Wed, 4 Jul 2018 16:42:31 +0800
+Subject: [PATCH edk2-platforms v2 08/43] Hisilicon/D0x: Unify FlashFvbDxe
+ driver
+
+Add PcdSFCMEM0BaseAddress and switch three 32-bit macro
+PcdFlashNvStorage of D05/D03 to 64-bit for unifying FlashFvbDxe
+driver.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Platform/Hisilicon/D03/D03.fdf                        |  6 +++---
+ Platform/Hisilicon/D05/D05.fdf                        |  6 +++---
+ Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf |  7 ++++---
+ Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c   | 22 ++++++++++----------
+ 4 files changed, 21 insertions(+), 20 deletions(-)
+
+diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf
+index 4591f7b5b1..b23765020d 100644
+--- a/Platform/Hisilicon/D03/D03.fdf
++++ b/Platform/Hisilicon/D03/D03.fdf
+@@ -69,7 +69,7 @@ FILE = Platform/Hisilicon/D03/bl1.bin
+ FILE = Platform/Hisilicon/D03/fip.bin
+ 
+ 0x002D0000|0x0000E000
+-gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
++gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ DATA = {
+   ## This is the EFI_FIRMWARE_VOLUME_HEADER
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+@@ -97,7 +97,7 @@ DATA = {
+ }
+ 
+ 0x002DE000|0x00002000
+-gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
++gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+ #NV_FTW_WORKING
+ DATA = {
+   # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid          =
+@@ -110,7 +110,7 @@ DATA = {
+ }
+ 
+ 0x002E0000|0x00010000
+-gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
++gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ 
+ 0x002F0000|0x00010000
+ FILE = Platform/Hisilicon/D0x-CustomData.Fv
+diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
+index 6227607ffe..6fa5b5e6c8 100644
+--- a/Platform/Hisilicon/D05/D05.fdf
++++ b/Platform/Hisilicon/D05/D05.fdf
+@@ -69,7 +69,7 @@ FILE = Platform/Hisilicon/D05/bl1.bin
+ FILE = Platform/Hisilicon/D05/fip.bin
+ 
+ 0x002D0000|0x0000E000
+-gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
++gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ DATA = {
+   ## This is the EFI_FIRMWARE_VOLUME_HEADER
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+@@ -97,7 +97,7 @@ DATA = {
+ }
+ 
+ 0x002DE000|0x00002000
+-gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
++gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+ #NV_FTW_WORKING
+ DATA = {
+   # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid          =
+@@ -110,7 +110,7 @@ DATA = {
+ }
+ 
+ 0x002E0000|0x00010000
+-gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
++gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ 
+ 0x002F0000|0x00010000
+ FILE = Platform/Hisilicon/D0x-CustomData.Fv
+diff --git a/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf b/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
+index 09ec7ce08b..f8be4741ef 100644
+--- a/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
++++ b/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
+@@ -54,14 +54,15 @@
+   gHisiSpiFlashProtocolGuid
+ 
+ [Pcd.common]
+-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
++  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64
+   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase
++  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64
+   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase
++  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64
+   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ 
+   gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked
++  gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress
+ 
+ [Depex]
+   gHisiSpiFlashProtocolGuid
+diff --git a/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c b/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c
+index 7c6b64c33e..e18cc9e06e 100644
+--- a/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c
++++ b/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c
+@@ -28,8 +28,8 @@ FLASH_DESCRIPTION mFlashDevices[FLASH_DEVICE_COUNT] =
+ {
+     {
+         // UEFI Variable Services non-volatile storage
+-        0xa4000000,
+-        FixedPcdGet32(PcdFlashNvStorageVariableBase),
++        FixedPcdGet64 (PcdSFCMEM0BaseAddress),
++        FixedPcdGet64 (PcdFlashNvStorageVariableBase64),
+         0x20000,
+         SIZE_64KB,
+         {0xCC2CBF29, 0x1498, 0x4CDD, {0x81, 0x71, 0xF8, 0xB6, 0xB4, 0x1D, 0x09, 0x09}}
+@@ -145,8 +145,8 @@ InitializeFvAndVariableStoreHeaders (
+     Headers = AllocateZeroPool(HeadersLength);
+ 
+     // FirmwareVolumeHeader->FvLength is declared to have the Variable area AND the FTW working area AND the FTW Spare contiguous.
+-    ASSERT(PcdGet32(PcdFlashNvStorageVariableBase) + PcdGet32(PcdFlashNvStorageVariableSize) == PcdGet32(PcdFlashNvStorageFtwWorkingBase));
+-    ASSERT(PcdGet32(PcdFlashNvStorageFtwWorkingBase) + PcdGet32(PcdFlashNvStorageFtwWorkingSize) == PcdGet32(PcdFlashNvStorageFtwSpareBase));
++    ASSERT(PcdGet64(PcdFlashNvStorageVariableBase64) + PcdGet32(PcdFlashNvStorageVariableSize) == PcdGet64(PcdFlashNvStorageFtwWorkingBase64));
++    ASSERT(PcdGet64(PcdFlashNvStorageFtwWorkingBase64) + PcdGet32(PcdFlashNvStorageFtwWorkingSize) == PcdGet64(PcdFlashNvStorageFtwSpareBase64));
+ 
+     // Check if the size of the area is at least one block size
+     ASSERT((PcdGet32(PcdFlashNvStorageVariableSize) > 0) && ((UINT32)PcdGet32(PcdFlashNvStorageVariableSize) / Instance->Media.BlockSize > 0));
+@@ -154,9 +154,9 @@ InitializeFvAndVariableStoreHeaders (
+     ASSERT((PcdGet32(PcdFlashNvStorageFtwSpareSize) > 0) && ((UINT32)PcdGet32(PcdFlashNvStorageFtwSpareSize) / Instance->Media.BlockSize > 0));
+ 
+     // Ensure the Variable area Base Addresses are aligned on a block size boundaries
+-    ASSERT((UINT32)PcdGet32(PcdFlashNvStorageVariableBase) % Instance->Media.BlockSize == 0);
+-    ASSERT((UINT32)PcdGet32(PcdFlashNvStorageFtwWorkingBase) % Instance->Media.BlockSize == 0);
+-    ASSERT((UINT32)PcdGet32(PcdFlashNvStorageFtwSpareBase) % Instance->Media.BlockSize == 0);
++    ASSERT((UINT32)PcdGet64(PcdFlashNvStorageVariableBase64) % Instance->Media.BlockSize == 0);
++    ASSERT((UINT32)PcdGet64(PcdFlashNvStorageFtwWorkingBase64) % Instance->Media.BlockSize == 0);
++    ASSERT((UINT32)PcdGet64(PcdFlashNvStorageFtwSpareBase64) % Instance->Media.BlockSize == 0);
+ 
+     //
+     // EFI_FIRMWARE_VOLUME_HEADER
+@@ -855,10 +855,10 @@ FvbInitialize (
+     UINT32      FvbNumLba;
+ 
+     Instance->Initialized = TRUE;
+-    mFlashNvStorageVariableBase = FixedPcdGet32 (PcdFlashNvStorageVariableBase);
++    mFlashNvStorageVariableBase = FixedPcdGet64 (PcdFlashNvStorageVariableBase64);
+ 
+     // Set the index of the first LBA for the FVB
+-    Instance->StartLba = (PcdGet32 (PcdFlashNvStorageVariableBase) - Instance->RegionBaseAddress) / Instance->Media.BlockSize;
++    Instance->StartLba = (PcdGet64 (PcdFlashNvStorageVariableBase64) - Instance->RegionBaseAddress) / Instance->Media.BlockSize;
+ 
+     // Determine if there is a valid header at the beginning of the Flash
+     Status = ValidateFvHeader (Instance);
+@@ -1208,8 +1208,8 @@ FlashFvbInitialize (
+     {
+         // Check if this Flash device contain the variable storage region
+         ContainVariableStorage =
+-            (FlashDevices[Index].RegionBaseAddress <= (UINT32)PcdGet32 (PcdFlashNvStorageVariableBase)) &&
+-            ((UINT32)(PcdGet32 (PcdFlashNvStorageVariableBase) + PcdGet32 (PcdFlashNvStorageVariableSize)) <= FlashDevices[Index].RegionBaseAddress + FlashDevices[Index].Size);
++             (FlashDevices[Index].RegionBaseAddress <= PcdGet64 (PcdFlashNvStorageVariableBase64)) &&
++             ((PcdGet64 (PcdFlashNvStorageVariableBase64) + PcdGet32 (PcdFlashNvStorageVariableSize)) <= FlashDevices[Index].RegionBaseAddress + FlashDevices[Index].Size);
+ 
+         Status = FlashCreateInstance (
+                      FlashDevices[Index].DeviceBaseAddress,
+-- 
+2.17.0
+
diff --git a/v2/v2-0009-Hisilicon-D0X-Rename-the-global-variable-gDS3231R.patch b/v2/v2-0009-Hisilicon-D0X-Rename-the-global-variable-gDS3231R.patch
new file mode 100644
index 0000000000..6dcf3efe16
--- /dev/null
+++ b/v2/v2-0009-Hisilicon-D0X-Rename-the-global-variable-gDS3231R.patch
@@ -0,0 +1,142 @@ 
+From edcaba67c20c15d40ec09fd0f4fc38dc86349cd2 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Fri, 29 Jun 2018 15:33:43 +0800
+Subject: [PATCH edk2-platforms v2 09/43] Hisilicon/D0X: Rename the global
+ variable gDS3231RtcDevice
+
+The global variable gDS3231RtcDevice is used by several
+modules included common module in HwPkg. Renaming it
+with a general name is proper.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Silicon/Hisilicon/Include/Library/OemMiscLib.h                                 | 2 +-
+ Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c | 8 ++++----
+ Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c             | 2 +-
+ Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c                 | 2 +-
+ Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c      | 8 ++++----
+ 5 files changed, 11 insertions(+), 11 deletions(-)
+
+diff --git a/Silicon/Hisilicon/Include/Library/OemMiscLib.h b/Silicon/Hisilicon/Include/Library/OemMiscLib.h
+index 6f18c0fa72..87cb498dd7 100644
+--- a/Silicon/Hisilicon/Include/Library/OemMiscLib.h
++++ b/Silicon/Hisilicon/Include/Library/OemMiscLib.h
+@@ -34,7 +34,7 @@ extern REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX];
+ BOOLEAN OemIsSocketPresent (UINTN Socket);
+ VOID CoreSelectBoot(VOID);
+ VOID OemPcieResetAndOffReset(void);
+-extern I2C_DEVICE gDS3231RtcDevice;
++extern I2C_DEVICE gRtcDevice;
+ 
+ UINTN OemGetSocketNumber(VOID);
+ UINTN OemGetDdrChannel (VOID);
+diff --git a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c
+index 07fa52aa78..f6dbcf6b75 100644
+--- a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c
++++ b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c
+@@ -41,7 +41,7 @@
+ #include <Library/CpldD03.h>
+ #include <Library/CpldIoLib.h>
+ 
+-extern I2C_DEVICE gDS3231RtcDevice;
++extern I2C_DEVICE gRtcDevice;
+ 
+ STATIC BOOLEAN       mDS3231Initialized = FALSE;
+ 
+@@ -117,7 +117,7 @@ InitializeDS3231 (
+   // Prepare the hardware
+   (VOID)IdentifyDS3231();
+ 
+-  (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev));
++  (VOID) CopyMem (&Dev, &gRtcDevice, sizeof(Dev));
+ 
+   Status = I2CInit(Dev.Socket,Dev.Port,Normal);
+   if (EFI_ERROR (Status)) {
+@@ -199,7 +199,7 @@ LibGetTime (
+     }
+   }
+ 
+-  (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev));
++  (VOID) CopyMem (&Dev, &gRtcDevice, sizeof(Dev));
+ 
+   Status |= I2CRead(&Dev,DS3231_REGADDR_MONTH,1,&Temp);
+ 
+@@ -299,7 +299,7 @@ LibSetTime (
+     }
+   }
+ 
+-  (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev));
++  (VOID) CopyMem (&Dev, &gRtcDevice, sizeof(Dev));
+ 
+   Temp = ((Time->Second/10)<<4) | (Time->Second%10);
+   MicroSecondDelay(1000);
+diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c b/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c
+index 66d62895a6..4771cb900c 100644
+--- a/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c
++++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c
+@@ -25,7 +25,7 @@
+ #include <Library/I2CLib.h>
+ #include <Library/HiiLib.h>
+ 
+-I2C_DEVICE gDS3231RtcDevice = {
++I2C_DEVICE gRtcDevice = {
+     .Socket = 0,
+     .Port = 6,
+     .DeviceType = DEVICE_TYPE_SPD,
+diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c b/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c
+index 15a509be5d..ae4c194070 100644
+--- a/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c
++++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c
+@@ -26,7 +26,7 @@
+ #include <Protocol/Smbios.h>
+ 
+ 
+-I2C_DEVICE gDS3231RtcDevice = {
++I2C_DEVICE gRtcDevice = {
+   .Socket = 0,
+   .Port = 4,
+   .DeviceType = DEVICE_TYPE_SPD,
+diff --git a/Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c b/Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c
+index 02d6d7f14d..105eb15635 100644
+--- a/Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c
++++ b/Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c
+@@ -39,7 +39,7 @@
+ #include <Library/I2CLib.h>
+ #include "DS3231RealTimeClock.h"
+ 
+-extern I2C_DEVICE gDS3231RtcDevice;
++extern I2C_DEVICE gRtcDevice;
+ 
+ STATIC BOOLEAN       mDS3231Initialized = FALSE;
+ 
+@@ -67,7 +67,7 @@ InitializeDS3231 (
+   // Prepare the hardware
+   (VOID)IdentifyDS3231();
+ 
+-  (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev));
++  (VOID) CopyMem (&Dev, &gRtcDevice, sizeof(Dev));
+ 
+   Status = I2CInit(Dev.Socket,Dev.Port,Normal);
+   if (EFI_ERROR (Status)) {
+@@ -143,7 +143,7 @@ LibGetTime (
+     }
+   }
+ 
+-  (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev));
++  (VOID) CopyMem (&Dev, &gRtcDevice, sizeof(Dev));
+ 
+ 
+   Status |= I2CRead(&Dev,DS3231_REGADDR_MONTH,1,&Temp);
+@@ -233,7 +233,7 @@ LibSetTime (
+     }
+   }
+ 
+-  (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev));
++  (VOID) CopyMem (&Dev, &gRtcDevice, sizeof(Dev));
+ 
+   Temp = ((Time->Second/10)<<4) | (Time->Second%10);
+   MicroSecondDelay(1000);
+-- 
+2.17.0
+
diff --git a/v2/v2-0010-Hisilicon-D06-Add-several-base-file-for-D06.patch b/v2/v2-0010-Hisilicon-D06-Add-several-base-file-for-D06.patch
new file mode 100644
index 0000000000..66f1b47ff7
--- /dev/null
+++ b/v2/v2-0010-Hisilicon-D06-Add-several-base-file-for-D06.patch
@@ -0,0 +1,1160 @@ 
+From d4e234e7fdabe58f9823bba7b194af03ec9f69e1 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Wed, 13 Jun 2018 20:13:08 +0800
+Subject: [PATCH edk2-platforms v2 10/43] Hisilicon/D06: Add several base file
+ for D06
+
+Add several base head files and add several build
+files for D06.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Platform/Hisilicon/D06/D06.dec                       |  29 ++
+ Platform/Hisilicon/D06/D06.dsc                       | 455 ++++++++++++++++++++
+ Platform/Hisilicon/D06/D06.fdf                       | 351 +++++++++++++++
+ Platform/Hisilicon/D06/Include/Library/CpldD06.h     |  37 ++
+ Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h |  85 ++++
+ Silicon/Hisilicon/Hi1620/Include/PlatformArch.h      |  61 +++
+ Silicon/Hisilicon/Include/Library/OemAddressMapLib.h |   6 +
+ Silicon/Hisilicon/Include/Library/OemNicLib.h        |  57 +++
+ 8 files changed, 1081 insertions(+)
+
+diff --git a/Platform/Hisilicon/D06/D06.dec b/Platform/Hisilicon/D06/D06.dec
+new file mode 100644
+index 0000000000..710f083eee
+--- /dev/null
++++ b/Platform/Hisilicon/D06/D06.dec
+@@ -0,0 +1,29 @@
++#/** @file
++#
++#    Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++#    Copyright (c) 2018, Linaro Limited. All rights reserved.
++#
++#    This program and the accompanying materials
++#    are licensed and made available under the terms and conditions of the BSD License
++#    which accompanies this distribution. The full text of the license may be found at
++#    http://opensource.org/licenses/bsd-license.php
++#
++#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++#
++#**/
++
++#
++# D06 Package
++#
++#
++#
++
++[Defines]
++  DEC_SPECIFICATION              = 0x0001001A
++  PACKAGE_NAME                   = D06Pkg
++  PACKAGE_GUID                   = B46F75D7-3864-450D-86D9-A0346A882232
++  PACKAGE_VERSION                = 0.1
++
++[Includes]
++  Include
+diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
+new file mode 100644
+index 0000000000..d14fce1159
+--- /dev/null
++++ b/Platform/Hisilicon/D06/D06.dsc
+@@ -0,0 +1,455 @@
++#
++#  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
++#  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++#  Copyright (c) 2018, Linaro Limited. All rights reserved.
++#
++#  This program and the accompanying materials
++#  are licensed and made available under the terms and conditions of the BSD License
++#  which accompanies this distribution.  The full text of the license may be found at
++#  http://opensource.org/licenses/bsd-license.php
++#
++#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++#
++#
++
++################################################################################
++#
++# Defines Section - statements that will be processed to create a Makefile.
++#
++################################################################################
++[Defines]
++  PLATFORM_NAME                  = D06
++  PLATFORM_GUID                  = D0D445F1-B2CA-4101-9986-1B23525CBEA6
++  PLATFORM_VERSION               = 0.1
++  DSC_SPECIFICATION              = 0x0001001A
++  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
++  SUPPORTED_ARCHITECTURES        = AARCH64
++  BUILD_TARGETS                  = DEBUG|NOOPT|RELEASE
++  SKUID_IDENTIFIER               = DEFAULT
++  FLASH_DEFINITION               = Platform/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf
++  DEFINE NETWORK_IP6_ENABLE      = FALSE
++  DEFINE HTTP_BOOT_ENABLE        = FALSE
++  DEFINE SECURE_BOOT_ENABLE      = FALSE
++
++!include Silicon/Hisilicon/Hisilicon.dsc.inc
++
++[LibraryClasses.common]
++  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
++  ArmPlatformLib|Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf
++
++
++  I2CLib|Silicon/Hisilicon/Library/I2CLib/I2CLib.inf
++  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
++  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
++  DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
++  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
++  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
++  UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
++  IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
++  OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
++  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
++  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
++  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
++  BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
++  SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
++
++!if $(NETWORK_IP6_ENABLE) == TRUE
++  TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf
++!endif
++
++!if $(HTTP_BOOT_ENABLE) == TRUE
++  HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf
++!endif
++
++  CpldIoLib|Silicon/Hisilicon/Library/CpldIoLib/CpldIoLib.inf
++
++  TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
++
++  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
++  GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
++  BmcConfigBootLib|Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf
++  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
++  SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
++  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
++  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
++  PlatformBootManagerLib|Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
++  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
++  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
++
++  # USB Requirements
++  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
++
++  SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
++!if $(SECURE_BOOT_ENABLE) == TRUE
++  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
++!endif
++  PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
++
++[LibraryClasses.common.SEC]
++  ArmPlatformLib|Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf
++
++
++[LibraryClasses.common.DXE_RUNTIME_DRIVER]
++  I2CLib|Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
++  SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
++
++[BuildOptions]
++  GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/Silicon/Hisilicon/Hi1620/Include
++
++################################################################################
++#
++# Pcd Section - list of all EDK II PCD Entries defined by this Platform
++#
++################################################################################
++
++[PcdsFeatureFlag.common]
++
++  ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
++  #  It could be set FALSE to save size.
++  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
++  gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE
++  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE
++  gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE
++
++[PcdsFixedAtBuild.common]
++  gArmPlatformTokenSpaceGuid.PcdCoreCount|48
++  gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|48
++
++  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
++
++
++  # Stacks for MPCores in Normal World
++  gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0xA0E88000
++  gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x40000
++
++  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
++  gArmTokenSpaceGuid.PcdSystemMemorySize|0x3FC00000
++
++  # Size of the region used by UEFI in permanent memory (Reserved 64MB)
++  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x10000000
++
++  gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|1
++
++  gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x2
++
++  ## Serial Terminal
++  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x94080000
++  gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x400094080000
++  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
++
++  gArmPlatformTokenSpaceGuid.PL011UartClkInHz|200000000
++
++  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
++  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
++  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
++
++  gHisiTokenSpaceGuid.PcdIsMPBoot|1
++  gHisiTokenSpaceGuid.PcdSocketMask|0x3
++  !ifdef $(FIRMWARE_VER)
++    gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"
++  !else
++    gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D06 UEFI RC0 - B308 (V0.38)"
++  !endif
++
++  gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
++
++  gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"0.38"
++
++  gHisiTokenSpaceGuid.PcdSystemProductName|L"D06"
++  gHisiTokenSpaceGuid.PcdSystemVersion|L"VER.A"
++  gHisiTokenSpaceGuid.PcdBaseBoardProductName|L"D06"
++  gHisiTokenSpaceGuid.PcdBaseBoardVersion|L"Estuary"
++
++  gHisiTokenSpaceGuid.PcdCPUInfo|L"Hisilicon 1620"
++
++  # TA
++  gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x80010000
++  gArmTokenSpaceGuid.PcdGicDistributorBase|0xAE000000
++  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0xAE100000
++  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xFE000000
++
++
++
++  #
++  # ARM Architectual Timer Frequency
++  #
++  # Set it to 0 so that the code will read frequency from register and be
++  # adapted to 100M and 50M boards
++  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0
++  gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000
++
++
++  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
++  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
++  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
++  gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x94010000
++  gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8
++
++  gHisiTokenSpaceGuid.PcdCpldBaseAddress|0x80000000
++  gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0x204000000
++
++  gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0x94000000
++
++  ## 2+1
++  gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x1
++
++  gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x40000000
++
++  gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x1000000000
++
++  gHisiTokenSpaceGuid.PcdNORFlashBase|0x80000000
++  gHisiTokenSpaceGuid.PcdNORFlashCachableSize|0x8000000
++
++  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x1
++  gHisiTokenSpaceGuid.PcdMacAddress|0xA47E0000
++
++  # PCIe ECAM Access BaseAddress
++  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xD0000000
++  gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|16
++
++  gHisiTokenSpaceGuid.Pcdsoctype|0x1620
++
++  # SMBIOS 3.0 only
++  #  BIT0 set indicates 32-bit entry point and table are produced.<BR>
++  #  BIT1 set indicates 64-bit entry point and table are produced.<BR>
++  gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2
++
++  #
++  # ACPI Table Version
++  #
++  #   BIT 1 - EFI_ACPI_TABLE_VERSION_1_0B.<BR>
++  #   BIT 2 - EFI_ACPI_TABLE_VERSION_2_0.<BR>
++  #   BIT 3 - EFI_ACPI_TABLE_VERSION_3_0.<BR>
++  #   BIT 4 - EFI_ACPI_TABLE_VERSION_4_0.<BR>
++  #   BIT 5 - EFI_ACPI_TABLE_VERSION_5_0.<BR>
++  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
++
++  gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
++  gArmTokenSpaceGuid.PcdPciIoTranslation|0x0
++
++################################################################################
++#
++# Components Section - list of all EDK II Modules needed by this Platform
++#
++################################################################################
++[Components.common]
++
++  #
++  # SEC
++  #
++
++  #
++  # PEI Phase modules
++  #
++  ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
++  MdeModulePkg/Core/Pei/PeiMain.inf
++  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
++
++  ArmPlatformPkg/PlatformPei/PlatformPeim.inf
++
++  ArmPkg/Drivers/CpuPei/CpuPei.inf
++  IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
++  MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
++  MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
++
++  Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
++
++  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
++    <LibraryClasses>
++      NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
++  }
++
++  #
++  # DXE
++  #
++  MdeModulePkg/Core/Dxe/DxeMain.inf {
++    <LibraryClasses>
++      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
++  }
++  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
++
++
++  #
++  # Architectural Protocols
++  #
++  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
++  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
++
++
++!if $(SECURE_BOOT_ENABLE) == TRUE
++  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf {
++    <LibraryClasses>
++      NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf
++  }
++  SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
++!else
++  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
++!endif
++  Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
++  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
++    <LibraryClasses>
++      NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
++      BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
++  }
++  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
++  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
++
++  MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
++  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
++  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
++    <LibraryClasses>
++      CpldIoLib|Silicon/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf
++  }
++  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
++
++  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
++  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
++  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
++  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
++  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
++
++  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
++
++  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
++
++  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
++
++  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
++  IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
++  #
++  #ACPI
++  #
++  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
++  Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
++
++  Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
++
++  #
++  # Usb Support
++  #
++  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
++  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
++  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
++  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
++  MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
++  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
++
++  #
++  #network
++  #
++  MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
++
++  MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
++  MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
++  MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
++  MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
++  MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
++  MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
++  MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
++!if $(NETWORK_IP6_ENABLE) == TRUE
++  NetworkPkg/Ip6Dxe/Ip6Dxe.inf
++  NetworkPkg/TcpDxe/TcpDxe.inf
++  NetworkPkg/Udp6Dxe/Udp6Dxe.inf
++  NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
++  NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
++  NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
++!else
++  MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
++  MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
++!endif
++  MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
++!if $(HTTP_BOOT_ENABLE) == TRUE
++  NetworkPkg/DnsDxe/DnsDxe.inf
++  NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
++  NetworkPkg/HttpDxe/HttpDxe.inf
++  NetworkPkg/HttpBootDxe/HttpBootDxe.inf
++!endif
++
++  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
++  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
++  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
++  #
++  # FAT filesystem + GPT/MBR partitioning
++  #
++
++  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
++  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
++  FatPkg/EnhancedFatDxe/Fat.inf
++  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
++
++  MdeModulePkg/Application/UiApp/UiApp.inf {
++    <LibraryClasses>
++      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
++      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
++      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
++  }
++  #
++  # Bds
++  #
++  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
++
++  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
++  Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
++  Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
++  Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
++  Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
++
++  #PCIe Support
++  Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf
++  ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
++  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
++    <LibraryClasses>
++      PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
++      PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
++      PciHostBridgeLib|MdeModulePkg/Library/PciHostBridgeLibNull/PciHostBridgeLibNull.inf
++  }
++
++  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
++
++  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
++
++  #
++  # Memory test
++  #
++  MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
++  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
++  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
++  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
++
++  #
++  # UEFI application (Shell Embedded Boot Loader)
++  #
++  ShellPkg/Application/Shell/Shell.inf {
++    <LibraryClasses>
++      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
++      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
++      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
++      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
++      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
++      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
++      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
++      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
++      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
++      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
++      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
++!if $(NETWORK_IP6_ENABLE) == TRUE
++      NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf
++!endif
++
++!if $(INCLUDE_DP) == TRUE
++      NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf
++!endif #$(INCLUDE_DP)
++
++    <PcdsFixedAtBuild>
++      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
++      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
++      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
++  }
++!if $(INCLUDE_TFTP_COMMAND) == TRUE
++  ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf {
++    <PcdsFixedAtBuild>
++      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
++  }
++!endif #$(INCLUDE_TFTP_COMMAND)
++
+diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf
+new file mode 100644
+index 0000000000..9567ede0ad
+--- /dev/null
++++ b/Platform/Hisilicon/D06/D06.fdf
+@@ -0,0 +1,351 @@
++#
++#  Copyright (c) 2011, 2012, ARM Limited. All rights reserved.
++#  Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved.
++#  Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved.
++#
++#  This program and the accompanying materials
++#  are licensed and made available under the terms and conditions of the BSD License
++#  which accompanies this distribution.  The full text of the license may be found at
++#  http://opensource.org/licenses/bsd-license.php
++#
++#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++#
++
++[DEFINES]
++
++################################################################################
++#
++# FD Section
++# The [FD] Section is made up of the definition statements and a
++# description of what goes into  the Flash Device Image.  Each FD section
++# defines one flash "device" image.  A flash device image may be one of
++# the following: Removable media bootable image (like a boot floppy
++# image,) an Option ROM image (that would be "flashed" into an add-in
++# card,) a System "Flash"  image (that would be burned into a system's
++# flash) or an Update ("Capsule") image that will be used to update and
++# existing system flash.
++#
++################################################################################
++[FD.D06]
++
++BaseAddress   = 0x204100000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
++
++Size          = 0x00400000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
++ErasePolarity = 1
++
++# This one is tricky, it must be: BlockSize * NumBlocks = Size
++BlockSize     = 0x00010000
++NumBlocks     = 0x40
++
++################################################################################
++#
++# Following are lists of FD Region layout which correspond to the locations of different
++# images within the flash device.
++#
++# Regions must be defined in ascending order and may not overlap.
++#
++# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
++# the pipe "|" character, followed by the size of the region, also in hex with the leading
++# "0x" characters. Like:
++# Offset|Size
++# PcdOffsetCName|PcdSizeCName
++# RegionType <FV, DATA, or FILE>
++#
++################################################################################
++
++0x00000000|0x00100000
++gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize
++
++0x00100000|0x00280000
++gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
++FV = FVMAIN_COMPACT
++
++0x00380000|0x00020000
++gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base
++FILE = Platform/Hisilicon/D06/bl1.bin
++0x003A0000|0x00020000
++FILE = Platform/Hisilicon/D06/fip.bin
++
++0x003C0000|0x0000e000
++gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
++DATA = {
++  ## This is the EFI_FIRMWARE_VOLUME_HEADER
++  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++  # FileSystemGuid: gEfiSystemNvDataFvGuid         =
++  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
++  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
++  # FvLength: 0x20000
++  0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
++  #Signature "_FVH"       #Attributes
++  0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
++  #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
++  0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02,
++  #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block
++  0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
++  #Blockmap[1]: End
++  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++  ## This is the VARIABLE_STORE_HEADER
++!if $(SECURE_BOOT_ENABLE) == TRUE
++  #Signature: gEfiAuthenticatedVariableGuid =
++  #  { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
++  0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
++  0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
++!else
++  #Signature: gEfiVariableGuid =
++  #  { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
++  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
++  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
++!endif
++  #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8
++  0xB8, 0xdF, 0x00, 0x00,
++  #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
++  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
++}
++
++0x003CE000|0x00002000
++gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
++#NV_FTW_WORKING
++DATA = {
++  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid          =
++  0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49,
++  0xA0, 0xCE, 0x65, 0x0 , 0xFD, 0x9F, 0x1B, 0x95,
++  # Crc:UINT32            #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
++  0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
++  # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0
++  0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
++}
++
++0x003D0000|0x00010000
++gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
++
++0x003E0000|0x00010000
++
++0x003F0000|0x00010000
++FILE = Platform/Hisilicon/D0x-CustomData.Fv
++
++################################################################################
++#
++# FV Section
++#
++# [FV] section is used to define what components or modules are placed within a flash
++# device file.  This section also defines order the components and modules are positioned
++# within the image.  The [FV] section consists of define statements, set statements and
++# module statements.
++#
++################################################################################
++
++[FV.FvMain]
++BlockSize          = 0x40
++NumBlocks          = 0         # This FV gets compressed so make it just big enough
++FvAlignment        = 16        # FV alignment and FV attributes setting.
++ERASE_POLARITY     = 1
++MEMORY_MAPPED      = TRUE
++STICKY_WRITE       = TRUE
++LOCK_CAP           = TRUE
++LOCK_STATUS        = TRUE
++WRITE_DISABLED_CAP = TRUE
++WRITE_ENABLED_CAP  = TRUE
++WRITE_STATUS       = TRUE
++WRITE_LOCK_CAP     = TRUE
++WRITE_LOCK_STATUS  = TRUE
++READ_DISABLED_CAP  = TRUE
++READ_ENABLED_CAP   = TRUE
++READ_STATUS        = TRUE
++READ_LOCK_CAP      = TRUE
++READ_LOCK_STATUS   = TRUE
++
++  APRIORI DXE {
++    INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
++  }
++
++  INF MdeModulePkg/Core/Dxe/DxeMain.inf
++  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
++
++  #
++  # PI DXE Drivers producing Architectural Protocols (EFI Services)
++  #
++  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
++  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
++
++  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
++
++
++  INF Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
++  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
++  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
++
++  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
++  INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
++
++!if $(SECURE_BOOT_ENABLE) == TRUE
++  INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
++!endif
++
++  INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
++  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
++  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
++
++  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
++
++  #
++  # Multiple Console IO support
++  #
++  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
++  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
++  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
++  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
++  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
++
++  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
++  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
++
++  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
++
++  #
++  # FAT filesystem + GPT/MBR partitioning
++  #
++  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
++  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
++  INF FatPkg/EnhancedFatDxe/Fat.inf
++  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
++  INF IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
++
++  #
++  # Usb Support
++  #
++
++
++  INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
++
++  INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
++  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
++  INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
++  INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
++  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
++
++  INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
++  INF Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
++  INF Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
++
++
++
++  INF Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
++
++  INF Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
++
++  #
++  #ACPI
++  #
++  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
++  INF Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
++
++  INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
++
++  #
++  #Network
++  #
++
++  INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
++  INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
++  INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
++  INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
++  INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
++  INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
++  INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
++  INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
++!if $(NETWORK_IP6_ENABLE) == TRUE
++  INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
++  INF NetworkPkg/TcpDxe/TcpDxe.inf
++  INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
++  INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
++  INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
++  INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
++!else
++  INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
++  INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
++!endif
++  INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
++!if $(HTTP_BOOT_ENABLE) == TRUE
++  INF NetworkPkg/DnsDxe/DnsDxe.inf
++  INF NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
++  INF NetworkPkg/HttpDxe/HttpDxe.inf
++  INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf
++!endif
++
++
++  #
++  # PCI Support
++  #
++  INF Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf
++  INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
++  INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
++  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
++
++  INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
++  INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
++  INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
++  INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
++
++  INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
++  #
++  # Build Shell from latest source code instead of prebuilt binary
++  #
++  INF ShellPkg/Application/Shell/Shell.inf
++
++  INF MdeModulePkg/Application/UiApp/UiApp.inf
++  #
++  # Bds
++  #
++  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
++
++  INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
++  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
++  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
++  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
++
++[FV.FVMAIN_COMPACT]
++FvAlignment        = 16
++ERASE_POLARITY     = 1
++MEMORY_MAPPED      = TRUE
++STICKY_WRITE       = TRUE
++LOCK_CAP           = TRUE
++LOCK_STATUS        = TRUE
++WRITE_DISABLED_CAP = TRUE
++WRITE_ENABLED_CAP  = TRUE
++WRITE_STATUS       = TRUE
++WRITE_LOCK_CAP     = TRUE
++WRITE_LOCK_STATUS  = TRUE
++READ_DISABLED_CAP  = TRUE
++READ_ENABLED_CAP   = TRUE
++READ_STATUS        = TRUE
++READ_LOCK_CAP      = TRUE
++READ_LOCK_STATUS   = TRUE
++
++  APRIORI PEI {
++    INF  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
++  }
++  INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
++  INF MdeModulePkg/Core/Pei/PeiMain.inf
++  INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
++
++  INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
++  INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
++
++  INF Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
++
++  INF ArmPkg/Drivers/CpuPei/CpuPei.inf
++  INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
++  INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
++
++  INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
++
++  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
++    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
++      SECTION FV_IMAGE = FVMAIN
++    }
++  }
++
++!include Silicon/Hisilicon/Hisilicon.fdf.inc
++
+diff --git a/Platform/Hisilicon/D06/Include/Library/CpldD06.h b/Platform/Hisilicon/D06/Include/Library/CpldD06.h
+new file mode 100644
+index 0000000000..be3548c8d1
+--- /dev/null
++++ b/Platform/Hisilicon/D06/Include/Library/CpldD06.h
+@@ -0,0 +1,37 @@
++/** @file
++
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++  Copyright (c) 2018, Linaro Limited. All rights reserved.<BR>
++
++  This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++**/
++
++#ifndef __CPLDD06_H__
++#define __CPLDD06_H__
++
++#define CPLD_BASE_ADDRESS                 0x80000000
++
++#define CPLD_BIOSINDICATE_FLAG            0x09
++#define CPLD_I2C_SWITCH_FLAG              0x17
++#define CPU_GET_I2C_CONTROL               BIT2
++#define BMC_I2C_STATUS                    BIT3
++
++#define CPLD_LOGIC_VERSION                (0x4)
++#define CPLD_LOGIC_COMPILE_YEAR          (0x1)
++#define CPLD_LOGIC_COMPILE_MONTH         (0x2)
++#define CPLD_LOGIC_COMPILE_DAY           (0x3)
++
++#define CPLD_RISER_PRSNT_FLAG             0x40
++#define CPLD_RISER2_BOARD_ID              0x44
++
++#define CPLD_X8_X8_X8_BOARD_ID            0x92
++#define CPLD_X16_X8_BOARD_ID              0x93
++
++#endif /* __CPLDD06_H__ */
+diff --git a/Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h b/Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h
+new file mode 100644
+index 0000000000..05f0f7020e
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h
+@@ -0,0 +1,85 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++#ifndef _SERDES_LIB_H_
++#define _SERDES_LIB_H_
++
++typedef enum {
++  EmHilink0Hccs1X8 = 0,
++  EmHilink0Pcie1X8 = 2,
++  EmHilink0Pcie1X4Pcie2X4 = 3,
++  EmHilink0Sas2X8 = 4,
++  EmHilink0Hccs1X8Width16,
++  EmHilink0Hccs1X8Width32,
++  EmHilink0Hccs1X8Speed5G,
++} HILINK0_MODE_TYPE;
++
++typedef enum {
++  EmHilink1Sas2X1 = 0,
++  EmHilink1Hccs0X8 = 1,
++  EmHilink1Pcie0X8 = 2,
++  EmHilink1Hccs0X8Width16,
++  EmHilink1Hccs0X8Width32,
++  EmHilink1Hccs0X8Speed5G,
++} HILINK1_MODE_TYPE;
++
++typedef enum {
++  EmHilink2Pcie2X8 = 0,
++  EmHilink2Hccs2X8 = 1,
++  EmHilink2Sas0X8 = 2,
++  EmHilink2Hccs2X8Width16,
++  EmHilink2Hccs2X8Width32,
++  EmHilink2Hccs2X8Speed5G,
++} HILINK2_MODE_TYPE;
++
++typedef enum {
++  EmHilink5Pcie3X4 = 0,
++  EmHilink5Pcie2X2Pcie3X2 = 1,
++  EmHilink5Sas1X4 = 2,
++} HILINK5_MODE_TYPE;
++
++
++typedef struct {
++  HILINK0_MODE_TYPE Hilink0Mode;
++  HILINK1_MODE_TYPE Hilink1Mode;
++  HILINK2_MODE_TYPE Hilink2Mode;
++  UINT32 Hilink3Mode;
++  UINT32 Hilink4Mode;
++  HILINK5_MODE_TYPE Hilink5Mode;
++  UINT32 Hilink6Mode;
++  UINT32 UseSsc;
++} SERDES_PARAM;
++
++#define SERDES_INVALID_MACRO_ID  0xFFFFFFFF
++#define SERDES_INVALID_LANE_NUM  0xFFFFFFFF
++#define SERDES_INVALID_RATE_MODE  0xFFFFFFFF
++
++typedef struct {
++  UINT32 MacroId;
++  UINT32 DsNum;
++  UINT32 DsCfg;
++} SERDES_POLARITY_INVERT;
++
++EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId);
++extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[];
++extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[];
++UINT32 GetEthType (UINT8 EthChannel);
++VOID SerdesEnableCtleDfe (UINT32 NimbusId, UINT32 Macro, UINT32 Lane, UINT32 LaneMode);
++
++EFI_STATUS EfiSerdesInitWrap (UINT32 RateMode);
++INT32 SerdesReset (UINT32 SiclId, UINT32 Macro);
++VOID SerdesLoadFirmware (UINT32 SiclId, UINT32 Macro);
++INT32 h30_serdes_run_firmware (UINT32 nimbus_id, UINT32 macro, UINT8 DsMask, UINT8 ctle_mode);
++#endif
+diff --git a/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h
+new file mode 100644
+index 0000000000..9539cfdada
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h
+@@ -0,0 +1,61 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++
++
++#ifndef _PLATFORM_ARCH_H_
++#define _PLATFORM_ARCH_H_
++
++#define MAX_SOCKET      2
++#define MAX_DIE         4
++#define MAX_DDRC        4
++#define MAX_NODE        (MAX_SOCKET * MAX_DIE)
++#define MAX_CHANNEL     8
++#define MAX_DIMM        2
++#define MAX_RANK_CH     8
++#define MAX_RANK_DIMM   4
++#define MAX_DIMM_SIZE   256  // In GB
++// Max NUMA node number for each node type
++#define MAX_NUM_PER_TYPE 8
++
++#define RASC_BASE                (0x1800)
++#define RASC_CFG_INFOIDX_REG     (RASC_BASE + 0x58)  /* configuration register for Rank statistical information */
++#define RASC_CFG_SPLVL_REG       (RASC_BASE + 0xD4)  /* configuration register for Sparing level */
++
++//
++// ACPI table information used to initialize tables.
++//
++#define EFI_ACPI_ARM_OEM_ID           'H','I','S','I',' ',' '   // OEMID 6 bytes long
++#define EFI_ACPI_ARM_OEM_TABLE_ID     SIGNATURE_64 ('H','I','P','0','8',' ',' ',' ') // OEM table id 8 bytes long
++#define EFI_ACPI_ARM_OEM_REVISION     0x00000000
++#define EFI_ACPI_ARM_CREATOR_ID       SIGNATURE_32 ('H','I','S','I')
++#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
++
++// A macro to initialise the common header part of EFI ACPI tables as defined by
++// EFI_ACPI_DESCRIPTION_HEADER structure.
++#define ARM_ACPI_HEADER(Signature, Type, Revision) {            \
++  Signature,                      /* UINT32  Signature */       \
++  sizeof (Type),                  /* UINT32  Length */          \
++  Revision,                       /* UINT8   Revision */        \
++  0,                              /* UINT8   Checksum */        \
++  { EFI_ACPI_ARM_OEM_ID },        /* UINT8   OemId[6] */        \
++  EFI_ACPI_ARM_OEM_TABLE_ID,      /* UINT64  OemTableId */      \
++  EFI_ACPI_ARM_OEM_REVISION,      /* UINT32  OemRevision */     \
++  EFI_ACPI_ARM_CREATOR_ID,        /* UINT32  CreatorId */       \
++  EFI_ACPI_ARM_CREATOR_REVISION   /* UINT32  CreatorRevision */ \
++  }
++
++#endif
++
+diff --git a/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h b/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h
+index 21498b7056..332a79343f 100644
+--- a/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h
++++ b/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h
+@@ -27,7 +27,13 @@ typedef struct _DDRC_BASE_ID{
+ UINTN OemGetPoeSubBase (UINT32 NodeId);
+ UINTN OemGetPeriSubBase (UINT32 NodeId);
+ UINTN OemGetAlgSubBase (UINT32 NodeId);
++UINTN OemGetCfgbusBase (UINT32 NodeId);
++UINTN OemGetGicSubBase (UINT32 NodeId);
++UINTN OemGetHACSubBase (UINT32 NodeId);
++UINTN OemGetIOMGMTSubBase (UINT32 NodeId);
++UINTN OemGetNetworkSubBase (UINT32 NodeId);
+ UINTN OemGetM3SubBase (UINT32 NodeId);
++UINTN OemGetPCIeSubBase (UINT32 NodeId);
+ 
+ VOID OemAddressMapInit(VOID);
+ 
+diff --git a/Silicon/Hisilicon/Include/Library/OemNicLib.h b/Silicon/Hisilicon/Include/Library/OemNicLib.h
+new file mode 100644
+index 0000000000..66fe9a2e9b
+--- /dev/null
++++ b/Silicon/Hisilicon/Include/Library/OemNicLib.h
+@@ -0,0 +1,57 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++
++#ifndef _OEM_NIC_LIB_H_
++#define _OEM_NIC_LIB_H_
++
++#define ETH_MAX_PORT          8
++#define ETH_DEBUG_PORT0       6
++#define ETH_DEBUG_PORT1       7
++
++#define ETH_SPEED_10M     6
++#define ETH_SPEED_100M    7
++#define ETH_SPEED_1000M   8
++#define ETH_SPEED_10KM    9
++#define ETH_HALF_DUPLEX   0
++#define ETH_FULL_DUPLEX   1
++
++#define ETH_GDD_ID                          0x001378e0
++#define ETH_PHY_BCM5241_ID                  0x0143bc30
++#define ETH_PHY_MVL88E1145_ID               0x01410cd0
++#define ETH_PHY_MVL88E1119_ID               0x01410e80
++#define ETH_PHY_MVL88E1512_ID               0x01410dd0
++#define ETH_PHY_MVL88E1543_ID               0x01410ea0
++#define ETH_PHY_NLP3142_ID                  0x00000412
++
++#define ETH_INVALID                         0xffffffff
++
++typedef struct {
++  UINT32 Valid;
++  UINT32 Speed;
++  UINT32 Duplex;
++  UINT32 PhyId;
++  UINT32 PhyAddr;
++} ETH_PRODUCT_DESC;
++
++BOOLEAN OemIsInitEth (UINT32 Port);
++UINT32 OemEthFindFirstSP ();
++ETH_PRODUCT_DESC *OemEthInit (UINT32 port);
++UINT32 GetCpu1FiberType (UINT8 *Fiber1Type, UINT8 *Fiber2Type);
++UINT32 GetCpu2FiberType (UINT8 *Fiber1Type, UINT8 *Fiber2Type, UINT8 *Fiber100Ge);
++EFI_STATUS EFIAPI OemGetMac (IN OUT EFI_MAC_ADDRESS *Mac, IN UINTN Port);
++EFI_STATUS EFIAPI OemSetMac (IN EFI_MAC_ADDRESS *Mac, IN UINTN Port);
++
++#endif
+-- 
+2.17.0
+
diff --git a/v2/v2-0011-Platform-Hisilicon-D06-Add-M41T83RealTimeClockLib.patch b/v2/v2-0011-Platform-Hisilicon-D06-Add-M41T83RealTimeClockLib.patch
new file mode 100644
index 0000000000..15bb4f327c
--- /dev/null
+++ b/v2/v2-0011-Platform-Hisilicon-D06-Add-M41T83RealTimeClockLib.patch
@@ -0,0 +1,818 @@ 
+From 6335047a06601ba279e8a761a42794cd70461f4a Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Wed, 13 Jun 2018 20:20:29 +0800
+Subject: [PATCH edk2-platforms v2 11/43] Platform/Hisilicon/D06: Add
+ M41T83RealTimeClockLib
+
+Add M41T83RealTimeClockLib for RTC.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Platform/Hisilicon/D06/D06.dsc                                              |   1 +
+ Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf |  46 ++
+ Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClock.h      | 158 ++++++
+ Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.c   | 564 ++++++++++++++++++++
+ 4 files changed, 769 insertions(+)
+
+diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
+index d14fce1159..27358f8c78 100644
+--- a/Platform/Hisilicon/D06/D06.dsc
++++ b/Platform/Hisilicon/D06/D06.dsc
+@@ -65,6 +65,7 @@
+   CpldIoLib|Silicon/Hisilicon/Library/CpldIoLib/CpldIoLib.inf
+ 
+   TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
++  RealTimeClockLib|Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf
+ 
+   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+   GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
+diff --git a/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf b/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf
+new file mode 100644
+index 0000000000..e0bf6b3f24
+--- /dev/null
++++ b/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf
+@@ -0,0 +1,46 @@
++#/** @file
++#
++#  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++#  Copyright (c) 2018, Linaro Limited. All rights reserved.<BR>
++#
++#  This program and the accompanying materials
++#  are licensed and made available under the terms and conditions of the BSD License
++#  which accompanies this distribution.  The full text of the license may be found at
++#  http://opensource.org/licenses/bsd-license.php
++#
++#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++#
++#**/
++
++[Defines]
++  INF_VERSION                    = 0x0001001A
++  BASE_NAME                      = M41T83RealTimeClockLib
++  FILE_GUID                      = 470DFB96-E205-4515-A75E-2E60F853E79D
++  MODULE_TYPE                    = BASE
++  VERSION_STRING                 = 1.0
++  LIBRARY_CLASS                  = RealTimeClockLib
++
++[Sources.common]
++  M41T83RealTimeClockLib.c
++
++[Packages]
++  EmbeddedPkg/EmbeddedPkg.dec
++  MdePkg/MdePkg.dec
++  Platform/Hisilicon/D06/D06.dec
++  Silicon/Hisilicon/HisiPkg.dec
++
++[LibraryClasses]
++  BaseMemoryLib
++  CpldIoLib
++  DebugLib
++  I2CLib
++  IoLib
++  PcdLib
++  TimeBaseLib
++  TimerLib
++  UefiLib
++  UefiRuntimeLib        # Use EFiAtRuntime to check stage
++
++[Depex]
++  gEfiCpuArchProtocolGuid
+diff --git a/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClock.h b/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClock.h
+new file mode 100644
+index 0000000000..ed10099bf3
+--- /dev/null
++++ b/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClock.h
+@@ -0,0 +1,158 @@
++/** @file
++
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++  Copyright (c) 2018, Linaro Limited. All rights reserved.<BR>
++
++  This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++**/
++
++#ifndef __M41T83_REAL_TIME_CLOCK_H__
++#define __M41T83_REAL_TIME_CLOCK_H__
++
++// The delay is need for cpld and I2C. This is a empirical value. MemoryFance is no need.
++#define RTC_DELAY_30_MS            30000
++// The delay is need for cpld and I2C. This is a empirical value. MemoryFance is no need.
++#define RTC_DELAY_1000_MACROSECOND 1000
++// The delay is need for cpld and I2C. This is a empirical value. MemoryFance is no need.
++#define RTC_DELAY_2_MACROSECOND    2
++
++#define M41T83_REGADDR_DOTSECONDS       0x00
++#define M41T83_REGADDR_SECONDS          0x01
++#define M41T83_REGADDR_MINUTES          0x02
++#define M41T83_REGADDR_HOURS            0x03
++#define M41T83_REGADDR_WEEK_DAY         0x04
++#define M41T83_REGADDR_DAY              0x05
++#define M41T83_REGADDR_MONTH            0x06
++#define M41T83_REGADDR_YEAR             0x07
++#define M41T83_REGADDR_ALARM1SEC        0x0E
++#define M41T83_REGADDR_ALARM1MIN        0x0D
++#define M41T83_REGADDR_ALARM1HOUR       0x0C
++#define M41T83_REGADDR_ALARM1DATE       0x0B
++#define M41T83_REGADDR_ALARM1MONTH      0x0A
++
++#define M41T83_REGADDR_TIMERCONTROL     0x11
++
++#define M41T83_REGADDR_ALARM2SEC        0x18
++#define M41T83_REGADDR_ALARM2MIN        0x17
++#define M41T83_REGADDR_ALARM2HOUR       0x16
++#define M41T83_REGADDR_ALARM2DATE       0x15
++#define M41T83_REGADDR_ALARM2MONTH      0x14
++
++typedef union {
++  struct {
++    UINT8 TD0:1;
++    UINT8 TD1:1;
++    UINT8 RSV:3;
++    UINT8 TIE:1;
++    UINT8 TITP:1;
++    UINT8 TE:1;
++  } Bits;
++  UINT8 Uint8;
++} RTC_M41T83_TIMERCONTROL;
++
++typedef union {
++  struct {
++    UINT8 MicroSeconds;
++  } Bits;
++  UINT8 Uint8;
++} RTC_M41T83_DOTSECOND;
++
++typedef union {
++  struct{
++    UINT8 Seconds:7;
++    UINT8 ST:1;
++  } Bits;
++  UINT8 Uint8;
++} RTC_M41T83_SECOND;
++
++typedef union {
++  struct {
++    UINT8 Minutes:7;
++    UINT8 Rsv:1;
++  } Bits;
++  UINT8 Uint8;
++} RTC_M41T83_MINUTE;
++
++typedef union {
++  struct {
++    UINT8 Hours:6;
++    UINT8 CB:2;
++  } Bits;
++  UINT8 Uint8;
++} RTC_M41T83_HOUR;
++
++typedef union {
++  struct{
++    UINT8 Days:3;
++    UINT8 Rsv:5;
++  } Bits;
++  UINT8 Uint8;
++} RTC_M41T83_WEEK_DAY;
++
++typedef union {
++  struct{
++    UINT8 Days:6;
++    UINT8 Rsv:2;
++  } Bits;
++  UINT8 Uint8;
++} RTC_M41T83_MONTH_DAY;
++
++typedef union {
++  struct {
++    UINT8 Months:5;
++    UINT8 Rsv:3;
++  } Bits;
++  UINT8 Uint8;
++} RTC_M41T83_MONTH;
++
++typedef union {
++  struct {
++    UINT8 Years:8;
++  } Bits;
++  UINT8 Uint8;
++} RTC_M41T83_YEAR;
++
++typedef union {
++  struct {
++    UINT8 Second:7;
++    UINT8 RPT11:1;
++  } Bits;
++  UINT8 Uint8;
++} RTC_M41T83_ALARM1SEC;
++
++typedef union {
++  struct {
++    UINT8 Minute:7;
++    UINT8 RPT12:1;
++  } Bits;
++  UINT8 Uint8;
++} RTC_M41T83_ALARM1MIN;
++
++typedef union {
++  struct {
++    UINT8 Hour:6;
++    UINT8 HT:1;
++    UINT8 RPT13:1;
++  } Bits;
++  UINT8 Uint8;
++} RTC_M41T83_ALARM1HOUR;
++
++typedef struct {
++  RTC_M41T83_DOTSECOND  DotSecond;
++  RTC_M41T83_SECOND     Second;
++  RTC_M41T83_MINUTE     Minute;
++  RTC_M41T83_HOUR       Hour;
++  RTC_M41T83_WEEK_DAY   WeekDay;
++  RTC_M41T83_MONTH_DAY  Day;
++  RTC_M41T83_MONTH      Month;
++  RTC_M41T83_YEAR       Year;
++} RTC_M41T83_TIME;
++
++#endif
+diff --git a/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.c b/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.c
+new file mode 100644
+index 0000000000..eabe8dc0f3
+--- /dev/null
++++ b/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.c
+@@ -0,0 +1,564 @@
++/** @file
++
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++  Copyright (c) 2018, Linaro Limited. All rights reserved.<BR>
++
++  This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++**/
++
++#include <Uefi.h>
++#include <PiDxe.h>
++#include <Library/BaseLib.h>
++#include <Library/BaseMemoryLib.h>
++#include <Library/CpldD06.h>
++#include <Library/CpldIoLib.h>
++#include <Library/DebugLib.h>
++#include <Library/I2CLib.h>
++#include <Library/IoLib.h>
++#include <Library/MemoryAllocationLib.h>
++#include <Library/PcdLib.h>
++#include <Library/TimeBaseLib.h>
++#include <Library/TimerLib.h>
++#include <Library/UefiLib.h>
++#include <Library/UefiBootServicesTableLib.h>
++#include <Library/UefiRuntimeLib.h>
++#include <Library/UefiRuntimeServicesTableLib.h>
++#include <Protocol/RealTimeClock.h>
++#include "M41T83RealTimeClock.h"
++
++extern I2C_DEVICE gRtcDevice;
++
++STATIC EFI_LOCK  mRtcLock;
++
++EFI_STATUS
++SwitchRtcI2cChannelAndLock (
++  VOID
++  )
++{
++  UINT8   Temp;
++  UINT8   Count;
++
++  for (Count = 0; Count < 100; Count++) {
++    // To get the other side's state is idle first
++    Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
++    if ((Temp & BIT3) != 0) {
++      (VOID) MicroSecondDelay (RTC_DELAY_30_MS);
++      // Try 100 times, if BMC has not released the bus, return preemption failed
++      if (Count == 99) {
++        if (!EfiAtRuntime ()) {
++          DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Clear cpu_i2c_rtc_state 100 times fail!\n",
++            __FUNCTION__, __LINE__));
++        }
++        return EFI_DEVICE_ERROR;
++      }
++      continue;
++    }
++
++    // if BMC free the bus, can be set 1 preemption
++    Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
++    Temp = Temp | CPU_GET_I2C_CONTROL;
++    // CPU occupied RTC I2C State
++    WriteCpldReg (CPLD_I2C_SWITCH_FLAG, Temp);
++    (VOID) MicroSecondDelay (RTC_DELAY_2_MACROSECOND);
++    Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
++    // Is preempt success
++    if(CPU_GET_I2C_CONTROL == (Temp & CPU_GET_I2C_CONTROL)) {
++      break;
++    }
++    if (Count == 99) {
++      if (!EfiAtRuntime ()) {
++        DEBUG((DEBUG_ERROR, "[%a]:[%dL]  Clear cpu_i2c_rtc_state fail !!! \n",
++          __FUNCTION__, __LINE__));
++      }
++      return EFI_DEVICE_ERROR;
++    }
++    (VOID) MicroSecondDelay (RTC_DELAY_30_MS);
++  }
++
++  //Polling BMC RTC I2C status
++  for (Count = 0; Count < 100; Count++) {
++    Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
++    if ((Temp & BIT3) == 0) {
++      return EFI_SUCCESS;
++    }
++    (VOID) MicroSecondDelay (RTC_DELAY_30_MS);
++  }
++
++  //If the BMC occupies the RTC I2C Channel, write back the CPU side is idle
++  // or the subsequent BMC will not preempt
++  Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
++  Temp = Temp & (~CPU_GET_I2C_CONTROL);
++  WriteCpldReg (CPLD_I2C_SWITCH_FLAG, Temp);
++
++  return EFI_NOT_READY;
++}
++
++
++/**
++  Read RTC content through its registers.
++
++  @param  Address   Address offset of RTC data.
++  @param  Size      Size of RTC data to read.
++  @param  Data      The data of UINT8 type read from RTC.
++
++  @return EFI_STATUS
++**/
++EFI_STATUS
++RtcRead (
++  IN  UINT8   Address,
++  IN  UINT8   Size,
++  OUT UINT8   *Data
++  )
++{
++  EFI_STATUS  Status;
++
++  Status = I2CRead (&gRtcDevice, Address, Size, Data);
++  MicroSecondDelay (RTC_DELAY_1000_MACROSECOND);
++  return Status;
++}
++
++/**
++  Write RTC through its registers.
++
++  @param  Address   Address offset of RTC data.
++  @param  Size      Size of RTC data to write.
++  @param  Data      The data of UINT8 type write from RTC.
++
++  @return EFI_STATUS
++**/
++EFI_STATUS
++RtcWrite (
++  IN  UINT8   Address,
++  IN  UINT8   Size,
++  UINT8       *Data
++  )
++{
++  EFI_STATUS  Status;
++
++  Status = I2CWrite (&gRtcDevice, Address, Size, Data);
++  MicroSecondDelay (RTC_DELAY_1000_MACROSECOND);
++  return Status;
++}
++
++VOID
++ReleaseOwnershipOfRtc (
++  VOID
++  )
++{
++  UINT8   Temp;
++
++  Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
++  Temp = Temp & ~CPU_GET_I2C_CONTROL;
++  WriteCpldReg (CPLD_I2C_SWITCH_FLAG, Temp);
++}
++
++
++EFI_STATUS
++InitializeM41T83 (
++  VOID
++  )
++{
++  EFI_STATUS                Status;
++  RTC_M41T83_ALARM1HOUR     Alarm1Hour;
++  RTC_M41T83_SECOND         Second;
++
++  // Acquire RTC Lock to make access to RTC atomic
++  if (!EfiAtRuntime ()) {
++    EfiAcquireLock (&mRtcLock);
++  }
++
++  Status = I2CInit (gRtcDevice.Socket, gRtcDevice.Port, Normal);
++  MicroSecondDelay (RTC_DELAY_1000_MACROSECOND);
++  if (EFI_ERROR (Status)) {
++    if (!EfiAtRuntime ()) {
++      EfiReleaseLock (&mRtcLock);
++    }
++    return Status;
++  }
++
++  Status = SwitchRtcI2cChannelAndLock ();
++  if (EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "Get i2c preemption failed: %r\n", Status));
++    if (!EfiAtRuntime ()) {
++      EfiReleaseLock (&mRtcLock);
++    }
++    return Status;
++  }
++
++  MicroSecondDelay(RTC_DELAY_1000_MACROSECOND);
++
++  // Set ST at Power up to clear Oscillator fail detection(OF)
++  Status = RtcRead (M41T83_REGADDR_SECONDS, 1, &Second.Uint8);
++  if (EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n",
++      __FUNCTION__, __LINE__, Status));
++  }
++  Second.Bits.ST= 1;
++  Status = RtcWrite (M41T83_REGADDR_SECONDS, 1, &Second.Uint8);
++  if (EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n",
++      __FUNCTION__, __LINE__, Status));
++    goto Exit;
++  }
++  Status = RtcRead (M41T83_REGADDR_SECONDS, 1, &Second.Uint8);
++  if (EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n",
++      __FUNCTION__, __LINE__, Status));
++  }
++  Second.Bits.ST= 0;
++  Status = RtcWrite (M41T83_REGADDR_SECONDS, 1, &Second.Uint8);
++  if (EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n",
++      __FUNCTION__, __LINE__, Status));
++    goto Exit;
++  }
++
++  // Clear HT bit to enanle write to the RTC registers (addresses 0-7)
++  Status = RtcRead (M41T83_REGADDR_ALARM1HOUR, 1, &Alarm1Hour.Uint8);
++  if (EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n",
++      __FUNCTION__, __LINE__, Status));
++  }
++  Alarm1Hour.Bits.HT = 0;
++  Status = RtcWrite (M41T83_REGADDR_ALARM1HOUR, 1, &Alarm1Hour.Uint8);
++  if (EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n",
++      __FUNCTION__, __LINE__, Status));
++    goto Exit;
++  }
++
++Exit:
++  // Release RTC Lock.
++  ReleaseOwnershipOfRtc ();
++  if (!EfiAtRuntime ()) {
++    EfiReleaseLock (&mRtcLock);
++  }
++  return Status;
++}
++
++/**
++  Sets the current local time and date information.
++
++  @param  Time                  A pointer to the current time.
++
++  @retval EFI_SUCCESS           The operation completed successfully.
++  @retval EFI_INVALID_PARAMETER A time field is out of range.
++  @retval EFI_DEVICE_ERROR      The time could not be set due due to hardware error.
++
++**/
++EFI_STATUS
++EFIAPI
++LibSetTime (
++  IN  EFI_TIME                *Time
++  )
++{
++  EFI_STATUS                  Status = EFI_SUCCESS;
++  RTC_M41T83_TIME             BcdTime;
++  UINT16                      CenturyBase = 2000;
++  UINTN                       LineNum = 0;
++
++  if (NULL == Time) {
++    return EFI_INVALID_PARAMETER;
++  }
++
++  if (!IsTimeValid (Time)) {
++    if (!EfiAtRuntime ()) {
++      DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n",
++        __FUNCTION__, __LINE__, Status));
++      DEBUG ((DEBUG_ERROR, "Now RTC Time is : %04d-%02d-%02d %02d:%02d:%02d\n",
++        Time->Year, Time->Month, Time->Day, Time->Hour, Time->Minute, Time->Second
++      ));
++    }
++    return EFI_INVALID_PARAMETER;
++  }
++
++  Status = SwitchRtcI2cChannelAndLock ();
++  if (EFI_ERROR (Status)) {
++    return Status;
++  }
++  (VOID)MicroSecondDelay (RTC_DELAY_1000_MACROSECOND);
++
++  SetMem (&BcdTime, sizeof (RTC_M41T83_TIME), 0);
++
++  // Acquire RTC Lock to make access to RTC atomic
++  if (!EfiAtRuntime ()) {
++    EfiAcquireLock (&mRtcLock);
++  }
++
++  BcdTime.Second.Bits.Seconds = DecimalToBcd8 (Time->Second);
++  BcdTime.Minute.Bits.Minutes = DecimalToBcd8 (Time->Minute);
++  BcdTime.Hour.Bits.Hours = DecimalToBcd8 (Time->Hour);
++  BcdTime.Day.Bits.Days = DecimalToBcd8 (Time->Day);
++  BcdTime.Month.Bits.Months = DecimalToBcd8 (Time->Month);
++  BcdTime.Year.Bits.Years = DecimalToBcd8 (Time->Year % 100);
++  BcdTime.Hour.Bits.CB = (Time->Year - CenturyBase) / 100 % 10;
++
++  Status = RtcWrite (M41T83_REGADDR_DOTSECONDS, 1, &BcdTime.DotSecond.Uint8);
++  if (EFI_ERROR (Status)) {
++    LineNum = __LINE__;
++    goto Exit;
++  }
++  Status = RtcWrite (M41T83_REGADDR_SECONDS, 1, &BcdTime.Second.Uint8);
++  if (EFI_ERROR (Status)) {
++    LineNum = __LINE__;
++    goto Exit;
++  }
++  Status = RtcWrite (M41T83_REGADDR_MINUTES, 1, &BcdTime.Minute.Uint8);
++  if (EFI_ERROR (Status)) {
++    LineNum = __LINE__;
++    goto Exit;
++  }
++  Status = RtcWrite (M41T83_REGADDR_HOURS, 1, &BcdTime.Hour.Uint8);
++  if (EFI_ERROR (Status)) {
++    LineNum = __LINE__;
++    goto Exit;
++  }
++  Status = RtcWrite (M41T83_REGADDR_DAY, 1, &BcdTime.Day.Uint8);
++  if (EFI_ERROR (Status)) {
++    LineNum = __LINE__;
++    goto Exit;
++  }
++  Status = RtcWrite (M41T83_REGADDR_MONTH, 1, &BcdTime.Month.Uint8);
++  if (EFI_ERROR (Status)) {
++    LineNum = __LINE__;
++    goto Exit;
++  }
++  Status = RtcWrite (M41T83_REGADDR_YEAR, 1, &BcdTime.Year.Uint8);
++  if (EFI_ERROR (Status)) {
++    LineNum = __LINE__;
++    goto Exit;
++  }
++
++Exit:
++  ReleaseOwnershipOfRtc ();
++  // Release RTC Lock.
++  if (!EfiAtRuntime ()) {
++    if (EFI_ERROR (Status)) {
++      DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n",
++        __FUNCTION__, LineNum, Status));
++    }
++    EfiReleaseLock (&mRtcLock);
++  }
++  return Status;
++}
++
++
++/**
++  Returns the current time and date information, and the time-keeping capabilities
++  of the hardware platform.
++
++  @param  Time                   A pointer to storage to receive a snapshot of the current time.
++  @param  Capabilities           An optional pointer to a buffer to receive the real time clock
++                                 device's capabilities.
++
++  @retval EFI_SUCCESS            The operation completed successfully.
++  @retval EFI_INVALID_PARAMETER  Time is NULL.
++  @retval EFI_DEVICE_ERROR       The time could not be retrieved due to hardware error.
++  @retval EFI_SECURITY_VIOLATION The time could not be retrieved due to an authentication failure.
++**/
++EFI_STATUS
++EFIAPI
++LibGetTime (
++  OUT EFI_TIME                *Time,
++  OUT EFI_TIME_CAPABILITIES   *Capabilities
++  )
++{
++  EFI_STATUS                  Status = EFI_SUCCESS;
++  RTC_M41T83_TIME             BcdTime;
++  UINT16                      CenturyBase = 2000;
++  UINTN                       LineNum = 0;
++  BOOLEAN                     IsTimeInvalid = FALSE;
++  UINT8                       TimeTemp[7] = {0};
++
++  // Ensure Time is a valid pointer
++  if (Time == NULL) {
++    return EFI_INVALID_PARAMETER;
++  }
++
++  Status = SwitchRtcI2cChannelAndLock ();
++  if (EFI_ERROR (Status)) {
++    return Status;
++  }
++
++  MicroSecondDelay(RTC_DELAY_1000_MACROSECOND);
++
++  SetMem (&BcdTime, sizeof (RTC_M41T83_TIME), 0);
++  SetMem (Time , sizeof (EFI_TIME), 0);
++
++  // Acquire RTC Lock to make access to RTC atomic
++  if (!EfiAtRuntime ()) {
++    EfiAcquireLock (&mRtcLock);
++  }
++
++  Status = RtcRead (M41T83_REGADDR_SECONDS, 7, TimeTemp);
++  if (EFI_ERROR (Status)) {
++    LineNum = __LINE__;
++    goto Exit;
++  }
++
++  BcdTime.Second.Uint8 = TimeTemp[0];  //SECONDS
++  BcdTime.Minute.Uint8 = TimeTemp[1];  //MINUTES
++  BcdTime.Hour.Uint8 = TimeTemp[2];    //HOURS
++  BcdTime.Day.Uint8 = TimeTemp[4];     //DAY
++  BcdTime.Month.Uint8 = TimeTemp[5];   //MONTH
++  BcdTime.Year.Uint8 = TimeTemp[6];    //Year
++
++  Time->Year = BcdToDecimal8 (BcdTime.Year.Bits.Years);
++  Time->Year += CenturyBase + BcdTime.Hour.Bits.CB * 100;
++  Time->Month = BcdToDecimal8 (BcdTime.Month.Bits.Months);
++  Time->Day = BcdToDecimal8 (BcdTime.Day.Bits.Days);
++  Time->Hour = BcdToDecimal8 (BcdTime.Hour.Bits.Hours);
++  Time->Minute = BcdToDecimal8 (BcdTime.Minute.Bits.Minutes);
++  Time->Second = BcdToDecimal8 (BcdTime.Second.Bits.Seconds);
++  Time->TimeZone = EFI_UNSPECIFIED_TIMEZONE;
++
++  if (!IsTimeValid (Time)) {
++      Status = EFI_DEVICE_ERROR;
++      LineNum = __LINE__;
++      IsTimeInvalid = TRUE;
++      goto Exit;
++  }
++
++Exit:
++  ReleaseOwnershipOfRtc ();
++  // Release RTC Lock.
++  if (!EfiAtRuntime ()) {
++    if (EFI_ERROR (Status)) {
++      if (IsTimeInvalid == TRUE) {
++        DEBUG((DEBUG_ERROR, "%a(%d) Time invalid.\r\n",__FUNCTION__, LineNum));
++      } else {
++        DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n",
++          __FUNCTION__, LineNum, Status));
++      }
++    }
++    EfiReleaseLock (&mRtcLock);
++  }
++  return Status;
++}
++
++
++/**
++  Returns the current wakeup alarm clock setting.
++
++  @param  Enabled               Indicates if the alarm is currently enabled or disabled.
++  @param  Pending               Indicates if the alarm signal is pending and requires acknowledgement.
++  @param  Time                  The current alarm setting.
++
++  @retval EFI_SUCCESS           The alarm settings were returned.
++  @retval EFI_INVALID_PARAMETER Any parameter is NULL.
++  @retval EFI_DEVICE_ERROR      The wakeup time could not be retrieved due to a hardware error.
++
++**/
++EFI_STATUS
++EFIAPI
++LibGetWakeupTime (
++  OUT BOOLEAN     *Enabled,
++  OUT BOOLEAN     *Pending,
++  OUT EFI_TIME    *Time
++  )
++{
++  // Not a required feature
++  return EFI_UNSUPPORTED;
++}
++
++
++/**
++  Sets the system wakeup alarm clock time.
++
++  @param  Enabled               Enable or disable the wakeup alarm.
++  @param  Time                  If Enable is TRUE, the time to set the wakeup alarm for.
++
++  @retval EFI_SUCCESS           If Enable is TRUE, then the wakeup alarm was enabled. If
++                                Enable is FALSE, then the wakeup alarm was disabled.
++  @retval EFI_INVALID_PARAMETER A time field is out of range.
++  @retval EFI_DEVICE_ERROR      The wakeup time could not be set due to a hardware error.
++  @retval EFI_UNSUPPORTED       A wakeup timer is not supported on this platform.
++
++**/
++EFI_STATUS
++EFIAPI
++LibSetWakeupTime (
++  IN  BOOLEAN      Enabled,
++  OUT EFI_TIME     *Time
++  )
++{
++  // Not a required feature
++  return EFI_UNSUPPORTED;
++}
++
++
++/**
++  This is the declaration of an EFI image entry point. This can be the entry point to an application
++  written to this specification, an EFI boot service driver, or an EFI runtime driver.
++
++  @param  ImageHandle           Handle that identifies the loaded image.
++  @param  SystemTable           System Table for this image.
++
++  @retval EFI_SUCCESS           The operation completed successfully.
++
++**/
++EFI_STATUS
++EFIAPI
++LibRtcInitialize (
++  IN EFI_HANDLE                            ImageHandle,
++  IN EFI_SYSTEM_TABLE                      *SystemTable
++  )
++{
++  EFI_STATUS    Status = EFI_SUCCESS;
++  EFI_TIME      EfiTime;
++
++  EfiInitializeLock (&mRtcLock, TPL_CALLBACK);
++
++  // Setup the setters and getters
++  gRT->GetTime       = LibGetTime;
++  gRT->SetTime       = LibSetTime;
++  gRT->GetWakeupTime = LibGetWakeupTime;
++  gRT->SetWakeupTime = LibSetWakeupTime;
++
++  Status = InitializeM41T83 ();
++  if (EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\nRTC M41T83 Init Failed !!!\n",
++            __FUNCTION__, __LINE__, Status));
++    /*
++     * Returning ERROR on failure of RTC initilization will cause the system to hang up.
++     * So we add some debug message to indecate the RTC initilization failed,
++     * and continue without returning with error to avoid system hanging up.
++     *
++     *return Status;
++     */
++  }
++
++  LibGetTime (&EfiTime, NULL);
++  if (!IsTimeValid (&EfiTime)) {
++    EfiTime.Year    = 2015;
++    EfiTime.Month   = 1;
++    EfiTime.Day     = 1;
++    EfiTime.Hour    = 0;
++    EfiTime.Minute  = 0;
++    EfiTime.Second  = 0;
++    Status = LibSetTime (&EfiTime);
++    if (EFI_ERROR (Status)) {
++      DEBUG ((DEBUG_ERROR, "[%a]:[%dL] RTC settime Status : %r\n",
++        __FUNCTION__, __LINE__, Status));
++    }
++  }
++
++  DEBUG ((
++    DEBUG_ERROR, "Now RTC Time is : %04d-%02d-%02d %02d:%02d:%02d\n",
++    EfiTime.Year, EfiTime.Month, EfiTime.Day, EfiTime.Hour, EfiTime.Minute,
++    EfiTime.Second
++    ));
++    /*
++     * Returning ERROR on failure of RTC initilization will cause the system to hang up.
++     * So we add some debug message to indecate the RTC initilization failed,
++     * and return success to avoid system hanging up.
++     */
++  return EFI_SUCCESS;
++}
+-- 
+2.17.0
+
diff --git a/v2/v2-0012-Platform-Hisilicon-D06-Add-edk2-non-osi-component.patch b/v2/v2-0012-Platform-Hisilicon-D06-Add-edk2-non-osi-component.patch
new file mode 100644
index 0000000000..984b1b6640
--- /dev/null
+++ b/v2/v2-0012-Platform-Hisilicon-D06-Add-edk2-non-osi-component.patch
@@ -0,0 +1,149 @@ 
+From 74db81672b83c782223a1e68963e4dbb090f592d Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Sat, 21 Jul 2018 14:31:06 +0800
+Subject: [PATCH edk2-platforms v2 12/43] Platform/Hisilicon/D06: Add
+ edk2-non-osi components for D06
+
+Add PcdCoreCount to fix build issue while add binary components.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Platform/Hisilicon/D06/D06.dsc                                                 |  7 +++++++
+ Platform/Hisilicon/D06/D06.fdf                                                 | 17 +++++++++++++++++
+ Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf |  2 ++
+ 3 files changed, 26 insertions(+)
+
+diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
+index 27358f8c78..94454569f6 100644
+--- a/Platform/Hisilicon/D06/D06.dsc
++++ b/Platform/Hisilicon/D06/D06.dsc
+@@ -41,6 +41,8 @@
+ 
+   I2CLib|Silicon/Hisilicon/Library/I2CLib/I2CLib.inf
+   TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
++  IpmiCmdLib|Silicon/Hisilicon/Library/IpmiCmdLib/IpmiCmdLib.inf
++
+   NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+   DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+   HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+@@ -64,8 +66,12 @@
+ 
+   CpldIoLib|Silicon/Hisilicon/Library/CpldIoLib/CpldIoLib.inf
+ 
++  SerdesLib|Silicon/Hisilicon/Hi1620/Library/Hi1620Serdes/Hi1620SerdesLib.inf
++
+   TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
+   RealTimeClockLib|Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf
++  OemAddressMapLib|Platform/Hisilicon/D06/Library/OemAddressMapD06/OemAddressMapD06.inf
++  PlatformSysCtrlLib|Silicon/Hisilicon/Hi1620/Library/PlatformSysCtrlLibHi1620/PlatformSysCtrlLibHi1620.inf
+ 
+   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+   GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
+@@ -81,6 +87,7 @@
+   # USB Requirements
+   UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+ 
++  LpcLib|Silicon/Hisilicon/Hi1620/Library/LpcLibHi1620/LpcLib.inf
+   SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+ !if $(SECURE_BOOT_ENABLE) == TRUE
+   FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf
+index 9567ede0ad..07fe096f61 100644
+--- a/Platform/Hisilicon/D06/D06.fdf
++++ b/Platform/Hisilicon/D06/D06.fdf
+@@ -56,6 +56,7 @@ NumBlocks     = 0x40
+ 
+ 0x00000000|0x00100000
+ gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize
++FILE = Platform/Hisilicon/D06/Sec/FVMAIN_SEC.Fv
+ 
+ 0x00100000|0x00280000
+ gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+@@ -163,6 +164,7 @@ READ_LOCK_STATUS   = TRUE
+   INF MdeModulePkg/Core/Dxe/DxeMain.inf
+   INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+ 
++  INF Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.inf
+   #
+   # PI DXE Drivers producing Architectural Protocols (EFI Services)
+   #
+@@ -170,6 +172,7 @@ READ_LOCK_STATUS   = TRUE
+   INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ 
+   INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
++  INF Platform/Hisilicon/D06/Drivers/SFC/SfcDxeDriver.inf
+ 
+ 
+   INF Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
+@@ -225,10 +228,15 @@ READ_LOCK_STATUS   = TRUE
+   INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+   INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+ 
++  INF Platform/Hisilicon/D06/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf
++  INF Platform/Hisilicon/D06/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
+   INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+   INF Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
+   INF Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
++  INF Platform/Hisilicon/D06/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
++  INF Platform/Hisilicon/D06/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
+ 
++  INF Platform/Hisilicon/D06/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
+ 
+ 
+   INF Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
+@@ -246,6 +254,7 @@ READ_LOCK_STATUS   = TRUE
+   #
+   #Network
+   #
++  INF Platform/Hisilicon/D06/Drivers/Net/SnpHi1620NewDxe/SnpDxe.inf
+ 
+   INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+   INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+@@ -282,8 +291,14 @@ READ_LOCK_STATUS   = TRUE
+   INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+   INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+   INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
++  INF Platform/Hisilicon/D06/Drivers/PcieRasInitDxe/PcieRasInitDxe.inf
++  INF Platform/Hisilicon/D06/Drivers/RasInitDxe/RasInitDxe.inf
+ 
++  # VGA Driver
++  #
++  INF Platform/Hisilicon/D06/Drivers/Sm750Dxe/UefiSmi.inf
+   INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
++  INF Platform/Hisilicon/D06/Drivers/Sas/SasDxeDriver.inf
+   INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+   INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+   INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+@@ -335,6 +350,8 @@ READ_LOCK_STATUS   = TRUE
+ 
+   INF Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
+ 
++  INF Platform/Hisilicon/D06/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
++  INF Platform/Hisilicon/D06/MemoryInitPei/MemoryInitPeim.inf
+   INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+   INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+   INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+diff --git a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf b/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
+index 2275586ff3..a47806f391 100644
+--- a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
++++ b/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
+@@ -28,6 +28,7 @@
+ 
+ [Packages]
+   ArmPkg/ArmPkg.dec
++  ArmPlatformPkg/ArmPlatformPkg.dec
+   MdePkg/MdePkg.dec
+   MdeModulePkg/MdeModulePkg.dec
+   IntelFrameworkPkg/IntelFrameworkPkg.dec
+@@ -52,6 +53,7 @@
+   gEfiSmbiosProtocolGuid                       # PROTOCOL ALWAYS_CONSUMED
+ 
+ [Pcd]
++  gArmPlatformTokenSpaceGuid.PcdCoreCount
+   gHisiTokenSpaceGuid.PcdCPUInfo
+   gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
+ 
+-- 
+2.17.0
+
diff --git a/v2/v2-0013-Hisilicon-D06-Add-OemMiscLibD06.patch b/v2/v2-0013-Hisilicon-D06-Add-OemMiscLibD06.patch
new file mode 100644
index 0000000000..491a305e54
--- /dev/null
+++ b/v2/v2-0013-Hisilicon-D06-Add-OemMiscLibD06.patch
@@ -0,0 +1,751 @@ 
+From ad190a05d535c5d242a404418b14496cc323fc47 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Fri, 15 Jun 2018 17:47:45 +0800
+Subject: [PATCH edk2-platforms v2 13/43] Hisilicon/D06: Add OemMiscLibD06
+
+This library include BoardFeatureD06.c and OemMiscLibD06.c c file,
+use for several modules like PciHostBridgeLib and Smbios.
+Enlarge macro PCIEDEVICE_REPORT_MAX for D06.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Platform/Hisilicon/D06/D06.dsc                                          |   1 +
+ Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf          |  47 +++
+ Silicon/Hisilicon/Include/Library/OemMiscLib.h                          |   6 +-
+ Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c          | 432 ++++++++++++++++++++
+ Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c            | 132 ++++++
+ Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06Strings.uni |  64 +++
+ 6 files changed, 681 insertions(+), 1 deletion(-)
+
+diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
+index 94454569f6..9ca7160dad 100644
+--- a/Platform/Hisilicon/D06/D06.dsc
++++ b/Platform/Hisilicon/D06/D06.dsc
+@@ -70,6 +70,7 @@
+ 
+   TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
+   RealTimeClockLib|Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf
++  OemMiscLib|Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
+   OemAddressMapLib|Platform/Hisilicon/D06/Library/OemAddressMapD06/OemAddressMapD06.inf
+   PlatformSysCtrlLib|Silicon/Hisilicon/Hi1620/Library/PlatformSysCtrlLibHi1620/PlatformSysCtrlLibHi1620.inf
+ 
+diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
+new file mode 100644
+index 0000000000..8f68f7cec5
+--- /dev/null
++++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
+@@ -0,0 +1,47 @@
++#/** @file
++#
++#    Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++#    Copyright (c) 2018, Linaro Limited. All rights reserved.
++#
++#    This program and the accompanying materials
++#    are licensed and made available under the terms and conditions of the BSD License
++#    which accompanies this distribution. The full text of the license may be found at
++#    http://opensource.org/licenses/bsd-license.php
++#
++#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++#
++#**/
++
++[Defines]
++  INF_VERSION                    = 0x0001001A
++  BASE_NAME                      = OemMiscLib
++  FILE_GUID                      = 3002911C-C160-4C46-93BB-782846673EEA
++  MODULE_TYPE                    = BASE
++  VERSION_STRING                 = 1.0
++  LIBRARY_CLASS                  = OemMiscLib
++
++[Sources.common]
++  BoardFeatureD06.c
++  BoardFeatureD06Strings.uni
++  OemMiscLibD06.c
++
++[Packages]
++  ArmPkg/ArmPkg.dec
++  MdeModulePkg/MdeModulePkg.dec
++  MdePkg/MdePkg.dec
++  Silicon/Hisilicon/HisiPkg.dec
++
++[LibraryClasses]
++  PcdLib
++  SerdesLib
++  TimerLib
++
++[Ppis]
++  gEfiPeiReadOnlyVariable2PpiGuid   ## SOMETIMES_CONSUMES
++
++[Pcd]
++  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
++  gHisiTokenSpaceGuid.PcdIsMPBoot
++  gHisiTokenSpaceGuid.PcdSocketMask
++  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+diff --git a/Silicon/Hisilicon/Include/Library/OemMiscLib.h b/Silicon/Hisilicon/Include/Library/OemMiscLib.h
+index 87cb498dd7..efecb9aa77 100644
+--- a/Silicon/Hisilicon/Include/Library/OemMiscLib.h
++++ b/Silicon/Hisilicon/Include/Library/OemMiscLib.h
+@@ -22,7 +22,11 @@
+ #include <PlatformArch.h>
+ #include <Library/I2CLib.h>
+ 
+-#define PCIEDEVICE_REPORT_MAX      4
++#define PCIEDEVICE_REPORT_MAX      8
++#define MAX_PROCESSOR_SOCKETS      MAX_SOCKET
++#define MAX_MEMORY_CHANNELS        MAX_CHANNEL
++#define MAX_DIMM_PER_CHANNEL       MAX_DIMM
++
+ typedef struct _REPORT_PCIEDIDVID2BMC{
+     UINTN   Bus;
+     UINTN   Device;
+diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c
+new file mode 100644
+index 0000000000..7e3f2e2a0e
+--- /dev/null
++++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c
+@@ -0,0 +1,432 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++#include <Uefi.h>
++#include <IndustryStandard/SmBios.h>
++#include <Library/BaseMemoryLib.h>
++#include <Library/DebugLib.h>
++#include <Library/HiiLib.h>
++#include <Library/I2CLib.h>
++#include <Library/IoLib.h>
++#include <Library/OemMiscLib.h>
++#include <Library/SerdesLib.h>
++#include <Protocol/Smbios.h>
++
++#include <PlatformArch.h>
++
++I2C_DEVICE gRtcDevice = {
++  .Socket = 0,
++  .Port = 5,
++  .DeviceType = DEVICE_TYPE_SPD,
++  .SlaveDeviceAddress = 0x68
++};
++
++SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] =
++{
++  {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
++};
++
++SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] =
++{
++  {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
++};
++
++SERDES_PARAM gSerdesParamNA = {
++  .Hilink0Mode = EmHilink0Hccs1X8Width16,
++  .Hilink1Mode = EmHilink1Hccs0X8Width16,
++  .Hilink2Mode = EmHilink2Pcie2X8,
++  .Hilink3Mode = 0x0,
++  .Hilink4Mode = 0xF,
++  .Hilink5Mode = EmHilink5Sas1X4,
++  .Hilink6Mode = 0x0,
++  .UseSsc      = 0,
++};
++
++SERDES_PARAM gSerdesParamNB = {
++  .Hilink0Mode = EmHilink0Pcie1X8,
++  .Hilink1Mode = EmHilink1Pcie0X8,
++  .Hilink2Mode = EmHilink2Sas0X8,
++  .Hilink3Mode = 0x0,
++  .Hilink4Mode = 0xF,
++  .Hilink5Mode = EmHilink5Pcie2X2Pcie3X2,
++  .Hilink6Mode = 0xF,
++  .UseSsc      = 0,
++};
++
++SERDES_PARAM gSerdesParamS1NA = {
++  .Hilink0Mode = EmHilink0Hccs1X8Width16,
++  .Hilink1Mode = EmHilink1Hccs0X8Width16,
++  .Hilink2Mode = EmHilink2Pcie2X8,
++  .Hilink3Mode = 0x0,
++  .Hilink4Mode = 0xF,
++  .Hilink5Mode = EmHilink5Sas1X4,
++  .Hilink6Mode = 0x0,
++  .UseSsc      = 0,
++};
++
++SERDES_PARAM gSerdesParamS1NB = {
++  .Hilink0Mode = EmHilink0Pcie1X8,
++  .Hilink1Mode = EmHilink1Pcie0X8,
++  .Hilink2Mode = EmHilink2Sas0X8,
++  .Hilink3Mode = 0x0,
++  .Hilink4Mode = 0xF,
++  .Hilink5Mode = EmHilink5Pcie2X2Pcie3X2,
++  .Hilink6Mode = 0xF,
++  .UseSsc      = 0,
++};
++
++
++EFI_STATUS
++OemGetSerdesParam (
++  OUT SERDES_PARAM *ParamA,
++  OUT SERDES_PARAM *ParamB,
++  IN  UINT32       SocketId
++ )
++{
++  if (NULL == ParamA) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
++    return EFI_INVALID_PARAMETER;
++  } if (NULL == ParamB) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
++    return EFI_INVALID_PARAMETER;
++  }
++
++  if (0 == SocketId) {
++    (VOID) CopyMem (ParamA, &gSerdesParamNA, sizeof (*ParamA));
++    (VOID) CopyMem (ParamB, &gSerdesParamNB, sizeof (*ParamB));
++  } else {
++    (VOID) CopyMem (ParamA, &gSerdesParamS1NA, sizeof (*ParamA));
++    (VOID) CopyMem (ParamB, &gSerdesParamS1NB, sizeof (*ParamB));
++  }
++
++  return EFI_SUCCESS;
++}
++
++VOID
++OemPcieResetAndOffReset (
++  VOID
++  )
++{
++  return;
++}
++
++SMBIOS_TABLE_TYPE9 gPcieSlotInfo[] = {
++  // PCIe0 Slot 1
++  {
++    {                                       // Hdr
++        EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
++        0,                                  // Length,
++        0                                   // Handle
++    },
++    1,                                      // SlotDesignation
++    SlotTypePciExpressX16,                  // SlotType
++    SlotDataBusWidth16X,                    // SlotDataBusWidth
++    SlotUsageAvailable,                     // SlotUsage
++    SlotLengthOther,                        // SlotLength
++    0x0001,                                 // SlotId
++    {                                       // SlotCharacteristics1
++        0,                                  // CharacteristicsUnknown  :1;
++        0,                                  // Provides50Volts         :1;
++        0,                                  // Provides33Volts         :1;
++        0,                                  // SharedSlot              :1;
++        0,                                  // PcCard16Supported       :1;
++        0,                                  // CardBusSupported        :1;
++        0,                                  // ZoomVideoSupported      :1;
++        0                                   // ModemRingResumeSupported:1;
++    },
++    {                                       // SlotCharacteristics2
++        0,                                  // PmeSignalSupported      :1;
++        0,                                  // HotPlugDevicesSupported :1;
++        0,                                  // SmbusSignalSupported    :1;
++        0                                   // Reserved                :5;
++    },
++    0x00,                                   // SegmentGroupNum
++    0x00,                                   // BusNum
++    0                                       // DevFuncNum
++  },
++  {
++      {                                       // Hdr
++          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
++          0,                                  // Length,
++          0                                   // Handle
++      },
++      1,                                      // SlotDesignation
++      SlotTypePciExpressX8,                   // SlotType
++      SlotDataBusWidth8X,                     // SlotDataBusWidth
++      SlotUsageAvailable,                     // SlotUsage
++      SlotLengthOther,                        // SlotLength
++      0x0002,                                 // SlotId
++      {                                       // SlotCharacteristics1
++          0,                                  // CharacteristicsUnknown  :1;
++          0,                                  // Provides50Volts         :1;
++          0,                                  // Provides33Volts         :1;
++          0,                                  // SharedSlot              :1;
++          0,                                  // PcCard16Supported       :1;
++          0,                                  // CardBusSupported        :1;
++          0,                                  // ZoomVideoSupported      :1;
++          0                                   // ModemRingResumeSupported:1;
++      },
++      {                                       // SlotCharacteristics2
++          0,                                  // PmeSignalSupported      :1;
++          0,                                  // HotPlugDevicesSupported :1;
++          0,                                  // SmbusSignalSupported    :1;
++          0                                   // Reserved                :5;
++      },
++      0x00,                                   // SegmentGroupNum
++      0x00,                                   // BusNum
++      0                                       // DevFuncNum
++  },
++  {
++      {                                       // Hdr
++          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
++          0,                                  // Length,
++          0                                   // Handle
++      },
++      1,                                      // SlotDesignation
++      SlotTypePciExpressX8,                   // SlotType
++      SlotDataBusWidth8X,                     // SlotDataBusWidth
++      SlotUsageAvailable,                     // SlotUsage
++      SlotLengthOther,                        // SlotLength
++      0x0003,                                 // SlotId
++      {                                       // SlotCharacteristics1
++          0,                                  // CharacteristicsUnknown  :1;
++          0,                                  // Provides50Volts         :1;
++          0,                                  // Provides33Volts         :1;
++          0,                                  // SharedSlot              :1;
++          0,                                  // PcCard16Supported       :1;
++          0,                                  // CardBusSupported        :1;
++          0,                                  // ZoomVideoSupported      :1;
++          0                                   // ModemRingResumeSupported:1;
++      },
++      {                                       // SlotCharacteristics2
++          0,                                  // PmeSignalSupported      :1;
++          0,                                  // HotPlugDevicesSupported :1;
++          0,                                  // SmbusSignalSupported    :1;
++          0                                   // Reserved                :5;
++      },
++      0x00,                                   // SegmentGroupNum
++      0x00,                                   // BusNum
++      0                                       // DevFuncNum
++  },
++
++
++  {
++      {                                       // Hdr
++          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
++          0,                                  // Length,
++          0                                   // Handle
++      },
++      1,                                      // SlotDesignation
++      SlotTypePciExpressX8,                   // SlotType
++      SlotDataBusWidth8X,                     // SlotDataBusWidth
++      SlotUsageAvailable,                     // SlotUsage
++      SlotLengthOther,                        // SlotLength
++      0x0004,                                 // SlotId
++      {                                       // SlotCharacteristics1
++          0,                                  // CharacteristicsUnknown  :1;
++          0,                                  // Provides50Volts         :1;
++          0,                                  // Provides33Volts         :1;
++          0,                                  // SharedSlot              :1;
++          0,                                  // PcCard16Supported       :1;
++          0,                                  // CardBusSupported        :1;
++          0,                                  // ZoomVideoSupported      :1;
++          0                                   // ModemRingResumeSupported:1;
++      },
++      {                                       // SlotCharacteristics2
++          0,                                  // PmeSignalSupported      :1;
++          0,                                  // HotPlugDevicesSupported :1;
++          0,                                  // SmbusSignalSupported    :1;
++          0                                   // Reserved                :5;
++      },
++      0x00,                                   // SegmentGroupNum
++      0x00,                                   // BusNum
++      0                                       // DevFuncNum
++  },
++
++  {
++      {                                       // Hdr
++          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
++          0,                                  // Length,
++          0                                   // Handle
++      },
++      1,                                      // SlotDesignation
++      SlotTypePciExpressX16,                  // SlotType
++      SlotDataBusWidth16X,                    // SlotDataBusWidth
++      SlotUsageAvailable,                     // SlotUsage
++      SlotLengthOther,                        // SlotLength
++      0x0005,                                 // SlotId
++      {                                       // SlotCharacteristics1
++          0,                                  // CharacteristicsUnknown  :1;
++          0,                                  // Provides50Volts         :1;
++          0,                                  // Provides33Volts         :1;
++          0,                                  // SharedSlot              :1;
++          0,                                  // PcCard16Supported       :1;
++          0,                                  // CardBusSupported        :1;
++          0,                                  // ZoomVideoSupported      :1;
++          0                                   // ModemRingResumeSupported:1;
++      },
++      {                                       // SlotCharacteristics2
++          0,                                  // PmeSignalSupported      :1;
++          0,                                  // HotPlugDevicesSupported :1;
++          0,                                  // SmbusSignalSupported    :1;
++          0                                   // Reserved                :5;
++      },
++      0x00,                                   // SegmentGroupNum
++      0x00,                                   // BusNum
++      0                                       // DevFuncNum
++  },
++  {
++      {                                       // Hdr
++          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
++          0,                                  // Length,
++          0                                   // Handle
++      },
++      1,                                      // SlotDesignation
++      SlotTypePciExpressX8,                   // SlotType
++      SlotDataBusWidth8X,                     // SlotDataBusWidth
++      SlotUsageAvailable,                     // SlotUsage
++      SlotLengthOther,                        // SlotLength
++      0x0006,                                 // SlotId
++      {                                       // SlotCharacteristics1
++          0,                                  // CharacteristicsUnknown  :1;
++          0,                                  // Provides50Volts         :1;
++          0,                                  // Provides33Volts         :1;
++          0,                                  // SharedSlot              :1;
++          0,                                  // PcCard16Supported       :1;
++          0,                                  // CardBusSupported        :1;
++          0,                                  // ZoomVideoSupported      :1;
++          0                                   // ModemRingResumeSupported:1;
++      },
++      {                                       // SlotCharacteristics2
++          0,                                  // PmeSignalSupported      :1;
++          0,                                  // HotPlugDevicesSupported :1;
++          0,                                  // SmbusSignalSupported    :1;
++          0                                   // Reserved                :5;
++      },
++      0x00,                                   // SegmentGroupNum
++      0x00,                                   // BusNum
++      0                                       // DevFuncNum
++  },
++  {
++      {                                       // Hdr
++          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
++          0,                                  // Length,
++          0                                   // Handle
++      },
++      1,                                      // SlotDesignation
++      SlotTypePciExpressX8,                   // SlotType
++      SlotDataBusWidth8X,                     // SlotDataBusWidth
++      SlotUsageAvailable,                     // SlotUsage
++      SlotLengthOther,                        // SlotLength
++      0x0007,                                 // SlotId
++      {                                       // SlotCharacteristics1
++          0,                                  // CharacteristicsUnknown  :1;
++          0,                                  // Provides50Volts         :1;
++          0,                                  // Provides33Volts         :1;
++          0,                                  // SharedSlot              :1;
++          0,                                  // PcCard16Supported       :1;
++          0,                                  // CardBusSupported        :1;
++          0,                                  // ZoomVideoSupported      :1;
++          0                                   // ModemRingResumeSupported:1;
++      },
++      {                                       // SlotCharacteristics2
++          0,                                  // PmeSignalSupported      :1;
++          0,                                  // HotPlugDevicesSupported :1;
++          0,                                  // SmbusSignalSupported    :1;
++          0                                   // Reserved                :5;
++      },
++      0x00,                                   // SegmentGroupNum
++      0x00,                                   // BusNum
++      0                                       // DevFuncNum
++  },
++  {
++      {                                       // Hdr
++          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
++          0,                                  // Length,
++          0                                   // Handle
++      },
++      1,                                      // SlotDesignation
++      SlotTypePciExpressX8,                   // SlotType
++      SlotDataBusWidth8X,                     // SlotDataBusWidth
++      SlotUsageAvailable,                     // SlotUsage
++      SlotLengthOther,                        // SlotLength
++      0x0008,                                 // SlotId
++      {                                       // SlotCharacteristics1
++          0,                                  // CharacteristicsUnknown  :1;
++          0,                                  // Provides50Volts         :1;
++          0,                                  // Provides33Volts         :1;
++          0,                                  // SharedSlot              :1;
++          0,                                  // PcCard16Supported       :1;
++          0,                                  // CardBusSupported        :1;
++          0,                                  // ZoomVideoSupported      :1;
++          0                                   // ModemRingResumeSupported:1;
++      },
++      {                                       // SlotCharacteristics2
++          0,                                  // PmeSignalSupported      :1;
++          0,                                  // HotPlugDevicesSupported :1;
++          0,                                  // SmbusSignalSupported    :1;
++          0                                   // Reserved                :5;
++      },
++      0x00,                                   // SegmentGroupNum
++      0x00,                                   // BusNum
++      0                                       // DevFuncNum
++  },
++
++  };
++
++UINT8
++OemGetPcieSlotNumber (
++  VOID
++  )
++{
++  return sizeof (gPcieSlotInfo) / sizeof (SMBIOS_TABLE_TYPE9);
++}
++
++EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = {
++  {{STRING_TOKEN(STR_LEMON_C10_DIMM_000), STRING_TOKEN(STR_LEMON_C10_DIMM_001)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_010), STRING_TOKEN(STR_LEMON_C10_DIMM_011)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_020), STRING_TOKEN(STR_LEMON_C10_DIMM_021)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_030), STRING_TOKEN(STR_LEMON_C10_DIMM_031)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_040), STRING_TOKEN(STR_LEMON_C10_DIMM_041)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_050), STRING_TOKEN(STR_LEMON_C10_DIMM_051)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_060), STRING_TOKEN(STR_LEMON_C10_DIMM_061)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_070), STRING_TOKEN(STR_LEMON_C10_DIMM_071)}},
++
++  {{STRING_TOKEN(STR_LEMON_C10_DIMM_100), STRING_TOKEN(STR_LEMON_C10_DIMM_101)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_110), STRING_TOKEN(STR_LEMON_C10_DIMM_111)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_120), STRING_TOKEN(STR_LEMON_C10_DIMM_121)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_130), STRING_TOKEN(STR_LEMON_C10_DIMM_131)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_140), STRING_TOKEN(STR_LEMON_C10_DIMM_141)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_150), STRING_TOKEN(STR_LEMON_C10_DIMM_151)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_160), STRING_TOKEN(STR_LEMON_C10_DIMM_161)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_170), STRING_TOKEN(STR_LEMON_C10_DIMM_171)}}
++};
++
++EFI_HII_HANDLE
++EFIAPI
++OemGetPackages (
++  VOID
++  )
++{
++  return HiiAddPackages (
++           &gEfiCallerIdGuid,
++           NULL,
++           OemMiscLibStrings,
++           NULL,
++           NULL
++           );
++}
++
++
+diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c
+new file mode 100644
+index 0000000000..2cd360d49f
+--- /dev/null
++++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c
+@@ -0,0 +1,132 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++#include <Uefi.h>
++#include <PlatformArch.h>
++#include <Library/DebugLib.h>
++#include <Library/IoLib.h>
++#include <Library/LpcLib.h>
++#include <Library/OemAddressMapLib.h>
++#include <Library/OemMiscLib.h>
++#include <Library/PcdLib.h>
++#include <Library/PlatformSysCtrlLib.h>
++#include <Library/SerdesLib.h>
++#include <Library/SerialPortLib.h>
++#include <Library/TimerLib.h>
++
++REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {
++  {67,0,0,0},
++  {225,0,0,3},
++  {0xFFFF,0xFFFF,0xFFFF,0xFFFF},
++  {0xFFFF,0xFFFF,0xFFFF,0xFFFF}
++};
++
++// Right now we only support 1P
++BOOLEAN
++OemIsSocketPresent (
++  UINTN Socket
++  )
++{
++  UINT32 SocketMask = PcdGet32 (PcdSocketMask);
++  return (BOOLEAN)((SocketMask & (1 << Socket)) ? TRUE : FALSE);
++}
++
++
++UINTN
++OemGetSocketNumber (
++  VOID
++  )
++{
++  if(!OemIsMpBoot ()) {
++    return 1;
++  }
++
++  return MAX_PROCESSOR_SOCKETS;
++}
++
++
++UINTN
++OemGetDdrChannel (
++  VOID
++  )
++{
++  return MAX_MEMORY_CHANNELS;
++}
++
++
++UINTN
++OemGetDimmSlot (
++  UINTN Socket,
++  UINTN Channel
++  )
++{
++  return MAX_DIMM_PER_CHANNEL;
++}
++
++
++VOID
++CoreSelectBoot (
++  VOID
++  )
++{
++  if (!PcdGet64 (PcdTrustedFirmwareEnable))
++  {
++    StartupAp ();
++  }
++
++  return;
++}
++
++BOOLEAN
++OemIsMpBoot (
++  VOID
++  )
++{
++  return PcdGet32 (PcdIsMPBoot);
++}
++
++VOID
++OemLpcInit (
++  VOID
++  )
++{
++  LpcInit ();
++  return;
++}
++
++UINT32
++OemIsWarmBoot (
++  VOID
++  )
++{
++  return 0;
++}
++
++VOID
++OemBiosSwitch (
++  UINT32 Master
++  )
++{
++  (VOID)Master;
++  return;
++}
++
++BOOLEAN
++OemIsNeedDisableExpanderBuffer (
++  VOID
++  )
++{
++  return TRUE;
++}
+diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06Strings.uni b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06Strings.uni
+new file mode 100644
+index 0000000000..046fa05dff
+--- /dev/null
++++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06Strings.uni
+@@ -0,0 +1,64 @@
++// *++
++//
++// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
++//
++// This program and the accompanying materials
++// are licensed and made available under the terms and conditions of the BSD License
++// which accompanies this distribution.  The full text of the license may be found at
++// http://opensource.org/licenses/bsd-license.php
++//
++// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++//
++// --*/
++
++/=#
++
++#langdef en-US "English"
++
++//
++// Begin English Language Strings
++//
++#string STR_MEMORY_SUBCLASS_UNKNOWN    #language en-US  "Unknown"
++
++//
++// DIMM Device Locator strings
++
++// D06
++#string STR_LEMON_C10_DIMM_000     #language en-US "J5"
++#string STR_LEMON_C10_DIMM_001     #language en-US "J6"
++#string STR_LEMON_C10_DIMM_010     #language en-US "J7"
++#string STR_LEMON_C10_DIMM_011     #language en-US "J8"
++#string STR_LEMON_C10_DIMM_020     #language en-US "J9"
++#string STR_LEMON_C10_DIMM_021     #language en-US "J10"
++#string STR_LEMON_C10_DIMM_030     #language en-US "J11"
++#string STR_LEMON_C10_DIMM_031     #language en-US "J12"
++#string STR_LEMON_C10_DIMM_040     #language en-US "J13"
++#string STR_LEMON_C10_DIMM_041     #language en-US "J14"
++#string STR_LEMON_C10_DIMM_050     #language en-US "J15"
++#string STR_LEMON_C10_DIMM_051     #language en-US "J16"
++#string STR_LEMON_C10_DIMM_060     #language en-US "J17"
++#string STR_LEMON_C10_DIMM_061     #language en-US "J18"
++#string STR_LEMON_C10_DIMM_070     #language en-US "J19"
++#string STR_LEMON_C10_DIMM_071     #language en-US "J20"
++#string STR_LEMON_C10_DIMM_100     #language en-US "J21"
++#string STR_LEMON_C10_DIMM_101     #language en-US "J22"
++#string STR_LEMON_C10_DIMM_110     #language en-US "J23"
++#string STR_LEMON_C10_DIMM_111     #language en-US "J24"
++#string STR_LEMON_C10_DIMM_120     #language en-US "J25"
++#string STR_LEMON_C10_DIMM_121     #language en-US "J26"
++#string STR_LEMON_C10_DIMM_130     #language en-US "J27"
++#string STR_LEMON_C10_DIMM_131     #language en-US "J28"
++#string STR_LEMON_C10_DIMM_140     #language en-US "J29"
++#string STR_LEMON_C10_DIMM_141     #language en-US "J30"
++#string STR_LEMON_C10_DIMM_150     #language en-US "J31"
++#string STR_LEMON_C10_DIMM_151     #language en-US "J32"
++#string STR_LEMON_C10_DIMM_160     #language en-US "J33"
++#string STR_LEMON_C10_DIMM_161     #language en-US "J34"
++#string STR_LEMON_C10_DIMM_170     #language en-US "J35"
++#string STR_LEMON_C10_DIMM_171     #language en-US "J36"
++
++//
++// End English Language Strings
++//
++
+-- 
+2.17.0
+
diff --git a/v2/v2-0014-Silicon-Hisilicon-D06-Wait-for-all-disk-ready.patch b/v2/v2-0014-Silicon-Hisilicon-D06-Wait-for-all-disk-ready.patch
new file mode 100644
index 0000000000..8653ee9159
--- /dev/null
+++ b/v2/v2-0014-Silicon-Hisilicon-D06-Wait-for-all-disk-ready.patch
@@ -0,0 +1,132 @@ 
+From 1bf2ad05d4558134248da8bd92072a15db3a6de1 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Sat, 12 May 2018 17:26:36 +0800
+Subject: [PATCH edk2-platforms v2 14/43] Silicon/Hisilicon/D06: Wait for all
+ disk ready
+
+This patch is relative to D06 SasDxe driver. The SasDxe set a
+variable to notice this libray. Here Wait for all disk ready
+for 15S at most.
+
+D06:
+For using straight-through hard disk backboard, some disk need
+15 seconds to ready. Actually, wait less 15 seconds here(minus
+the time from end of SAS driver to here).
+For using expander backboard, wait less 6 seconds here(minus
+the time from end of SAS driver to here).
+
+D03/D05:
+As Sas driver don't write the SASDiskInfo variable, D03/D05 will
+break the loop, so it no waiting here.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Silicon/Hisilicon/HisiPkg.dec                                               |  1 +
+ Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf |  2 +
+ Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c               | 43 ++++++++++++++++++++
+ 3 files changed, 46 insertions(+)
+
+diff --git a/Silicon/Hisilicon/HisiPkg.dec b/Silicon/Hisilicon/HisiPkg.dec
+index 35bea970ec..b56a6a6af7 100644
+--- a/Silicon/Hisilicon/HisiPkg.dec
++++ b/Silicon/Hisilicon/HisiPkg.dec
+@@ -45,6 +45,7 @@
+ 
+   gHisiEfiMemoryMapGuid  = {0xf8870015, 0x6994, 0x4b98, {0x95, 0xa2, 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f}}
+   gVersionInfoHobGuid = {0xe13a14c, 0x859c, 0x4f22, {0x82, 0xbd, 0x18, 0xe, 0xe1, 0x42, 0x12, 0xbf}}
++  gHisiOemVariableGuid = {0xac62b9a5, 0x9939, 0x41d3, {0xff, 0x5c, 0xc5, 0x80, 0x32, 0x7d, 0x9b, 0x29}}
+   gOemBootVariableGuid = {0xb7784577, 0x5aaf, 0x4557, {0xa1, 0x99, 0xd4, 0xa4, 0x2f, 0x45, 0x06, 0xf8}}
+   gEfiHisiSocControllerGuid = {0xee369cc3, 0xa743, 0x5382, {0x75, 0x64, 0x53, 0xe4, 0x31, 0x19, 0x38, 0x35}}
+ 
+diff --git a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+index 7a53befc44..a093f13fb0 100644
+--- a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
++++ b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+@@ -49,6 +49,7 @@
+   MemoryAllocationLib
+   PcdLib
+   PrintLib
++  TimerLib
+   UefiBootManagerLib
+   UefiBootServicesTableLib
+   UefiLib
+@@ -67,6 +68,7 @@
+ [Guids]
+   gEfiEndOfDxeEventGroupGuid
+   gEfiTtyTermGuid
++  gHisiOemVariableGuid
+ 
+ [Protocols]
+   gEfiGenericMemTestProtocolGuid
+diff --git a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c
+index 7dd5ba615c..d5f6d78fa4 100644
+--- a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c
++++ b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c
+@@ -20,6 +20,7 @@
+ #include <Library/BmcConfigBootLib.h>
+ #include <Library/DevicePathLib.h>
+ #include <Library/PcdLib.h>
++#include <Library/TimerLib.h>
+ #include <Library/UefiBootManagerLib.h>
+ #include <Library/UefiLib.h>
+ #include <Protocol/DevicePath.h>
+@@ -554,6 +555,47 @@ PlatformBootManagerBeforeConsole (
+   PlatformRegisterOptionsAndKeys ();
+ }
+ 
++STATIC
++VOID
++WaitForDiskReady (
++  )
++{
++  EFI_STATUS                Status;
++  UINT32                    Index;
++  UINTN                     DataSize;
++  UINT32                    DiskInfo;
++  UINT8                     IsFinished;
++
++  Status = EFI_NOT_FOUND;
++  DataSize = sizeof (UINT32);
++  // Wait for 15 seconds at most.
++  for (Index = 0; Index < 15; Index++) {
++    Status = gRT->GetVariable (
++                    L"SASDiskInfo",
++                    &gHisiOemVariableGuid,
++                    NULL,
++                    &DataSize,
++                    &DiskInfo
++                    );
++    if (EFI_ERROR(Status)) {
++      DEBUG ((DEBUG_ERROR, "Get DiskInfo:%r\n", Status));
++      break;
++    }
++
++    IsFinished = (UINT8)(DiskInfo >> 24);
++    if (IsFinished) {
++      break;
++    }
++    DEBUG ((DEBUG_ERROR, "%a", Index == 0 ? "Wait for disk." : "."));
++    MicroSecondDelay(1000 * 1000);
++  }
++
++  if (!EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "DiskInfo:%x\n", DiskInfo));
++    EfiBootManagerConnectAll ();
++  }
++}
++
+ /**
+   Do the platform specific action after the console is ready
+   Possible things that can be done in PlatformBootManagerAfterConsole:
+@@ -583,6 +625,7 @@ PlatformBootManagerAfterConsole (
+   // Connect the rest of the devices.
+   //
+   EfiBootManagerConnectAll ();
++  WaitForDiskReady ();
+ 
+   //
+   // Enumerate all possible boot options.
+-- 
+2.17.0
+
diff --git a/v2/v2-0015-Silicon-Hisilicon-Acpi-Unify-HisiAcipPlatformDxe.patch b/v2/v2-0015-Silicon-Hisilicon-Acpi-Unify-HisiAcipPlatformDxe.patch
new file mode 100644
index 0000000000..42a1c605ee
--- /dev/null
+++ b/v2/v2-0015-Silicon-Hisilicon-Acpi-Unify-HisiAcipPlatformDxe.patch
@@ -0,0 +1,126 @@ 
+From cb2f00d4a6634df9d4ae16cc0ec877a930de1604 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Fri, 22 Jun 2018 14:09:41 +0800
+Subject: [PATCH edk2-platforms v2 15/43] Silicon/Hisilicon/Acpi: Unify
+ HisiAcipPlatformDxe
+
+The EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE struct is used by
+UpdateAcpiTable.c and Srat aslc. The struct may be different
+according to chips, so move some macro to PlatformArch.h.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Silicon/Hisilicon/Hi1610/Include/PlatformArch.h                 |  6 ++++
+ Silicon/Hisilicon/Hi1620/Include/PlatformArch.h                 |  6 ++++
+ Silicon/Hisilicon/Include/Library/AcpiNextLib.h                 | 31 ++++++++++++++------
+ Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c |  2 --
+ 4 files changed, 34 insertions(+), 11 deletions(-)
+
+diff --git a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
+index f39ae0748c..1ebddca4e5 100644
+--- a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
++++ b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
+@@ -30,6 +30,12 @@
+ // Max NUMA node number for each node type
+ #define MAX_NUM_PER_TYPE 8
+ 
++// for acpi
++#define NODE_IN_SOCKET                                  2
++#define CORE_NUM_PER_SOCKET                             32
++#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT        10
++#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT       8
++
+ #define S1_BASE               0x40000000000
+ 
+ #define RASC_BASE                (0x5000)
+diff --git a/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h
+index 9539cfdada..f3ad45f6c6 100644
+--- a/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h
++++ b/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h
+@@ -57,5 +57,11 @@
+   EFI_ACPI_ARM_CREATOR_REVISION   /* UINT32  CreatorRevision */ \
+   }
+ 
++// for acpi
++#define NODE_IN_SOCKET                                  2
++#define CORE_NUM_PER_SOCKET                             48
++#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT        16
++#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT       1
++
+ #endif
+ 
+diff --git a/Silicon/Hisilicon/Include/Library/AcpiNextLib.h b/Silicon/Hisilicon/Include/Library/AcpiNextLib.h
+index fd05a3b960..2abffb65fc 100644
+--- a/Silicon/Hisilicon/Include/Library/AcpiNextLib.h
++++ b/Silicon/Hisilicon/Include/Library/AcpiNextLib.h
+@@ -19,6 +19,21 @@
+ #ifndef __ACPI_NEXT_LIB_H__
+ #define __ACPI_NEXT_LIB_H__
+ 
++#include <PlatformArch.h>
++
++///
++/// ITS Affinity Structure Definition
++///
++#pragma pack(1)
++typedef struct {
++  UINT8   Type;
++  UINT8   Length;
++  UINT32  ProximityDomain;
++  UINT16  Reserved;
++  UINT32  ItsHwId;
++} EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE;
++#pragma pack()
++
+ #define EFI_ACPI_6_1_GIC_ITS_INIT(GicITSHwId, GicITSBase) \
+   { \
+     EFI_ACPI_6_1_GIC_ITS, sizeof (EFI_ACPI_6_1_GIC_ITS_STRUCTURE), EFI_ACPI_RESERVED_WORD, \
+@@ -42,8 +57,8 @@
+ #define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(                                               \
+     ProximityDomain, ItsId)                                                                     \
+   {                                                                                             \
+-    4, sizeof (EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE), ProximityDomain,                           \
+-    {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, ItsId                                                               \
++    4, sizeof (EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE), ProximityDomain,                           \
++    EFI_ACPI_RESERVED_WORD, ItsId                                                               \
+   }
+ 
+ #define EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(                                              \
+@@ -75,15 +90,13 @@
+ // Define the number of each table type.
+ // This is where the table layout is modified.
+ //
+-#define EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT  64
+-#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT                10
+-#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT               8
++#define EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT  (MAX_SOCKET*CORE_NUM_PER_SOCKET)
+ 
+ typedef struct {
+-  EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER          Header;
+-  EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE                      Memory[EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT];
+-  EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE                        Gicc[EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT];
+-  EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE                     Its[EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT];
++  EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER          Header;
++  EFI_ACPI_6_2_MEMORY_AFFINITY_STRUCTURE                      Memory[EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT];
++  EFI_ACPI_6_2_GICC_AFFINITY_STRUCTURE                        Gicc[EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT];
++  EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE                         Its[EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT];
+ } EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE;
+ 
+ #pragma pack()
+diff --git a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c
+index f5869841dc..54f49977c3 100644
+--- a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c
++++ b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c
+@@ -20,8 +20,6 @@
+ #include <Library/UefiBootServicesTableLib.h>
+ #include <Library/UefiLib.h>
+ 
+-#define CORE_NUM_PER_SOCKET  32
+-#define NODE_IN_SOCKET       2
+ #define CORECOUNT(X) ((X) * CORE_NUM_PER_SOCKET)
+ 
+ STATIC
+-- 
+2.17.0
+
diff --git a/v2/v2-0016-Hisilicon-D06-Add-Debug-Serial-Port-Init-Driver.patch b/v2/v2-0016-Hisilicon-D06-Add-Debug-Serial-Port-Init-Driver.patch
new file mode 100644
index 0000000000..39d0253529
--- /dev/null
+++ b/v2/v2-0016-Hisilicon-D06-Add-Debug-Serial-Port-Init-Driver.patch
@@ -0,0 +1,172 @@ 
+From 476730eb3dc5807555d4908abc39f2a5becc130c Mon Sep 17 00:00:00 2001
+From: Heyi Guo <heyi.guo@linaro.org>
+Date: Mon, 7 May 2018 15:45:38 +0800
+Subject: [PATCH edk2-platforms v2 16/43] Hisilicon/D06: Add Debug Serial Port
+ Init Driver
+
+Hi1620 have two physical PL011 serial ports on the board,
+one for serial port console (described by ACPI SPCR) and
+the other for standard debug port (described by ACPI DBG2).
+This driver is to initialize the debug UART, not the serial
+console.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
+---
+ Platform/Hisilicon/D06/D06.dsc                                                               |  1 +
+ Platform/Hisilicon/D06/D06.fdf                                                               |  1 +
+ Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf | 48 +++++++++++++++
+ Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.c   | 64 ++++++++++++++++++++
+ 4 files changed, 114 insertions(+)
+
+diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
+index 9ca7160dad..20d2d2a1b4 100644
+--- a/Platform/Hisilicon/D06/D06.dsc
++++ b/Platform/Hisilicon/D06/D06.dsc
+@@ -422,6 +422,7 @@
+   # Memory test
+   #
+   MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
++  Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf
+   MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+   MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+   MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf
+index 07fe096f61..8cac126ccf 100644
+--- a/Platform/Hisilicon/D06/D06.fdf
++++ b/Platform/Hisilicon/D06/D06.fdf
+@@ -303,6 +303,7 @@ READ_LOCK_STATUS   = TRUE
+   INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+   INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ 
++  INF Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf
+   INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+   #
+   # Build Shell from latest source code instead of prebuilt binary
+diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf b/Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf
+new file mode 100644
+index 0000000000..8c91bdf0f4
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf
+@@ -0,0 +1,48 @@
++#/** @file
++#
++#    Copyright (c) 2016 - 2018, Hisilicon Limited. All rights reserved.
++#    Copyright (c) 2016 - 2018, Linaro Limited. All rights reserved.
++#
++#    This program and the accompanying materials
++#    are licensed and made available under the terms and conditions of the BSD License
++#    which accompanies this distribution. The full text of the license may be found at
++#    http://opensource.org/licenses/bsd-license.php
++#
++#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++#
++#**/
++
++[Defines]
++  INF_VERSION                    = 0x0001001A
++  BASE_NAME                      = Pl011DebugSerialPortInitDxe
++  FILE_GUID                      = 16D53E86-7EA4-47bd-861F-511EA9B8ABE0
++  MODULE_TYPE                    = DXE_DRIVER
++  VERSION_STRING                 = 1.0
++  ENTRY_POINT                    = SerialPortEntry
++
++[Sources.common]
++  Pl011DebugSerialPortInitDxe.c
++
++
++[Packages]
++  ArmPlatformPkg/ArmPlatformPkg.dec
++  MdeModulePkg/MdeModulePkg.dec
++  MdePkg/MdePkg.dec
++  Silicon/Hisilicon/HisiPkg.dec
++
++[LibraryClasses]
++  BaseLib
++  UefiDriverEntryPoint
++
++[Pcd]
++  gArmPlatformTokenSpaceGuid.PL011UartClkInHz
++  gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
++  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
++  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
++  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
++  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
++
++[Depex]
++  TRUE
++
+diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.c b/Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.c
+new file mode 100644
+index 0000000000..8f83737327
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.c
+@@ -0,0 +1,64 @@
++/** @file
++
++    Copyright (c) 2016 - 2018, Hisilicon Limited. All rights reserved.
++    Copyright (c) 2016 - 2018, Linaro Limited. All rights reserved.
++
++    This program and the accompanying materials
++    are licensed and made available under the terms and conditions of the BSD License
++    which accompanies this distribution. The full text of the license may be found at
++    http://opensource.org/licenses/bsd-license.php
++
++    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++**/
++
++#include <Uefi.h>
++#include <Library/BaseLib.h>
++#include <Library/DebugLib.h>
++#include <Library/PL011UartLib.h>
++#include <Library/PcdLib.h>
++#include <Library/SerialPortLib.h>
++
++RETURN_STATUS
++EFIAPI
++DebugSerialPortInitialize (
++  VOID
++  )
++{
++  UINT64              BaudRate;
++  UINT32              ReceiveFifoDepth;
++  EFI_PARITY_TYPE     Parity;
++  UINT8               DataBits;
++  EFI_STOP_BITS_TYPE  StopBits;
++
++  BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
++  ReceiveFifoDepth = 0;         // Use default FIFO depth
++  Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
++  DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
++  StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);
++  return PL011UartInitializePort (
++           (UINTN)FixedPcdGet64 (PcdSerialDbgRegisterBase),
++           FixedPcdGet32 (PL011UartClkInHz),
++           &BaudRate,
++           &ReceiveFifoDepth,
++           &Parity,
++           &DataBits,
++           &StopBits
++           );
++}
++
++EFI_STATUS
++SerialPortEntry (
++  IN EFI_HANDLE         ImageHandle,
++  IN EFI_SYSTEM_TABLE   *SystemTable
++  )
++{
++  EFI_STATUS Status;
++  Status = DebugSerialPortInitialize ();
++  if (EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "CPU1 TB serial port init ERROR: %r\n", Status));
++  }
++  return EFI_SUCCESS;
++}
++
+-- 
+2.17.0
+
diff --git a/v2/v2-0017-Hisilicon-D06-Add-ACPI-Tables-for-D06.patch b/v2/v2-0017-Hisilicon-D06-Add-ACPI-Tables-for-D06.patch
new file mode 100644
index 0000000000..0a2c72f49d
--- /dev/null
+++ b/v2/v2-0017-Hisilicon-D06-Add-ACPI-Tables-for-D06.patch
@@ -0,0 +1,10864 @@ 
+From 89b4761e354506305df57ee40f6089a536f965ae Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Thu, 21 Jun 2018 15:55:28 +0800
+Subject: [PATCH edk2-platforms v2 17/43] Hisilicon/D06: Add ACPI Tables for
+ D06
+
+ACPI tables for D06 2P, especially,Hi1620Iort.asl is include smmu
+and Hi1620IortNoSmmu.asl is without smmu.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Platform/Hisilicon/D06/D06.dsc                                          |    1 +
+ Platform/Hisilicon/D06/D06.fdf                                          |    1 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf          |   59 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Platform.h              |   27 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/CPU.asl                  |  409 ++++
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Com.asl                  |   30 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/DsdtHi1620.asl           |   35 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Apei.asl           |   93 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Ged.asl            |   58 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl           | 1459 ++++++++++++++
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mctp.asl           |   41 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl            | 1216 ++++++++++++
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Power.asl          |   28 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Rde.asl            |   47 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Sec.asl            |   57 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c100k.asl |  249 +++
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c400k.asl |  249 +++
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/LpcUart_clk.asl          |   49 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Pv680UncorePmu.asl       | 1658 ++++++++++++++++
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/ipmi.asl                 |   49 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Facs.aslc                     |   67 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Fadt.aslc                     |   91 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Gtdt.aslc                     |   86 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc               |   86 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl                | 1989 ++++++++++++++++++++
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl          | 1736 +++++++++++++++++
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Mcfg.aslc               |   64 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Slit.aslc               |   64 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Spcr.aslc               |   81 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Srat.aslc               |  166 ++
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/MadtHi1620.aslc               |  375 ++++
+ 31 files changed, 10620 insertions(+)
+
+diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
+index 20d2d2a1b4..9d4a86a4f4 100644
+--- a/Platform/Hisilicon/D06/D06.dsc
++++ b/Platform/Hisilicon/D06/D06.dsc
+@@ -332,6 +332,7 @@
+   MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+   Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
+ 
++  Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf
+   Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ 
+   #
+diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf
+index 8cac126ccf..06203dc079 100644
+--- a/Platform/Hisilicon/D06/D06.fdf
++++ b/Platform/Hisilicon/D06/D06.fdf
+@@ -249,6 +249,7 @@ READ_LOCK_STATUS   = TRUE
+   INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+   INF Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
+ 
++  INF RuleOverride=ACPITABLE Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf
+   INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ 
+   #
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf
+new file mode 100644
+index 0000000000..4157e0feef
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf
+@@ -0,0 +1,59 @@
++## @file
++#
++#  ACPI table data and ASL sources required to boot the platform.
++#
++#  Copyright (c) 2014, ARM Ltd. All rights reserved.
++#  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++#  Copyright (c) 2018, Linaro Limited. All rights reserved.
++#
++#  This program and the accompanying materials
++#  are licensed and made available under the terms and conditions of the BSD License
++#  which accompanies this distribution.  The full text of the license may be found at
++#  http://opensource.org/licenses/bsd-license.php
++#
++#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++#
++#  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++#
++##
++
++[Defines]
++  INF_VERSION                    = 0x0001001A
++  BASE_NAME                      = Hi1620AcpiTables
++  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
++  MODULE_TYPE                    = USER_DEFINED
++  VERSION_STRING                 = 1.0
++
++[Sources]
++  Dsdt/DsdtHi1620.asl
++  Facs.aslc
++  Fadt.aslc
++  Gtdt.aslc
++  Hi1620Dbg2.aslc
++  Hi1620Iort.asl
++  Hi1620IortNoSmmu.asl
++  Hi1620Mcfg.aslc
++  Hi1620Slit.aslc
++  Hi1620Spcr.aslc
++  Hi1620Srat.aslc
++  MadtHi1620.aslc
++
++[Packages]
++  ArmPkg/ArmPkg.dec
++  ArmPlatformPkg/ArmPlatformPkg.dec
++  EmbeddedPkg/EmbeddedPkg.dec
++  MdeModulePkg/MdeModulePkg.dec
++  MdePkg/MdePkg.dec
++  Silicon/Hisilicon/HisiPkg.dec
++
++[FixedPcd]
++  gArmPlatformTokenSpaceGuid.PcdCoreCount
++  gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
++  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
++  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
++  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
++  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
++  gArmTokenSpaceGuid.PcdGicDistributorBase
++  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
++  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Platform.h b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Platform.h
+new file mode 100644
+index 0000000000..5a6aa9a876
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Platform.h
+@@ -0,0 +1,27 @@
++/** @file
++*
++*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2015-2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++*
++**/
++
++
++#ifndef _HI1620_PLATFORM_H_
++#define _HI1620_PLATFORM_H_
++
++#include <../Include/PlatformArch.h>
++
++#define HI1620_WATCHDOG_COUNT  2
++
++#endif
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/CPU.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/CPU.asl
+new file mode 100644
+index 0000000000..ef8dae4d01
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/CPU.asl
+@@ -0,0 +1,409 @@
++/** @file
++  Differentiated System Description Table Fields (DSDT)
++
++  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
++    This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++
++**/
++
++Scope(_SB)
++{
++  //
++  // A57x16 Processor declaration
++  //
++  Device(CPU0) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 0)
++  }
++  Device(CPU1) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 1)
++  }
++  Device(CPU2) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 2)
++  }
++  Device(CPU3) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 3)
++  }
++  Device(CPU4) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 4)
++  }
++  Device(CPU5) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 5)
++  }
++  Device(CPU6) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 6)
++  }
++  Device(CPU7) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 7)
++  }
++  Device(CPU8) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 8)
++  }
++  Device(CPU9) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 9)
++  }
++  Device(CP10) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 10)
++  }
++  Device(CP11) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 11)
++  }
++  Device(CP12) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 12)
++  }
++  Device(CP13) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 13)
++  }
++  Device(CP14) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 14)
++  }
++  Device(CP15) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 15)
++  }
++  Device(CP16) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 16)
++  }
++  Device(CP17) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 17)
++  }
++  Device(CP18) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 18)
++  }
++  Device(CP19) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 19)
++  }
++  Device(CP20) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 20)
++  }
++  Device(CP21) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 21)
++  }
++  Device(CP22) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 22)
++  }
++  Device(CP23) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 23)
++  }
++  Device(CP24) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 24)
++  }
++  Device(CP25) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 25)
++  }
++  Device(CP26) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 26)
++  }
++  Device(CP27) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 27)
++  }
++  Device(CP28) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 28)
++  }
++  Device(CP29) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 29)
++  }
++  Device(CP30) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 30)
++  }
++  Device(CP31) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 31)
++  }
++  Device(CP32) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 32)
++  }
++  Device(CP33) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 33)
++  }
++  Device(CP34) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 34)
++  }
++  Device(CP35) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 35)
++  }
++  Device(CP36) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 36)
++  }
++  Device(CP37) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 37)
++  }
++  Device(CP38) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 38)
++  }
++  Device(CP39) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 39)
++  }
++  Device(CP40) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 40)
++  }
++  Device(CP41) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 41)
++  }
++  Device(CP42) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 42)
++  }
++  Device(CP43) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 43)
++  }
++  Device(CP44) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 44)
++  }
++  Device(CP45) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 45)
++  }
++  Device(CP46) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 46)
++  }
++  Device(CP47) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 47)
++  }
++
++  Device(CP48) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 48)
++  }
++  Device(CP49) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 49)
++  }
++  Device(CP50) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 50)
++  }
++  Device(CP51) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 51)
++  }
++  Device(CP52) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 52)
++  }
++  Device(CP53) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 53)
++  }
++  Device(CP54) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 54)
++  }
++  Device(CP55) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 55)
++  }
++  Device(CP56) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 56)
++  }
++  Device(CP57) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 57)
++  }
++  Device(CP58) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 58)
++  }
++  Device(CP59) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 59)
++  }
++  Device(CP60) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 60)
++  }
++  Device(CP61) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 61)
++  }
++  Device(CP62) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 62)
++  }
++  Device(CP63) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 63)
++  }
++  Device(CP64) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 64)
++  }
++  Device(CP65) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 65)
++  }
++  Device(CP66) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 66)
++  }
++  Device(CP67) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 67)
++  }
++  Device(CP68) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 68)
++  }
++  Device(CP69) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 69)
++  }
++  Device(CP70) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 70)
++  }
++  Device(CP71) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 71)
++  }
++  Device(CP72) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 72)
++  }
++  Device(CP73) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 73)
++  }
++  Device(CP74) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 74)
++  }
++  Device(CP75) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 75)
++  }
++  Device(CP76) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 76)
++  }
++  Device(CP77) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 77)
++  }
++  Device(CP78) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 78)
++  }
++  Device(CP79) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 79)
++  }
++  Device(CP80) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 80)
++  }
++  Device(CP81) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 81)
++  }
++  Device(CP82) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 82)
++  }
++  Device(CP83) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 83)
++  }
++  Device(CP84) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 84)
++  }
++  Device(CP85) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 85)
++  }
++  Device(CP86) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 86)
++  }
++  Device(CP87) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 87)
++  }
++  Device(CP88) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 88)
++  }
++  Device(CP89) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 89)
++  }
++  Device(CP90) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 90)
++  }
++  Device(CP91) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 91)
++  }
++  Device(CP92) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 92)
++  }
++  Device(CP93) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 93)
++  }
++  Device(CP94) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 94)
++  }
++  Device(CP95) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 95)
++  }
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Com.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Com.asl
+new file mode 100644
+index 0000000000..377d171abb
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Com.asl
+@@ -0,0 +1,30 @@
++/** @file
++  Differentiated System Description Table Fields (DSDT)
++
++  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
++    This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++
++**/
++
++Scope(_SB)
++{
++  Device(COM0) {
++    Name(_HID, "ARMH0011")
++    Name(_CID, "PL011")
++    Name(_UID, Zero)
++    Name(_CRS, ResourceTemplate() {
++      Memory32Fixed(ReadWrite, 0x94080000, 0x1000)
++      Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 141 }
++    })
++  }
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/DsdtHi1620.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/DsdtHi1620.asl
+new file mode 100644
+index 0000000000..7e26ba22b7
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/DsdtHi1620.asl
+@@ -0,0 +1,35 @@
++/** @file
++  Differentiated System Description Table Fields (DSDT)
++
++  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
++    This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++
++**/
++
++#include "Hi1620Platform.h"
++
++DefinitionBlock("DsdtTable.aml", "DSDT", 2, "HISI  ", "HIP08   ", EFI_ACPI_ARM_OEM_REVISION) {
++  include ("Com.asl")
++  include ("CPU.asl")
++  include ("Hi1620Pci.asl")
++  include ("Hi1620Mbig.asl")
++  include ("Hi1620Rde.asl")
++  include ("Hi1620Sec.asl")
++  include ("ipmi.asl")
++  include ("LpcUart_clk.asl")
++  include ("Hi1620Ged.asl")
++  include ("Hi1620Power.asl")
++  include ("Hi1620Apei.asl")
++  include ("Hi1620Mctp.asl")
++  include ("Pv680UncorePmu.asl")
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Apei.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Apei.asl
+new file mode 100644
+index 0000000000..0970ed9b99
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Apei.asl
+@@ -0,0 +1,93 @@
++/** @file
++*
++*  Copyright (c) 2018 Hisilicon Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++//Define a control method APEI
++Scope(_SB)
++{
++  Device(GED2) {
++    Name(_HID, "ACPI0013")
++    Name(_UID, 2)
++
++    Name (_CRS, ResourceTemplate ()  {
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive) {
++        122
++      }
++    })
++
++    Method (_EVT, 0x1) {
++      Switch(ToInteger(Arg0)) {
++        Case(122) {
++          Notify (\_SB.ERRD, 0x80)
++        }
++      }
++    }
++
++    Method (_STA, 0x0, NotSerialized) {
++      return (0xF);
++    }
++  }
++}
++
++Device (\_SB.ERRD)
++{
++  Name (_HID, EISAID("PNP0C33"))
++  Name (_UID, 0)
++  Method (_STA, 0x0, NotSerialized) {
++    Return(0xF)
++  }
++}
++
++Name(PWCP, Zero) // Platform-Wide Capability value.
++
++Scope (\_SB) {
++  Method (_OSC,4) {
++    // Create DWord-adressable for Arg3 First DWORD.
++    CreateDWordField(Arg3,0,CDW1)
++
++    // Check for proper UUID
++    If (LEqual(Arg0,ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48"))) {
++      // Create DWord-adressable fields from the Capabilities Buffer
++      CreateDWordField (Arg3,4,TPD2)
++
++      // Save Capabilities DWord2
++      Store (TPD2, PWCP)
++
++      // Set Bit[4]: APEI Support
++      Or (PWCP,0x10,PWCP)
++
++      If (LNotEqual(Arg1,One)) {// Unknown revision
++        Or (CDW1,0x08,CDW1)
++      }
++
++      // Update DWORD2 in the buffer
++      Store (PWCP,TPD2)
++
++      Return (Arg3)
++    }
++    ElseIf (LEqual(Arg0, ToUUID("ed855e0c-6c90-47bf-a62a-26de0fc5ad5c"))) { // Check for WHEA GUID
++      CreateDWordField (Arg3,4,TPD3)
++
++      Or (TPD3, 0x10, TPD3) //Set Bit[4]: APEI support.
++
++      If (LNotEqual(Arg1,One)) {// Unknown revision
++        Or (CDW1,0x08,CDW1)
++      }
++
++      return (Arg3)
++    }
++    Else {
++      Or (CDW1,4,CDW1) // Unrecognized UUID
++      Return (Arg3)
++    }
++  } // End _OSC
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Ged.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Ged.asl
+new file mode 100644
+index 0000000000..6664c0c681
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Ged.asl
+@@ -0,0 +1,58 @@
++/** @file
++*
++* Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
++* Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++* Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++//
++// Ged
++//
++
++//Define a control method power button
++Scope(_SB)
++{
++  OperationRegion(IOM1, SystemMemory, 0x941900C8, 0x4)
++  Field(IOM1, DWordAcc, NoLock, Preserve) {
++    IMX0, 32,
++  }
++
++  Method (_INI) {
++    Store(IMX0, Local0)
++    And(Local0, 0xFFFFFFFC, Local0)
++    Or(Local0, 0x4, Local0)
++    Store(Local0, IMX0)
++  }
++
++  Device(GED1) {
++    Name(_HID, "ACPI0013")
++    Name(_UID, 0)
++
++    Name (_CRS, ResourceTemplate ()  {
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive) {
++        121
++      }
++    })
++
++    Method (_STA, 0x0, NotSerialized) {
++      return (0xF);
++    }
++
++    Method (_EVT, 0x1) {
++      Switch(ToInteger(Arg0)) {
++        Case(121) {
++          Notify (\_SB.PWRB, 0x80)
++        }
++      }
++    }
++  }
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl
+new file mode 100644
+index 0000000000..6adf5973a6
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl
+@@ -0,0 +1,1459 @@
++/** @file
++  Differentiated System Description Table Fields (DSDT)
++
++  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
++    This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++**/
++
++Scope(_SB)
++{
++  //This is for S0-TB-L3T0 PMU implementation
++  Device(MB30) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x30)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xA8080000,
++          0xA808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TB-L3T1 PMU implementation
++  Device(MB31) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x31)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xA8080000,
++          0xA808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TB-L3T2 PMU implementation
++  Device(MB32) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x32)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xA8080000,
++          0xA808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TB-L3T3 PMU implementation
++  Device(MB33) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x33)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xA8080000,
++          0xA808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TB-L3T4 PMU implementation
++  Device(MB34) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x34)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xA8080000,
++          0xA808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TB-L3T5 PMU implementation
++  Device(MB35) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x35)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xA8080000,
++          0xA808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TB-DDRC0 PMU implementation
++  Device(MB38) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x38)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xA8080000,
++          0xA808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TB-DDRC1 PMU implementation
++  Device(MB39) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x39)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xA8080000,
++          0xA808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TB-DDRC2 PMU implementation
++  Device(MB3A) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x3A)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xA8080000,
++          0xA808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TB-DDRC3 PMU implementation
++  Device(MB3B) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x3B)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xA8080000,
++          0xA808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TB-HHA0 PMU implementation
++  Device(MB3C) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x3C)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xA8080000,
++          0xA808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TB-HHA1 PMU implementation
++  Device(MB3D) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x3D)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xA8080000,
++          0xA808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TA-L3T0 PMU implementation
++  Device(MB10) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x10)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xAC080000,
++          0xAC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TA-L3T1 PMU implementation
++  Device(MB11) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x11)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xAC080000,
++          0xAC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TA-L3T2 PMU implementation
++  Device(MB12) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x12)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xAC080000,
++          0xAC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TA-L3T3 PMU implementation
++  Device(MB13) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x13)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xAC080000,
++          0xAC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++
++  //This is for S0-TA-L3T4 PMU implementation
++  Device(MB14) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x14)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xAC080000,
++          0xAC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TA-L3T5 PMU implementation
++  Device(MB15) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x15)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xAC080000,
++          0xAC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TA-DDRC0 PMU implementation
++  Device(MB18) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x18)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xAC080000,
++          0xAC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TA-DDRC1 PMU implementation
++  Device(MB19) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x19)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xAC080000,
++          0xAC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TA-DDRC2 PMU implementation
++  Device(MB1A) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x1A)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xAC080000,
++          0xAC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TA-DDRC3 PMU implementation
++  Device(MB1B) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x1B)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xAC080000,
++          0xAC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TA-HHA0 PMU implementation
++  Device(MB1C) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x1C)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xAC080000,
++          0xAC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TA-HHA1 PMU implementation
++  Device(MB1D) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x1D)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xAC080000,
++          0xAC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TB-L3T0 PMU implementation
++  Device(MB70) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x70)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000A8080000,
++          0x4000A808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TB-L3T1 PMU implementation
++  Device(MB71) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x71)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000A8080000,
++          0x4000A808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TB-L3T2 PMU implementation
++  Device(MB72) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x72)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000A8080000,
++          0x4000A808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TB-L3T3 PMU implementation
++  Device(MB73) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x73)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000A8080000,
++          0x4000A808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++
++  //This is for S1-TB-L3T4 PMU implementation
++  Device(MB74) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x74)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000A8080000,
++          0x4000A808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TB-L3T5 PMU implementation
++  Device(MB75) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x75)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000A8080000,
++          0x4000A808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TB-DDRC0 PMU implementation
++  Device(MB78) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x78)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000A8080000,
++          0x4000A808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TB-DDRC1 PMU implementation
++  Device(MB79) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x79)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000A8080000,
++          0x4000A808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TB-DDRC2 PMU implementation
++  Device(MB7A) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x7A)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000A8080000,
++          0x4000A808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TB-DDRC3 PMU implementation
++  Device(MB7B) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x7B)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000A8080000,
++          0x4000A808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TB-HHA0 PMU implementation
++  Device(MB7C) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x7C)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000A8080000,
++          0x4000A808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TB-HHA1 PMU implementation
++  Device(MB7D) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x7D)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000A8080000,
++          0x4000A808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TA-L3T0 PMU implementation
++  Device(MB50) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x50)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000AC080000,
++          0x4000AC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TA-L3T1 PMU implementation
++  Device(MB51) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x51)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000AC080000,
++          0x4000AC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TA-L3T2 PMU implementation
++  Device(MB52) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x52)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000AC080000,
++          0x4000AC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TA-L3T3 PMU implementation
++  Device(MB53) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x53)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000AC080000,
++          0x4000AC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++
++  //This is for S1-TA-L3T4 PMU implementation
++  Device(MB54) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x54)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000AC080000,
++          0x4000AC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TA-L3T5 PMU implementation
++  Device(MB55) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x55)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000AC080000,
++          0x4000AC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TA-DDRC0 PMU implementation
++  Device(MB58) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x58)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000AC080000,
++          0x4000AC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TA-DDRC1 PMU implementation
++  Device(MB59) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x59)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000AC080000,
++          0x4000AC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TA-DDRC2 PMU implementation
++  Device(MB5A) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x5A)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000AC080000,
++          0x4000AC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TA-DDRC3 PMU implementation
++  Device(MB5B) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x5B)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000AC080000,
++          0x4000AC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TA-HHA0 PMU implementation
++  Device(MB5C) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x5C)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000AC080000,
++          0x4000AC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TA-HHA1 PMU implementation
++  Device(MB5D) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x5D)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000AC080000,
++          0x4000AC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mctp.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mctp.asl
+new file mode 100644
+index 0000000000..d039e8a110
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mctp.asl
+@@ -0,0 +1,41 @@
++/** @file
++  Differentiated System Description Table Fields (DSDT)
++
++  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
++    This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++
++**/
++Scope(_SB)
++{
++  Device(LOC0) {
++    Name(_HID, "HISI02F1")
++    Name(_UID, 0)
++    Name (_CRS, ResourceTemplate ()  {
++      Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive)
++      {
++        488,489
++      }
++    })
++  }
++
++  Device(MCT0) {
++    Name(_HID, "HISI0301")
++    Name(_UID, 0)
++    Name (_CRS, ResourceTemplate ()  {
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI4")
++      {
++        656
++      }
++    })
++  }
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl
+new file mode 100644
+index 0000000000..8e3547926a
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl
+@@ -0,0 +1,1216 @@
++/** @file
++*
++*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2016, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++*
++**/
++
++//#include "ArmPlatform.h"
++Scope(_SB)
++{
++  Device (PCI0)
++  {                                          // PCI0 indicate host bridge 0
++    Name (_HID, "PNP0A08")                   // PCI Express Root Bridge
++    Name (_UID, 0)
++    Name (_CID, "PNP0A03")                   // Compatible PCI Root Bridge, Compatible ID
++    Name(_SEG, 0)                            // Segment of this Root complex
++    Name (_BBN, 0x0)                         // Base Bus Number
++    Name (_CCA, 1)                           // cache coherence attribute
++
++    Name (_PRT, Package (){
++      // INTx configure for RP0, whoes device number is 0
++      // For ESL/FPGA debug, we should modify this according to
++      // specific hardware configuration.
++      Package () {0xFFFF,0,0,640},         // INT_A
++      Package () {0xFFFF,1,0,641},         // INT_B
++      Package () {0xFFFF,2,0,642},         // INT_C
++      Package () {0xFFFF,3,0,643},         // INT_D
++
++      // This is an example of RP1 INTx configure. Adding or not
++      // adding RPx INTx configure deponds on hardware board topology,
++      // if UEFI enables RPx, RPy, RPz... related INTx configure
++      // should be added
++      Package () {0x4FFFF,0,0,640},         // INT_A
++      Package () {0x4FFFF,1,0,641},         // INT_B
++      Package () {0x4FFFF,2,0,642},         // INT_C
++      Package () {0x4FFFF,3,0,643},         // INT_D
++
++      Package () {0x8FFFF,0,0,640},         // INT_A
++      Package () {0x8FFFF,1,0,641},         // INT_B
++      Package () {0x8FFFF,2,0,642},         // INT_C
++      Package () {0x8FFFF,3,0,643},         // INT_D
++
++      Package () {0xCFFFF,0,0,640},         // INT_A
++      Package () {0xCFFFF,1,0,641},         // INT_B
++      Package () {0xCFFFF,2,0,642},         // INT_C
++      Package () {0xCFFFF,3,0,643},         // INT_D
++
++      Package () {0x10FFFF,0,0,640},         // INT_A
++      Package () {0x10FFFF,1,0,641},         // INT_B
++      Package () {0x10FFFF,2,0,642},         // INT_C
++      Package () {0x10FFFF,3,0,643},         // INT_D
++
++      Package () {0x12FFFF,0,0,640},         // INT_A
++      Package () {0x12FFFF,1,0,641},         // INT_B
++      Package () {0x12FFFF,2,0,642},         // INT_C
++      Package () {0x12FFFF,3,0,643},         // INT_D
++      })
++
++    Method (_CRS, 0, Serialized) {
++      // Method is defined in 19.6.82 in ACPI 6.0 spec
++      Name (RBUF, ResourceTemplate () {
++        // 19.3.3 in ACPI 6.0 spec
++        WordBusNumber (
++          ResourceProducer,
++          MinFixed,
++          MaxFixed,
++          PosDecode,
++          0,                                 // AddressGranularity
++          0x00,                              // AddressMinimum - Minimum Bus Number
++          0x3f,                              // AddressMaximum - Maximum Bus Number
++          0,                                 // AddressTranslation - Set to 0
++          0x40                               // RangeLength - Number of Busses
++        )
++        QWordMemory (                        // 64-bit prefetch BAR windows
++          ResourceProducer,
++          PosDecode,
++          MinFixed,
++          MaxFixed,
++          Prefetchable,
++          ReadWrite,
++          0x0,                               // Granularity
++          0x80000000000,                     // Min Base Address pci address
++          0x83fffffffff,                     // Max Base Address
++          0x0,                               // Translate
++          0x4000000000                       // Length, 256G
++        )
++        QWordMemory (                        // 32-bit non-prefetch BAR windows
++          ResourceProducer,
++          PosDecode,
++          MinFixed,
++          MaxFixed,
++          Cacheable,
++          ReadWrite,
++          0x0,                               // Granularity
++          0xe0000000,                        // Min Base Address pci address
++          0xeffeffff,                        // Max Base Address
++          0x0,                               // Translate
++          0xfff0000                          // Length, 256M - 64K
++        )
++        QWordIO (
++          ResourceProducer,
++          MinFixed,
++          MaxFixed,
++          PosDecode,
++          EntireRange,
++          0x0,                               // Granularity
++          0x0,                               // Min Base Address
++          0xffff,                            // Max Base Address
++          0xefff0000,                        // Translate
++          0x10000                            // Length, 64K
++        )}
++      )                                      // Name(RBUF)
++      Return (RBUF)
++    }                                        // Method(_CRS), this method return RBUF!
++
++  //
++  // OS Control Handoff
++  //
++  Name(SUPP, Zero) // PCI _OSC Support Field value
++  Name(CTRL, Zero) // PCI _OSC Control Field value
++
++  Method(_OSC,4) {
++    // Check for proper UUID
++    If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
++      // Create DWord-adressable fields from the Capabilities Buffer
++      CreateDWordField(Arg3,0,CDW1)
++      CreateDWordField(Arg3,4,CDW2)
++      CreateDWordField(Arg3,8,CDW3)
++
++      // Save Capabilities DWord2 & 3
++      Store(CDW2,SUPP)
++      Store(CDW3,CTRL)
++
++      // Only allow native hot plug control if OS supports:
++      //  ASPM
++      //  Clock PM
++      //  MSI/MSI-X
++      If(LNotEqual(And(SUPP, 0x16), 0x16)) {
++        And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
++      }
++
++      // Always allow native PME, AER (no dependencies)
++
++      // Never allow SHPC (no SHPC controller in this system)
++      And(CTRL,0x1D,CTRL)
++
++      If(LNotEqual(Arg1,One)) {  // Unknown revision
++        Or(CDW1,0x08,CDW1)
++      }
++
++      If(LNotEqual(CDW3,CTRL)) {  // Capabilities bits were masked
++        Or(CDW1,0x10,CDW1)
++      }
++
++      // Update DWORD3 in the buffer
++      Store(CTRL,CDW3)
++      Return(Arg3)
++    } Else {
++      Or(CDW1,4,CDW1) // Unrecognized UUID
++      Return(Arg3)
++    }
++  } // End _OSC
++
++  Method (_HPX, 0) {
++    Return (Package(2) {
++      Package(6) {    // PCI Setting Record
++        0x00,         // Type 0
++        0x01,         // Revision 1
++        0x08,         // CacheLineSize in DWORDS
++        0x40,         // LatencyTimer in PCI clocks
++        0x01,         // Enable SERR (Boolean)
++        0x01          // Enable PERR (Boolean)
++      },
++
++      Package(18){   // PCI-X Setting Record
++        0x02,        // Type 2
++        0x01,        // Revision 1
++        0xFFFFFFFF,  // Uncorrectable Error Mask Register AND Mask, Keep ->1
++        0x00000000,  // Uncorrectable Error Mask Register OR Mask, keep ->0
++        0xFFFFFFFF,  // Uncorrectable Error Severity Register AND Mask
++        0x00000000,  // Uncorrectable Error Severity Register OR Mask
++        0xFFFFFFFF,  // Correctable Error Mask Register AND Mask
++        0x00000000,  // Correctable Error Mask Register OR Mask
++        0xFFFFFFFF,  // Advanced Error Capabilities and Control Register AND Mask
++        0x00000000,  // Advanced Error Capabilities and Control Register OR Mask
++        0xFFF7,      // Device Control Register AND Mask
++        0x0007,      // Device Control Register OR Mask
++        0xFFFF,      // Link Control Register AND Mask
++        0x0000,      // Link Control Register OR Mask
++        0xFFFFFFFF,  // Secondary Uncorrectable Error Severity Register AND Mask
++        0x00000000,  // Secondary Uncorrectable Error Severity Register OR Mask
++        0xFFFFFFFF,  // Secondary Uncorrectable Error Mask Register AND Mask
++        0x00000000   // Secondary Uncorrectable Error Mask Register OR Mask
++      }
++    })
++  }
++
++  Method (_STA, 0x0, NotSerialized) {
++    Return (0xf)
++  }
++
++  Method (_PXM, 0, NotSerialized)
++  {
++    Return(0x01)
++  }
++} // Device(PCI0)
++
++
++Device (PCI1)
++{                                            // PCI1 indicate host bridge 1
++  Name (_HID, "PNP0A08")                   // PCI Express Root Bridge
++  Name (_UID, 1)
++  Name (_CID, "PNP0A03")                   // Compatible PCI Root Bridge, Compatible ID
++  Name(_SEG, 0)                            // Segment of this Root complex
++  Name(_BBN, 0x7b)                         // Base Bus Number ??
++  Name(_CCA, 1)                            // cache coherence attribute ??
++  Method (_CRS, 0, Serialized) {           // Root complex resources, _CRS: current resource setting
++    Name (RBUF, ResourceTemplate () {      // Name: 19.6.87, ResourceTemplate: 19.6.111,
++      WordBusNumber (                          // Bus numbers assigned to this root,
++        ResourceProducer,
++        MinFixed,
++        MaxFixed,
++        PosDecode,
++        0,                                 // AddressGranularity
++        0x7b,                              // AddressMinimum - Minimum Bus Number
++        0x7b,                              // AddressMaximum - Maximum Bus Number
++        0,                                 // AddressTranslation - Set to 0
++        0x1                                // RangeLength - Number of Busses
++      )
++      QWordMemory (                        // 64-bit BAR Windows, where to show this ??
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        Prefetchable,
++        ReadWrite,
++        0x0,                               // Granularity
++        0x148800000,                       // Min Base Address pci address ??
++        0x148ffffff,                       // Max Base Address
++        0x0,                               // Translate
++        0x800000                           // Length, 8M
++      )
++    })                                      // Name(RBUF)
++    Return (RBUF)
++  }                                         // Method(_CRS), this method return RBUF!
++
++  Method (_STA, 0x0, NotSerialized)
++  {
++    Return (0xf)
++  }
++
++  Method (_PXM, 0, NotSerialized)
++  {
++    Return(0x01)
++  }
++} // Device(PCI1)
++
++Device (PCI2)
++{
++  Name (_HID, "PNP0A08")                   // PCI Express Root Bridge
++  Name (_UID, 2)
++  Name (_CID, "PNP0A03")                   // Compatible PCI Root Bridge, Compatible ID
++  Name(_SEG, 0)                            // Segment of this Root complex
++  Name(_BBN, 0x7a)                         // Base Bus Number
++  Name(_CCA, 1)                            // cache coherence attribute ??
++  Name (_PRT, Package (){
++    Package () {0xFFFF,0,0,640},         // INT_A
++    Package () {0xFFFF,1,0,641},         // INT_B
++    Package () {0xFFFF,2,0,642},         // INT_C
++    Package () {0xFFFF,3,0,643},         // INT_D
++    Package () {0x1FFFF,0,0,640},         // INT_A
++    Package () {0x1FFFF,1,0,641},         // INT_B
++    Package () {0x1FFFF,2,0,642},         // INT_C
++    Package () {0x1FFFF,3,0,643},         // INT_D
++    Package () {0x2FFFF,0,0,640},         // INT_A
++    Package () {0x2FFFF,1,0,641},         // INT_B
++    Package () {0x2FFFF,2,0,642},         // INT_C
++    Package () {0x2FFFF,3,0,643},         // INT_D
++  })
++  Method (_CRS, 0, Serialized) {           // Root complex resources, _CRS: current resource //                               setting
++    Name (RBUF, ResourceTemplate () {      // Name: 19.6.87, ResourceTemplate: 19.6.111,
++      WordBusNumber (                      // Bus numbers assigned to this root,
++        ResourceProducer,
++        MinFixed,
++        MaxFixed,
++        PosDecode,
++        0,                                 // AddressGranularity
++        0x7a,                              // AddressMinimum - Minimum Bus Number
++        0x7a,                              // AddressMaximum - Maximum Bus Number
++        0,                                 // AddressTranslation - Set to 0
++        0x1                                // RangeLength - Number of Busses
++      )
++      QWordMemory (                        // 64-bit BAR Windows
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        Prefetchable,
++        ReadWrite,
++        0x0,                               // Granularity
++        0x20c000000,                       // Min Base Address pci address
++        0x20c1fffff,                       // Max Base Address
++        0x0,                               // Translate
++        0x200000                           // Length, 2M
++      )
++    })                                      // Name(RBUF)
++    Return (RBUF)
++  }                                         // Method(_CRS), this method return RBUF!
++
++  Method (_STA, 0x0, NotSerialized)
++  {
++    Return (0xf)
++  }
++
++  Method (_PXM, 0, NotSerialized)
++  {
++    Return(0x01)
++  }
++}
++
++Device (PCI3)
++{
++  Name (_HID, "PNP0A08")                   // PCI Express Root Bridge
++  Name (_UID, 3)
++  Name (_CID, "PNP0A03")                   // Compatible PCI Root Bridge, Compatible ID
++  Name(_SEG, 0)                            // Segment of this Root complex
++  Name(_BBN, 0x78)                         // Base Bus Number ??
++  Name(_CCA, 1)                            // cache coherence attribute ??
++  Method (_CRS, 0, Serialized) {           // Root complex resources, _CRS: current resource
++    Name (RBUF, ResourceTemplate () {      // Name: 19.6.87, ResourceTemplate: 19.6.111,
++      WordBusNumber (                      // Bus numbers assigned to this root,
++        ResourceProducer,
++        MinFixed,
++        MaxFixed,
++        PosDecode,
++        0,                                 // AddressGranularity
++        0x78,                              // AddressMinimum - Minimum Bus Number
++        0x79,                              // AddressMaximum - Maximum Bus Number
++        0,                                 // AddressTranslation - Set to 0
++        0x2                                // RangeLength - Number of Busses
++      )
++      QWordMemory (                        // 64-bit BAR Windows
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        Prefetchable,
++        ReadWrite,
++        0x0,                               // Granularity
++        0x208000000,                       // Min Base Address pci address
++        0x208ffffff,                       // Max Base Address
++        0x0,                               // Translate
++        0x1000000                          // Length, 16M
++      )
++    })                                      // Name(RBUF)
++    Return (RBUF)
++  }                                         // Method(_CRS), this method return RBUF!
++
++  Method (_STA, 0x0, NotSerialized)
++  {
++    Return (0xf)
++  }
++
++  Method (_PXM, 0, NotSerialized)
++  {
++    Return(0x01)
++  }
++}
++
++Device (PCI4)
++{
++  Name (_HID, "PNP0A08")                   // PCI Express Root Bridge
++  Name (_UID, 4)
++  Name (_CID, "PNP0A03")                   // Compatible PCI Root Bridge, Compatible ID
++  Name(_SEG, 0)                            // Segment of this Root complex
++  Name(_BBN, 0x7c)                         // Base Bus Number ??
++  Name(_CCA, 1)                            // cache coherence attribute ??
++  Method (_CRS, 0, Serialized) {           // Root complex resources, _CRS: current resource
++    Name (RBUF, ResourceTemplate () {      // Name: 19.6.87, ResourceTemplate: 19.6.111,
++      WordBusNumber (                      // Bus numbers assigned to this root,
++        ResourceProducer,
++        MinFixed,
++        MaxFixed,
++        PosDecode,
++        0,                                 // AddressGranularity
++        0x7c,                              // AddressMinimum - Minimum Bus Number
++        0x7d,                              // AddressMaximum - Maximum Bus Number
++        0,                                 // AddressTranslation - Set to 0
++        0x2                                // RangeLength - Number of Busses
++      )
++      QWordMemory (                        // 64-bit BAR Windows
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        Prefetchable,
++        ReadWrite,
++        0x0,                               // Granularity
++        0x120000000,                       // Min Base Address pci address
++        0x13fffffff,                       // Max Base Address
++        0x0,                               // Translate
++        0x20000000                         // Length, 512M
++      )
++    })                                      // Name(RBUF)
++    Return (RBUF)
++  }                                         // Method(_CRS), this method return RBUF!
++
++  Method (_STA, 0x0, NotSerialized)
++  {
++    Return (0x0F)
++  }
++
++  Method (_PXM, 0, NotSerialized)
++  {
++    Return(0x01)
++  }
++}
++
++Device (PCI5)
++{
++  Name (_HID, "PNP0A08")                   // PCI Express Root Bridge
++  Name (_UID, 5)
++  Name (_CID, "PNP0A03")                   // Compatible PCI Root Bridge, Compatible ID
++  Name(_SEG, 0)                            // Segment of this Root complex
++  Name(_BBN, 0x74)                         // Base Bus Number ??
++  Name(_CCA, 1)                            // cache coherence attribute ??
++
++  Name (_PRT, Package (){
++    Package () {0x2FFFF,0,0,640},         // INT_A
++    Package () {0x2FFFF,1,0,641},         // INT_B
++    Package () {0x2FFFF,2,0,642},         // INT_C
++    Package () {0x2FFFF,3,0,643},         // INT_D
++    Package () {0x3FFFF,0,0,640},         // INT_A
++    Package () {0x3FFFF,1,0,641},         // INT_B
++    Package () {0x3FFFF,2,0,642},         // INT_C
++    Package () {0x3FFFF,3,0,643},         // INT_D
++  })
++
++  Method (_CRS, 0, Serialized) {           // Root complex resources, _CRS: current resource setting
++    Name (RBUF, ResourceTemplate () {      // Name: 19.6.87, ResourceTemplate: 19.6.111,
++      WordBusNumber (                      // Bus numbers assigned to this root,
++      ResourceProducer,
++      MinFixed,
++      MaxFixed,
++      PosDecode,
++      0,                                 // AddressGranularity
++      0x74,                              // AddressMinimum - Minimum Bus Number
++      0x76,                              // AddressMaximum - Maximum Bus Number
++      0,                                 // AddressTranslation - Set to 0
++      0x3                                // RangeLength - Number of Busses
++      )
++      QWordMemory (                        // 64-bit BAR Windows
++      ResourceProducer,
++      PosDecode,
++      MinFixed,
++      MaxFixed,
++      Prefetchable,
++      ReadWrite,
++      0x0,                               // Granularity
++      0x144000000,                       // Min Base Address pci address
++      0x147ffffff,                       // Max Base Address
++      0x0,                               // Translate
++      0x4000000                          // Length, 32M
++      )
++      QWordMemory (                        // 32-bit non-prefetch BAR Windows
++      ResourceProducer,
++      PosDecode,
++      MinFixed,
++      MaxFixed,
++      Cacheable,
++      ReadWrite,
++      0x0,                               // Granularity
++      0xa2000000,                        // Min Base Address pci address
++      0xa2ffffff,                        // Max Base Address
++      0x0,                               // Translate
++      0x1000000                          // Length, 16M
++      )
++    })                                 // Name(RBUF)
++    Return (RBUF)
++  }                                    // Method(_CRS), this method return RBUF!
++
++  Method (_STA, 0x0, NotSerialized)
++  {
++    Return (0xf)
++  }
++
++  Device (SAS0)
++  {
++    Name (_ADR, 0x00020000)
++    Name (_DSD, Package ()
++    {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package ()
++      {
++        Package (2) {"sas-addr", Package() {0x50, 0x01, 0x88, 0x20, 0x16, 0x00, 0x00, 0x00}},
++        Package ()  {"queue-count", 16},
++        Package ()  {"phy-count", 8},
++      }
++    })
++
++    OperationRegion (CTL, SystemMemory, 0x140070000, 0x1000)
++    Field (CTL, DWordAcc, NoLock, Preserve)
++    {
++      Offset (0xa18),
++      RST, 32,
++      DRST, 32,
++    }
++
++    OperationRegion (TXD, SystemMemory, 0xA2000000, 0x4000)
++    Field (TXD, DwordAcc, NoLock, Preserve)
++    {
++      Offset (0x2350),  //port0
++      ST00, 32,   //0x2350
++      ST01, 32,   //0x2354
++      ST02, 32,   //0x2358
++      ST03, 32,   //0x235c
++      ST04, 32,   //0x2360
++      ST05, 32,   //0x2364
++      ST06, 32,   //0x2368
++      ST07, 32,   //0x236c
++      Offset (0x2750),  //port1
++      ST10, 32,   //0x2750
++      ST11, 32,   //0x2754
++      ST12, 32,   //0x2758
++      ST13, 32,   //0x275c
++      ST14, 32,   //0x2760
++      ST15, 32,   //0x2764
++      ST16, 32,   //0x2768
++      ST17, 32,   //0x276c
++      Offset (0x2b50),  //port2
++      ST20, 32,   //0x2b50
++      ST21, 32,   //0x2b54
++      ST22, 32,   //0x2b58
++      ST23, 32,   //0x2b5c
++      ST24, 32,   //0x2b60
++      ST25, 32,   //0x2b64
++      ST26, 32,   //0x2b68
++      ST27, 32,   //0x2b6c
++      Offset (0x2f50),  //port3
++      ST30, 32,   //0x2f50
++      ST31, 32,   //0x2f54
++      ST32, 32,   //0x2f58
++      ST33, 32,   //0x2f5c
++      ST34, 32,   //0x2f60
++      ST35, 32,   //0x2f64
++      ST36, 32,   //0x2f68
++      ST37, 32,   //0x2f6c
++      Offset (0x3350),  //port4
++      ST40, 32,   //0x3350
++      ST41, 32,   //0x3354
++      ST42, 32,   //0x3358
++      ST43, 32,   //0x335c
++      ST44, 32,   //0x3360
++      ST45, 32,   //0x3364
++      ST46, 32,   //0x3368
++      ST47, 32,   //0x336c
++      Offset (0x3750),//port5
++      ST50, 32,   //0x3750
++      ST51, 32,   //0x3754
++      ST52, 32,   //0x3758
++      ST53, 32,   //0x375c
++      ST54, 32,   //0x3760
++      ST55, 32,   //0x3764
++      ST56, 32,   //0x3768
++      ST57, 32,   //0x376c
++      Offset (0x3b50),  //port6
++      ST60, 32,   //0x3b50
++      ST61, 32,   //0x3b54
++      ST62, 32,   //0x3b58
++      ST63, 32,   //0x3b5c
++      ST64, 32,   //0x3b60
++      ST65, 32,   //0x3b64
++      ST66, 32,   //0x3b68
++      ST67, 32,   //0x3b6c
++      Offset (0x3f50),  //port7
++      ST70, 32,   //0x3f50
++      ST71, 32,   //0x3f54
++      ST72, 32,   //0x3f58
++      ST73, 32,   //0x3f5c
++      ST74, 32,   //0x3f60
++      ST75, 32,   //0x3f64
++      ST76, 32,   //0x3f68
++      ST77, 32    //0x3f6c
++    }
++
++    Method (_RST, 0x0, Serialized)
++    {
++      Store(0x7FFFFFF, RST)
++      Sleep(1)
++      Store(0x7FFFFFF, DRST)
++      Sleep(1)
++
++      //port0
++      Store (0x8D04, ST00)
++      Sleep(1)
++      Store (0x8D04, ST01)
++      Sleep(1)
++      Store (0x8D04, ST02)
++      Sleep(1)
++      Store (0x8D04, ST03)
++      Sleep(1)
++      Store (0x8D04, ST05)
++      Sleep(1)
++      Store (0x8D04, ST06)
++      Sleep(1)
++      Store (0x8D04, ST07)
++      Sleep(1)
++
++      //port1
++      Store (0x8D04, ST10)
++      Sleep(1)
++      Store (0x8D04, ST11)
++      Sleep(1)
++      Store (0x8D04, ST12)
++      Sleep(1)
++      Store (0x8D04, ST13)
++      Sleep(1)
++      Store (0x8D04, ST15)
++      Sleep(1)
++      Store (0x8D04, ST16)
++      Sleep(1)
++      Store (0x8D04, ST17)
++      Sleep(1)
++
++      //port2
++      Store (0x8D04, ST20)
++      Sleep(1)
++      Store (0x8D04, ST21)
++      Sleep(1)
++      Store (0x8D04, ST22)
++      Sleep(1)
++      Store (0x8D04, ST23)
++      Sleep(1)
++      Store (0x8D04, ST25)
++      Sleep(1)
++      Store (0x8D04, ST26)
++      Sleep(1)
++      Store (0x8D04, ST27)
++      Sleep(1)
++
++      //port3
++      Store (0x8D04, ST30)
++      Sleep(1)
++      Store (0x8D04, ST31)
++      Sleep(1)
++      Store (0x8D04, ST32)
++      Sleep(1)
++      Store (0x8D04, ST33)
++      Sleep(1)
++      Store (0x8D04, ST35)
++      Sleep(1)
++      Store (0x8D04, ST36)
++      Sleep(1)
++      Store (0x8D04, ST37)
++      Sleep(1)
++
++      //port4
++      Store (0x8D04, ST40)
++      Sleep(1)
++      Store (0x8D04, ST41)
++      Sleep(1)
++      Store (0x8D04, ST42)
++      Sleep(1)
++      Store (0x8D04, ST43)
++      Sleep(1)
++      Store (0x8D04, ST45)
++      Sleep(1)
++      Store (0x8D04, ST46)
++      Sleep(1)
++      Store (0x8D04, ST47)
++      Sleep(1)
++
++      //port5
++      Store (0x8D04, ST50)
++      Sleep(1)
++      Store (0x8D04, ST51)
++      Sleep(1)
++      Store (0x8D04, ST52)
++      Sleep(1)
++      Store (0x8D04, ST53)
++      Sleep(1)
++      Store (0x8D04, ST55)
++      Sleep(1)
++      Store (0x8D04, ST56)
++      Sleep(1)
++      Store (0x8D04, ST57)
++      Sleep(1)
++
++      //port6
++      Store (0x8D04, ST60)
++      Sleep(1)
++      Store (0x8D04, ST61)
++      Sleep(1)
++      Store (0x8D04, ST62)
++      Sleep(1)
++      Store (0x8D04, ST63)
++      Sleep(1)
++      Store (0x8D04, ST65)
++      Sleep(1)
++      Store (0x8D04, ST66)
++      Sleep(1)
++      Store (0x8D04, ST67)
++      Sleep(1)
++
++      //port7
++      Store (0x8D04, ST70)
++      Sleep(1)
++      Store (0x8D04, ST71)
++      Sleep(1)
++      Store (0x8D04, ST72)
++      Sleep(1)
++      Store (0x8D04, ST73)
++      Sleep(1)
++      Store (0x8D04, ST75)
++      Sleep(1)
++      Store (0x8D04, ST76)
++      Sleep(1)
++      Store (0x8D04, ST77)
++      Sleep(1)
++    }
++  }
++
++  Method (_PXM, 0, NotSerialized)
++  {
++    Return(0x01)
++  }
++}
++
++Device (PCI6)
++{                                            // PCI0 indicate host bridge 0
++  Name (_HID, "PNP0A08")                   // PCI Express Root Bridge
++  Name (_UID, 6)
++  Name (_CID, "PNP0A03")                   // Compatible PCI Root Bridge, Compatible ID
++  Name(_SEG, 0)                            // Segment of this Root complex
++  Name(_BBN, 0x80)                          // Base Bus Number ??
++  Name(_CCA, 1)                            // cache coherence attribute ??
++
++  Name (_PRT, Package (){
++    // INTx configure for RP0, whoes device number is 0
++    // For ESL/FPGA debug, we should modify this according to
++    // specific hardware configuration.
++    Package () {0xFFFF,0,0,640},         // INT_A
++    Package () {0xFFFF,1,0,641},         // INT_B
++    Package () {0xFFFF,2,0,642},         // INT_C
++    Package () {0xFFFF,3,0,643},         // INT_D
++
++    // This is an example of RP1 INTx configure. Adding or not
++    // adding RPx INTx configure deponds on hardware board topology,
++    // if UEFI enables RPx, RPy, RPz... related INTx configure
++    // should be added
++    Package () {0x04FFFF,0,0,640},         // INT_A
++    Package () {0x04FFFF,1,0,641},         // INT_B
++    Package () {0x04FFFF,2,0,642},         // INT_C
++    Package () {0x04FFFF,3,0,643},         // INT_D
++
++    Package () {0x08FFFF,0,0,640},         // INT_A
++    Package () {0x08FFFF,1,0,641},         // INT_B
++    Package () {0x08FFFF,2,0,642},         // INT_C
++    Package () {0x08FFFF,3,0,643},         // INT_D
++
++    Package () {0x0CFFFF,0,0,640},         // INT_A
++    Package () {0x0CFFFF,1,0,641},         // INT_B
++    Package () {0x0CFFFF,2,0,642},         // INT_C
++    Package () {0x0CFFFF,3,0,643},         // INT_D
++
++    Package () {0x10FFFF,0,0,640},         // INT_A
++    Package () {0x10FFFF,1,0,641},         // INT_B
++    Package () {0x10FFFF,2,0,642},         // INT_C
++    Package () {0x10FFFF,3,0,643},         // INT_D
++  })
++
++  Method (_CRS, 0, Serialized) {           // Root complex resources, _CRS: current resource setting
++    Name (RBUF, ResourceTemplate () {      // Name: 19.6.87, ResourceTemplate: 19.6.111,
++      WordBusNumber (                      // Bus numbers assigned to this root,
++        ResourceProducer,
++        MinFixed,
++        MaxFixed,
++        PosDecode,
++        0,                                 // AddressGranularity
++        0x80,                              // AddressMinimum - Minimum Bus Number
++        0x9f,                              // AddressMaximum - Maximum Bus Number
++        0,                                 // AddressTranslation - Set to 0
++        0x20                               // RangeLength - Number of Busses
++      )
++      QWordMemory (                        // 64-bit prefetch BAR windows
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        Prefetchable,
++        ReadWrite,
++        0x0,                               // Granularity
++        0x480000000000,                     // Min Base Address pci address
++        0x483fffffffff,                     // Max Base Address
++        0x0,                               // Translate
++        0x4000000000                       // Length, 256G
++      )
++      QWordMemory (                        // 32-bit non-prefetch BAR windows
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        Cacheable,
++        ReadWrite,
++        0x0,                               // Granularity
++        0xf0000000,                        // Min Base Address pci address
++        0xfffeffff,                        // Max Base Address
++        0x0,                               // Translate
++        0xfff0000                          // Length, 256M - 64K
++      )
++      QWordIO (
++        ResourceProducer,
++        MinFixed,
++        MaxFixed,
++        PosDecode,
++        EntireRange,
++        0x0,                               // Granularity
++        0x0,                               // Min Base Address
++        0xffff,                            // Max Base Address
++        0xffff0000,                        // Translate
++        0x10000                            // Length, 64K
++      )
++    })                                      // Name(RBUF)
++    Return (RBUF)
++  }                                         // Method(_CRS), this method return RBUF!
++
++  //
++  // OS Control Handoff
++  //
++  Name(SUPP, Zero) // PCI _OSC Support Field value
++  Name(CTRL, Zero) // PCI _OSC Control Field value
++
++  Method(_OSC,4) {
++    // Check for proper UUID
++    If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
++    // Create DWord-adressable fields from the Capabilities Buffer
++    CreateDWordField(Arg3,0,CDW1)
++    CreateDWordField(Arg3,4,CDW2)
++    CreateDWordField(Arg3,8,CDW3)
++
++    // Save Capabilities DWord2 & 3
++    Store(CDW2,SUPP)
++    Store(CDW3,CTRL)
++
++    // Only allow native hot plug control if OS supports:
++    //  ASPM
++    //  Clock PM
++    //  MSI/MSI-X
++    If(LNotEqual(And(SUPP, 0x16), 0x16)) {
++      And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
++    }
++
++    // Always allow native PME, AER (no dependencies)
++
++    // Never allow SHPC (no SHPC controller in this system)
++    And(CTRL,0x1D,CTRL)
++
++    If(LNotEqual(Arg1,One)) {  // Unknown revision
++      Or(CDW1,0x08,CDW1)
++    }
++
++    If(LNotEqual(CDW3,CTRL)) {  // Capabilities bits were masked
++      Or(CDW1,0x10,CDW1)
++    }
++
++    // Update DWORD3 in the buffer
++    Store(CTRL,CDW3)
++    Return(Arg3)
++    } Else {
++    Or(CDW1,4,CDW1) // Unrecognized UUID
++    Return(Arg3)
++    }
++  } // End _OSC
++
++  Method (_HPX, 0) {
++    Return (Package(2) {
++      Package(6) { // PCI Setting Record
++        0x00, // Type 0
++        0x01, // Revision 1
++        0x08, // CacheLineSize in DWORDS
++        0x40, // LatencyTimer in PCI clocks
++        0x01, // Enable SERR (Boolean)
++        0x01  // Enable PERR (Boolean)
++       },
++
++       Package(18){ // PCI-X Setting Record
++       0x02,      // Type 2
++       0x01,      // Revision 1
++       0xFFFFFFFF,  // Uncorrectable Error Mask Register AND Mask, Keep ->1
++       0x00000000,  // Uncorrectable Error Mask Register OR Mask, keep ->0
++       0xFFFFFFFF,  // Uncorrectable Error Severity Register AND Mask
++       0x00000000,  // Uncorrectable Error Severity Register OR Mask
++       0xFFFFFFFF,  // Correctable Error Mask Register AND Mask
++       0x00000000,  // Correctable Error Mask Register OR Mask
++       0xFFFFFFFF,  // Advanced Error Capabilities and Control Register AND Mask
++       0x00000000,  // Advanced Error Capabilities and Control Register OR Mask
++       0xFFF7,    // Device Control Register AND Mask
++       0x0007,    // Device Control Register OR Mask
++       0xFFFF,    // Link Control Register AND Mask
++       0x0000,    // Link Control Register OR Mask
++       0xFFFFFFFF,  // Secondary Uncorrectable Error Severity Register AND Mask
++       0x00000000,  // Secondary Uncorrectable Error Severity Register OR Mask
++       0xFFFFFFFF,  // Secondary Uncorrectable Error Mask Register AND Mask
++       0x00000000   // Secondary Uncorrectable Error Mask Register OR Mask
++     }
++   })
++ }
++
++  Method (_STA, 0x0, NotSerialized)
++  {
++    Return (0xf)
++  }
++
++  Method (_PXM, 0, NotSerialized)
++  {
++    Return(0x03)
++  }
++} // Device(PCI6)
++
++
++Device (PCI7)
++{                                          // PCI1 indicate host bridge 1
++  Name (_HID, "PNP0A08")                   // PCI Express Root Bridge
++  Name (_UID, 7)
++  Name (_CID, "PNP0A03")                   // Compatible PCI Root Bridge, Compatible ID
++  Name(_SEG, 0)                            // Segment of this Root complex
++  Name(_BBN, 0xbb)                         // Base Bus Number ??
++  Name(_CCA, 1)                            // cache coherence attribute ??
++  Method (_CRS, 0, Serialized) {           // Root complex resources, _CRS: current resource setting
++    Name (RBUF, ResourceTemplate () {      // Name: 19.6.87, ResourceTemplate: 19.6.111,
++      WordBusNumber (                      // Bus numbers assigned to this root,
++        ResourceProducer,
++        MinFixed,
++        MaxFixed,
++        PosDecode,
++        0,                                 // AddressGranularity
++        0xbb,                              // AddressMinimum - Minimum Bus Number
++        0xbb,                              // AddressMaximum - Maximum Bus Number
++        0,                                 // AddressTranslation - Set to 0
++        0x1                                // RangeLength - Number of Busses
++      )
++      QWordMemory (                        // 64-bit BAR Windows, where to show this ??
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        Prefetchable,
++        ReadWrite,
++        0x0,                               // Granularity
++        0x400148800000,                       // Min Base Address pci address ??
++        0x400148ffffff,                       // Max Base Address
++        0x0,                               // Translate
++        0x800000                           // Length, 8M
++      )
++    })                                      // Name(RBUF)
++    Return (RBUF)
++  }                                         // Method(_CRS), this method return RBUF!
++
++  Method (_STA, 0x0, NotSerialized)
++  {
++    Return (0xf)
++  }
++
++  Method (_PXM, 0, NotSerialized)
++  {
++    Return(0x03)
++  }
++} // Device(PCI7)
++
++Device (PCI8)
++{
++  Name (_HID, "PNP0A08")                   // PCI Express Root Bridge
++  Name (_UID, 8)
++  Name (_CID, "PNP0A03")                   // Compatible PCI Root Bridge, Compatible ID
++  Name(_SEG, 0)                            // Segment of this Root complex
++  Name(_BBN, 0xba)                         // Base Bus Number
++  Name(_CCA, 1)                            // cache coherence attribute ??
++  Name (_PRT, Package (){
++    Package () {0xFFFF,0,0,640},         // INT_A
++    Package () {0xFFFF,1,0,641},         // INT_B
++    Package () {0xFFFF,2,0,642},         // INT_C
++    Package () {0xFFFF,3,0,643},         // INT_D
++    Package () {0x1FFFF,0,0,640},         // INT_A
++    Package () {0x1FFFF,1,0,641},         // INT_B
++    Package () {0x1FFFF,2,0,642},         // INT_C
++    Package () {0x1FFFF,3,0,643},         // INT_D
++    Package () {0x2FFFF,0,0,640},         // INT_A
++    Package () {0x2FFFF,1,0,641},         // INT_B
++    Package () {0x2FFFF,2,0,642},         // INT_C
++    Package () {0x2FFFF,3,0,643},         // INT_D
++  })
++
++  Method (_CRS, 0, Serialized) {           // Root complex resources, _CRS: current resource //                               setting
++    Name (RBUF, ResourceTemplate () {      // Name: 19.6.87, ResourceTemplate: 19.6.111,
++      WordBusNumber (                      // Bus numbers assigned to this root,
++        ResourceProducer,
++        MinFixed,
++        MaxFixed,
++        PosDecode,
++        0,                                 // AddressGranularity
++        0xba,                              // AddressMinimum - Minimum Bus Number
++        0xba,                              // AddressMaximum - Maximum Bus Number
++        0,                                 // AddressTranslation - Set to 0
++        0x1                                // RangeLength - Number of Busses
++      )
++      QWordMemory (                        // 64-bit BAR Windows
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        Prefetchable,
++        ReadWrite,
++        0x0,                               // Granularity
++        0x40020c000000,                       // Min Base Address pci address
++        0x40020c1fffff,                       // Max Base Address
++        0x0,                               // Translate
++        0x200000                           // Length, 2M
++      )
++    })                                      // Name(RBUF)
++    Return (RBUF)
++  }                                         // Method(_CRS), this method return RBUF!
++
++  Method (_STA, 0x0, NotSerialized)
++  {
++    Return (0xf)
++  }
++
++  Method (_PXM, 0, NotSerialized)
++  {
++    Return(0x03)
++  }
++}// Device(PCI8)
++
++Device (PCI9)
++{
++  Name (_HID, "PNP0A08")                   // PCI Express Root Bridge
++  Name (_UID, 9)
++  Name (_CID, "PNP0A03")                   // Compatible PCI Root Bridge, Compatible ID
++  Name(_SEG, 0)                            // Segment of this Root complex
++  Name(_BBN, 0xb8)                         // Base Bus Number ??
++  Name(_CCA, 1)                            // cache coherence attribute ??
++  Method (_CRS, 0, Serialized) {           // Root complex resources, _CRS: current resource //                               setting
++    Name (RBUF, ResourceTemplate () {      // Name: 19.6.87, ResourceTemplate: 19.6.111,
++      WordBusNumber (                      // Bus numbers assigned to this root,
++        ResourceProducer,
++        MinFixed,
++        MaxFixed,
++        PosDecode,
++        0,                                 // AddressGranularity
++        0xb8,                              // AddressMinimum - Minimum Bus Number
++        0xb9,                              // AddressMaximum - Maximum Bus Number
++        0,                                 // AddressTranslation - Set to 0
++        0x2                                // RangeLength - Number of Busses
++      )
++      QWordMemory (                        // 64-bit BAR Windows
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        Prefetchable,
++        ReadWrite,
++        0x0,                               // Granularity
++        0x400208000000,                       // Min Base Address pci address
++        0x400208ffffff,                       // Max Base Address
++        0x0,                               // Translate
++        0x1000000                          // Length, 16M
++      )
++    })                                      // Name(RBUF)
++    Return (RBUF)
++  }                                         // Method(_CRS), this method return RBUF!
++
++  Method (_STA, 0x0, NotSerialized)
++  {
++    Return (0xf)
++  }
++
++  Method (_PXM, 0, NotSerialized)
++  {
++    Return(0x03)
++  }
++}// Device(PCI9)
++
++Device (PCIA)
++{
++  Name (_HID, "PNP0A08")                   // PCI Express Root Bridge
++  Name (_UID, 0xA)
++  Name (_CID, "PNP0A03")                   // Compatible PCI Root Bridge, Compatible ID
++  Name(_SEG, 0)                            // Segment of this Root complex
++  Name(_BBN, 0xbc)                         // Base Bus Number ??
++  Name(_CCA, 1)                            // cache coherence attribute ??
++  Method (_CRS, 0, Serialized) {           // Root complex resources, _CRS: current resource
++    Name (RBUF, ResourceTemplate () {      // Name: 19.6.87, ResourceTemplate: 19.6.111,
++      WordBusNumber (                      // Bus numbers assigned to this root,
++        ResourceProducer,
++        MinFixed,
++        MaxFixed,
++        PosDecode,
++        0,                                 // AddressGranularity
++        0xbc,                              // AddressMinimum - Minimum Bus Number
++        0xbd,                              // AddressMaximum - Maximum Bus Number
++        0,                                 // AddressTranslation - Set to 0
++        0x2                                // RangeLength - Number of Busses
++      )
++      QWordMemory (                        // 64-bit BAR Windows
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        Prefetchable,
++        ReadWrite,
++        0x0,                               // Granularity
++        0x400120000000,                       // Min Base Address pci address
++        0x40013fffffff,                       // Max Base Address
++        0x0,                               // Translate
++        0x20000000                         // Length, 512M
++      )
++    })                                      // Name(RBUF)
++    Return (RBUF)
++  }                                         // Method(_CRS), this method return RBUF!
++
++  Method (_STA, 0x0, NotSerialized)
++  {
++    Return (0x0F)
++  }
++
++  Method (_PXM, 0, NotSerialized)
++  {
++    Return(0x03)
++  }
++}// Device(PCIA)
++
++Device (PCIB)
++{
++  Name (_HID, "PNP0A08")                   // PCI Express Root Bridge
++  Name (_UID, 0xB)
++  Name (_CID, "PNP0A03")                   // Compatible PCI Root Bridge, Compatible ID
++  Name(_SEG, 0)                            // Segment of this Root complex
++  Name(_BBN, 0xb4)                         // Base Bus Number ??
++  Name(_CCA, 1)                            // cache coherence attribute ??
++
++  Name (_PRT, Package (){
++    Package () {0x2FFFF,0,0,640},         // INT_A
++    Package () {0x2FFFF,1,0,641},         // INT_B
++    Package () {0x2FFFF,2,0,642},         // INT_C
++    Package () {0x2FFFF,3,0,643},         // INT_D
++    Package () {0x3FFFF,0,0,640},         // INT_A
++    Package () {0x3FFFF,1,0,641},         // INT_B
++    Package () {0x3FFFF,2,0,642},         // INT_C
++    Package () {0x3FFFF,3,0,643},         // INT_D
++  })
++
++  Method (_CRS, 0, Serialized) {           // Root complex resources, _CRS: current resource setting
++    Name (RBUF, ResourceTemplate () {      // Name: 19.6.87, ResourceTemplate: 19.6.111,
++      WordBusNumber (                      // Bus numbers assigned to this root,
++        ResourceProducer,
++        MinFixed,
++        MaxFixed,
++        PosDecode,
++        0,                                 // AddressGranularity
++        0xb4,                              // AddressMinimum - Minimum Bus Number
++        0xb6,                              // AddressMaximum - Maximum Bus Number
++        0,                                 // AddressTranslation - Set to 0
++        0x3                                // RangeLength - Number of Busses
++      )
++      QWordMemory (                        // 64-bit BAR Windows
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        Prefetchable,
++        ReadWrite,
++        0x0,                               // Granularity
++        0x400144000000,                       // Min Base Address pci address
++        0x400147ffffff,                       // Max Base Address
++        0x0,                               // Translate
++        0x4000000                          // Length, 32M
++      )
++      QWordMemory (                        // 32-bit non-prefetch BAR Windows
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        Cacheable,
++        ReadWrite,
++        0x0,                                // Granularity
++        0xa3000000,                        // Min Base Address pci address
++        0xa3ffffff,                        // Max Base Address
++        0x0,                                // Translate
++        0x1000000                          // Length, 16M
++      )
++    })                                      // Name(RBUF)
++    Return (RBUF)
++  }                                         // Method(_CRS), this method return RBUF!
++
++  Method (_STA, 0x0, NotSerialized)
++  {
++    Return (0xf)
++  }
++
++  Method (_PXM, 0, NotSerialized)
++  {
++    Return(0x03)
++  }
++}
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Power.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Power.asl
+new file mode 100644
+index 0000000000..39553e01af
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Power.asl
+@@ -0,0 +1,28 @@
++/** @file
++  Differentiated System Description Table Fields (DSDT)
++
++  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++  Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
++  This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++
++**/
++
++Scope(_SB)
++{
++  Device(PWRB) {
++    Name(_HID, "PNP0C0C")
++    Name(_UID, Zero)
++    Method(_STA, 0x0, NotSerialized) {
++      Return(0xF)
++    }
++  }
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Rde.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Rde.asl
+new file mode 100644
+index 0000000000..1dcf1bba7e
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Rde.asl
+@@ -0,0 +1,47 @@
++/** @file
++  Differentiated System Description Table Fields (DSDT)
++
++  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
++    This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++
++**/
++
++Scope(_SB)
++{
++  Device(RDE0) {
++    Name(_HID, "HISI0201")
++    Name(_UID, 0)
++    Name(_CCA, 1)
++    Name (_CRS, ResourceTemplate ()  {
++      //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
++      QWordMemory (
++        ResourceConsumer,
++        ,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0,
++        0x209000000,
++        0x209ffffff,
++        0x0,
++        0x01000000
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI2")
++      { 586,587,588,589,590,591,592,593,594,595,596,597,598,599,600,601,
++        602,603,604,605,606,607,608,609,610,611,612,613,614,615,616,617
++      }
++    })
++  }
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Sec.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Sec.asl
+new file mode 100644
+index 0000000000..bba455468e
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Sec.asl
+@@ -0,0 +1,57 @@
++/** @file
++  Differentiated System Description Table Fields (DSDT)
++
++  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++  Copyright (c) 2018, Linaro Limited. All rights reserved.<BR>
++    This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++
++**/
++
++Scope(_SB)
++{
++  Device(SEC0) {
++    Name (_HID, "HISI0200")
++    Name(_UID, 0)
++    Name(_CCA, 1)
++    Name (_CRS, ResourceTemplate ()  {
++      //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
++      QWordMemory (
++        ResourceConsumer,
++        ,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0,
++        0x141000000,
++        0x141ffffff,
++        0x0,
++        0x01000000
++      )
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3")
++      {
++        624,625,626,627,628,629,630,631,632,633,634,635,636,637,638,639,
++        640,641,642,643,644,645,646,647,648,649,650,651,652,653,654,655
++      }
++    })
++  }
++
++  Device(SEC1) {
++    Name(_HID, "HISI0200")
++    Name(_UID, 1)
++    Name (_CRS, ResourceTemplate ()  {
++      Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive)
++      { 466,467
++      }
++    })
++  }
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c100k.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c100k.asl
+new file mode 100644
+index 0000000000..622355ade0
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c100k.asl
+@@ -0,0 +1,249 @@
++/** @file
++*
++*  Copyright (c) 2018 Hisilicon Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++//
++// GPIO
++//
++
++//#include "ArmPlatform.h"
++Scope(_SB)
++{
++Device(GPO0) {
++  Name(_HID, "HISI0181")
++  Name(_ADR, 0)
++  Name(_UID, 0)
++
++  Name (_CRS, ResourceTemplate ()  {
++    //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
++    QWordMemory (
++      ResourceConsumer,
++      ,
++      MinFixed,
++      MaxFixed,
++      NonCacheable,
++      ReadWrite,
++      0x0,
++      0x201120000,
++      0x20112ffff,
++      0x0,
++      0x10000
++    )
++    Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
++    {
++      476,
++    }
++  })
++
++  Device(PRTa) {
++    Name(_ADR, 0)
++    Name(_UID, 0)
++    Name(_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"reg", 0},
++        Package () {"snps,nr-gpios", 32},
++      }
++    })
++  }
++}
++
++/**
++*I2C for 100k release
++**/
++Device(I2C0) {
++  Name(_HID, "HISI02A2")
++  Name(_ADR, 0)
++  Name(_UID, 0)
++  Name(_DSD, Package () {
++    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++    Package () {
++      Package () {"i2c-sda-falling-time-ns", 913},
++      Package () {"i2c-scl-falling-time-ns", 303},
++      Package () {"i2c-sda-hold-time-ns", 1000},
++      Package () {"clock-frequency", 100000},
++    }
++  })
++
++  Name (_CRS, ResourceTemplate ()  {
++    //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
++    QWordMemory (
++      ResourceConsumer,
++      ,
++      MinFixed,
++      MaxFixed,
++      NonCacheable,
++      ReadWrite,
++      0x0,
++      0x201160000,
++      0x20116ffff,
++      0x0,
++      0x10000
++    )
++    Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
++    {
++      480,
++    }
++  })
++}
++
++
++/**
++*I2C for 100k vtof
++**/
++Device(I2C2) {
++  Name(_HID, "HISI0182")
++  Name(_ADR, 0)
++  Name(_UID, 0)
++  Name(_DSD, Package () {
++    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++    Package () {
++      Package () {"i2c-sda-falling-time-ns", 913},
++      Package () {"i2c-scl-falling-time-ns", 303},
++      Package () {"i2c-sda-hold-time-ns", 1000},
++      Package () {"clock-frequency", 100000},
++    }
++    })
++
++  Name (_CRS, ResourceTemplate ()  {
++    //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
++    QWordMemory (
++      ResourceConsumer,
++      ,
++      MinFixed,
++      MaxFixed,
++      NonCacheable,
++      ReadWrite,
++      0x0,
++      0x201160000,
++      0x20116ffff,
++      0x0,
++      0x10000
++    )
++    Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
++    {
++      480,
++    }
++  })
++}
++
++/**
++*I2C for 400k fpga
++**/
++Device(I2C3) {
++  Name(_HID, "HISI0183")
++  Name(_ADR, 0)
++  Name(_UID, 0)
++  Name(_DSD, Package () {
++    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++    Package () {
++      Package () {"i2c-sda-falling-time-ns", 300},
++      Package () {"i2c-scl-falling-time-ns", 100},
++      Package () {"i2c-sda-hold-time-ns", 250},
++      Package () {"clock-frequency", 400000},
++    }
++    })
++
++  Name (_CRS, ResourceTemplate ()  {
++  //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
++  QWordMemory (
++    ResourceConsumer,
++    ,
++    MinFixed,
++    MaxFixed,
++    NonCacheable,
++    ReadWrite,
++    0x0,
++    0x201160000,
++    0x20116ffff,
++    0x0,
++    0x10000
++  )
++  Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
++  {
++    480,
++  }
++  })
++}
++
++Device(LPC) {
++  Name(_HID, "HISI0191")
++  Name(_ADR, 0)
++  Name(_UID, 0)
++  Name(_DSD, Package () {
++    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++    Package () {
++    }
++  })
++
++  Name (_CRS, ResourceTemplate ()  {
++  Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
++  {
++    484,
++    490
++  }
++  })
++}
++
++Device(NAD) {
++  Name(_HID, "HISI0192")
++  Name(_ADR, 0)
++  Name(_UID, 0)
++  Name(_CCA, 1)
++  Name(_DSD, Package () {
++    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++    Package () {
++      Package () {"nand-bus-width", 8},
++      Package () {"nand-ecc-mode", "hw"},
++      Package () {"nand-ecc-strength", 24},
++      Package () {"nand-ecc-step-size", 1024},
++    }
++  })
++
++  Name (_CRS, ResourceTemplate ()  {
++    //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
++    QWordMemory (
++      ResourceConsumer,
++      ,
++      MinFixed,
++      MaxFixed,
++      NonCacheable,
++      ReadWrite,
++      0x0,
++      0x206220000,
++      0x20622ffff,
++      0x0,
++      0x10000
++    )
++
++    QWordMemory (
++      ResourceConsumer,
++      ,
++      MinFixed,
++      MaxFixed,
++      NonCacheable,
++      ReadWrite,
++      0x0,
++      0x206210000,
++      0x20621ffff,
++      0x0,
++      0x10000
++    )
++
++    Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
++    {
++      483,
++    }
++  })
++}
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c400k.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c400k.asl
+new file mode 100644
+index 0000000000..5db4284467
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c400k.asl
+@@ -0,0 +1,249 @@
++/** @file
++*
++*  Copyright (c) 2018 Hisilicon Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++//
++// GPIO
++//
++
++//#include "ArmPlatform.h"
++Scope(_SB)
++{
++  Device(GPO0) {
++  Name(_HID, "HISI0181")
++  Name(_ADR, 0)
++  Name(_UID, 0)
++
++  Name (_CRS, ResourceTemplate ()  {
++    //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
++    QWordMemory (
++      ResourceConsumer,
++      ,
++      MinFixed,
++      MaxFixed,
++      NonCacheable,
++      ReadWrite,
++      0x0,
++      0x201120000,
++      0x20112ffff,
++      0x0,
++      0x10000
++    )
++    Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
++    {
++      476,
++    }
++  })
++
++  Device(PRTa) {
++    Name(_ADR, 0)
++    Name(_UID, 0)
++    Name(_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"reg", 0},
++        Package () {"snps,nr-gpios", 32},
++      }
++    })
++  }
++
++  }
++
++/**
++*I2C for 400k release
++**/
++Device(I2C1) {
++  Name(_HID, "HISI02A2")
++  Name(_ADR, 0)
++  Name(_UID, 0)
++  Name(_DSD, Package () {
++    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++    Package () {
++      Package () {"i2c-sda-falling-time-ns", 500},
++      Package () {"i2c-scl-falling-time-ns", 100},
++      Package () {"i2c-sda-hold-time-ns", 250},
++      Package () {"clock-frequency", 400000},
++    }
++  })
++
++  Name (_CRS, ResourceTemplate ()  {
++    //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
++    QWordMemory (
++      ResourceConsumer,
++      ,
++      MinFixed,
++      MaxFixed,
++      NonCacheable,
++      ReadWrite,
++      0x0,
++      0x201160000,
++      0x20116ffff,
++      0x0,
++      0x10000
++    )
++    Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
++    {
++      480,
++    }
++  })
++}
++
++/**
++*I2C for 100k vtof
++**/
++Device(I2C2) {
++  Name(_HID, "HISI0182")
++  Name(_ADR, 0)
++  Name(_UID, 0)
++  Name(_DSD, Package () {
++    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++    Package () {
++      Package () {"i2c-sda-falling-time-ns", 913},
++      Package () {"i2c-scl-falling-time-ns", 303},
++      Package () {"i2c-sda-hold-time-ns", 1000},
++      Package () {"clock-frequency", 100000},
++    }
++  })
++
++  Name (_CRS, ResourceTemplate ()  {
++    //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
++    QWordMemory (
++      ResourceConsumer,
++      ,
++      MinFixed,
++      MaxFixed,
++      NonCacheable,
++      ReadWrite,
++      0x0,
++      0x201160000,
++      0x20116ffff,
++      0x0,
++      0x10000
++    )
++    Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
++    {
++      480,
++    }
++  })
++}
++
++/**
++*I2C for 400k fpga
++**/
++Device(I2C3) {
++  Name(_HID, "HISI0183")
++  Name(_ADR, 0)
++  Name(_UID, 0)
++  Name(_DSD, Package () {
++    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++    Package () {
++      Package () {"i2c-sda-falling-time-ns", 300},
++      Package () {"i2c-scl-falling-time-ns", 100},
++      Package () {"i2c-sda-hold-time-ns", 250},
++      Package () {"clock-frequency", 400000},
++    }
++  })
++
++  Name (_CRS, ResourceTemplate ()  {
++    //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
++    QWordMemory (
++      ResourceConsumer,
++      ,
++      MinFixed,
++      MaxFixed,
++      NonCacheable,
++      ReadWrite,
++      0x0,
++      0x201160000,
++      0x20116ffff,
++      0x0,
++      0x10000
++    )
++    Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
++    {
++      480,
++    }
++  })
++}
++
++Device(LPC) {
++  Name(_HID, "HISI0191")
++  Name(_ADR, 0)
++  Name(_UID, 0)
++  Name(_DSD, Package () {
++    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++    Package () {
++    }
++  })
++
++  Name (_CRS, ResourceTemplate ()  {
++    Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
++    {
++      484,
++      490
++    }
++  })
++}
++
++Device(NAD) {
++  Name(_HID, "HISI0192")
++  Name(_ADR, 0)
++  Name(_UID, 0)
++  Name(_CCA, 1)
++  Name(_DSD, Package () {
++    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++    Package () {
++      Package () {"nand-bus-width", 8},
++      Package () {"nand-ecc-mode", "hw"},
++      Package () {"nand-ecc-strength", 24},
++      Package () {"nand-ecc-step-size", 1024},
++    }
++    })
++
++  Name (_CRS, ResourceTemplate ()  {
++    //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
++    QWordMemory (
++      ResourceConsumer,
++      ,
++      MinFixed,
++      MaxFixed,
++      NonCacheable,
++      ReadWrite,
++      0x0,
++      0x206220000,
++      0x20622ffff,
++      0x0,
++      0x10000
++    )
++
++    QWordMemory (
++      ResourceConsumer,
++      ,
++      MinFixed,
++      MaxFixed,
++      NonCacheable,
++      ReadWrite,
++      0x0,
++      0x206210000,
++      0x20621ffff,
++      0x0,
++      0x10000
++    )
++
++    Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
++    {
++      483,
++    }
++  })
++}
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/LpcUart_clk.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/LpcUart_clk.asl
+new file mode 100644
+index 0000000000..14e36353ad
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/LpcUart_clk.asl
+@@ -0,0 +1,49 @@
++/** @file
++  Differentiated System Description Table Fields (DSDT)
++
++  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
++    This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++
++**/
++
++Scope(_SB)
++{
++  Device(UART) {
++    Name(_HID, "PNP0501")
++    Name(_UID, 0)
++    Name(_CCA, 1)
++    Name(_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"clock-frequency", 1843200},
++      }
++    })
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++        ResourceConsumer,
++        ,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0,
++        0x3f00003f8,
++        0x3f00003ff,
++        0x0,
++        0x8
++      )
++      Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 484 }
++    })
++  }
++}
++
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Pv680UncorePmu.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Pv680UncorePmu.asl
+new file mode 100644
+index 0000000000..65c3eccf0a
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Pv680UncorePmu.asl
+@@ -0,0 +1,1658 @@
++/** @file
++  Differentiated System Description Table Fields (DSDT)
++
++  Copyright (c) 2017, ARM Ltd. All rights reserved.<BR>
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++  Copyright (c) 2017, Linaro Limited. All rights reserved.<BR>
++    This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++
++**/
++
++Scope(_SB)
++{
++    // L3T0 for S0_TB(DieID:3)
++    Device (L300) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x90180000, // Min Base Address
++        0x9018FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB30")
++      {
++        832,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x03},
++        Package () {"hisilicon,ccl-id", 0x00},
++      }
++    })
++
++  }
++  // L3T1 for S0_TB(DieID:3)
++  Device (L301) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 1) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x90190000, // Min Base Address
++        0x9019FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB31")
++      {
++        833,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x03},
++        Package () {"hisilicon,ccl-id", 0x01},
++      }
++    })
++
++  }
++
++  // L3T2 for S0_TB(DieID:3)
++  Device (L302) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 2) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x901A0000, // Min Base Address
++        0x901AFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB32")
++      {
++        834,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x03},
++        Package () {"hisilicon,ccl-id", 0x02},
++      }
++    })
++
++  }
++
++  // L3T3 for S0_TB(DieID:3)
++  Device (L303) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 3) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x901B0000, // Min Base Address
++        0x901BFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB33")
++      {
++        835,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x03},
++        Package () {"hisilicon,ccl-id", 0x03},
++      }
++    })
++
++  }
++  // L3T4 for S0_TB(DieID:3)
++  Device (L304) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 4) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x901C0000, // Min Base Address
++        0x901CFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB34")
++      {
++        836,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x03},
++        Package () {"hisilicon,ccl-id", 0x04},
++      }
++    })
++
++  }
++  // L3T5 for S0_TB(DieID:3)
++  Device (L305) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 5) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x901D0000, // Min Base Address
++        0x901DFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB35")
++      {
++        837,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x03},
++        Package () {"hisilicon,ccl-id", 0x05},
++      }
++    })
++
++  }
++
++  // DDRC0 for S0_TB(DieID:3)
++  Device (DDR0) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 0) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // DDRC address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x94D20000, // Min Base Address
++        0x94D2FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB38")
++      {
++        844,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x03},
++        Package () {"hisilicon,ch-id", 0x0},
++      }
++    })
++
++  }
++  // DDRC1 for S0_TB(DieID:3)
++  Device (DDR1) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 1) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // DDRC address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x94D30000, // Min Base Address
++        0x94D3FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB39")
++      {
++        845,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x03},
++        Package () {"hisilicon,ch-id", 0x1},
++      }
++    })
++
++  }
++  // DDRC2 for S0_TB(DieID:3)
++  Device (DDR2) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 2) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // DDRC address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x94D40000, // Min Base Address
++        0x94D4FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB3A")
++      {
++        846,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x03},
++        Package () {"hisilicon,ch-id", 0x2},
++      }
++    })
++
++  }
++  // DDRC3 for S0_TB(DieID:3)
++  Device (DDR3) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 3) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // DDRC address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x94D50000, // Min Base Address
++        0x94D5FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB3B")
++      {
++        847,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x03},
++        Package () {"hisilicon,ch-id", 0x3},
++      }
++    })
++
++  }
++
++  // HHA0 for S0_TB(DieID:3)
++  Device (HHA0) {
++    Name (_HID, "HISI0243")  // _HID: Hardware ID
++    Name (_UID, 0)  // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // HHA address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x90120000, // Min Base Address
++        0x9012FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB3C")
++      {
++        848,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x03}
++      }
++    })
++  }
++
++  // HHA1 for S0_TB(DieID:3)
++  Device (HHA1) {
++    Name (_HID, "HISI0243")  // _HID: Hardware ID
++    Name (_UID, 1)  // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // HHA address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x90130000, // Min Base Address
++        0x9013FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++    Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB3D")
++    {
++      849,
++    }
++  })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x03}
++      }
++    })
++  }
++
++  // L3T0 for S0_TA(DieID:1)
++  Device (L308) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x08) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x98180000, // Min Base Address
++        0x9818FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB10")
++      {
++        832,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x01},
++        Package () {"hisilicon,ccl-id", 0x00},
++      }
++    })
++
++  }
++  // L3T1 for S0_TA(DieID:1)
++  Device (L309) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x09) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x98190000, // Min Base Address
++        0x9819FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB11")
++      {
++        833,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x01},
++        Package () {"hisilicon,ccl-id", 0x01},
++      }
++    })
++
++  }
++
++  // L3T2 for S0_TA(DieID:1)
++  Device (L30A) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x0A) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x981A0000, // Min Base Address
++        0x981AFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB12")
++      {
++        834,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x01},
++        Package () {"hisilicon,ccl-id", 0x02},
++      }
++    })
++
++  }
++
++  // L3T3 for S0_TA(DieID:1)
++  Device (L30B) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x0B) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x981B0000, // Min Base Address
++        0x981BFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB13")
++      {
++        835,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x01},
++        Package () {"hisilicon,ccl-id", 0x03},
++      }
++    })
++
++  }
++  // L3T4 for S0_TA(DieID:1)
++  Device (L30C) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x0C) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x981C0000, // Min Base Address
++        0x981CFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB14")
++      {
++        836,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x01},
++        Package () {"hisilicon,ccl-id", 0x04},
++      }
++    })
++
++  }
++  // L3T5 for S0_TA(DieID:1)
++  Device (L30D) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x0D) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x981D0000, // Min Base Address
++        0x981DFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB15")
++      {
++        837,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x01},
++        Package () {"hisilicon,ccl-id", 0x05},
++      }
++    })
++
++  }
++
++  // DDRC0 for S0_TA(DieID:1)
++  Device (DDR4) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 4) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x9CD20000, // Min Base Address
++        0x9CD2FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB18")
++      {
++        844,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x01},
++        Package () {"hisilicon,ch-id", 0x0},
++      }
++    })
++
++  }
++  // DDRC1 for S0_TA(DieID:1)
++  Device (DDR5) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 5) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x9CD30000, // Min Base Address
++        0x9CD3FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB19")
++      {
++        845,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x01},
++        Package () {"hisilicon,ch-id", 0x1},
++      }
++    })
++
++  }
++  // DDRC2 for S0_TA(DieID:1)
++  Device (DDR6) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 6) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x9CD40000, // Min Base Address
++        0x9CD4FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB1A")
++      {
++        846,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x01},
++        Package () {"hisilicon,ch-id", 0x2},
++      }
++    })
++
++  }
++  // DDRC3 for S0_TA(DieID:1)
++  Device (DDR7) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 7) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x9CD50000, // Min Base Address
++        0x9CD5FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB1B")
++      {
++        847,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x01},
++        Package () {"hisilicon,ch-id", 0x3},
++      }
++    })
++  }
++
++  // HHA0 for S0_TA(DieID:1)
++  Device (HHA2) {
++    Name (_HID, "HISI0243")  // _HID: Hardware ID
++    Name (_UID, 2)  // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // HHA address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x98120000, // Min Base Address
++        0x9812FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB1C")
++      {
++        848,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x01}
++      }
++    })
++  }
++
++  // HHA1 for S0_TA(DieID:1)
++  Device (HHA3) {
++    Name (_HID, "HISI0243")  // _HID: Hardware ID
++    Name (_UID, 3)  // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // HHA address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x98130000, // Min Base Address
++        0x9813FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++    Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB1D")
++    {
++      849,
++    }
++  })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x01}
++      }
++    })
++  }
++
++  // It is the list PMU node of Socket1
++  // L3T0 for S1_TB(DieID:7)
++    Device (L310) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x10) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x400090180000, // Min Base Address
++        0x40009018FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB70")
++      {
++        832,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x07},
++        Package () {"hisilicon,ccl-id", 0x00},
++      }
++    })
++
++  }
++  // L3T1 for S1_TB(DieID:7)
++  Device (L311) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x11) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x400090190000, // Min Base Address
++        0x40009019FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB71")
++      {
++        833,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x07},
++        Package () {"hisilicon,ccl-id", 0x01},
++      }
++    })
++
++  }
++
++  // L3T2 for S1_TB(DieID:7)
++  Device (L312) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x12) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x4000901A0000, // Min Base Address
++        0x4000901AFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB72")
++      {
++        834,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x07},
++        Package () {"hisilicon,ccl-id", 0x02},
++      }
++    })
++
++  }
++
++  // L3T3 for S1_TB(DieID:7)
++  Device (L313) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x13) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x4000901B0000, // Min Base Address
++        0x4000901BFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB73")
++      {
++        835,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x07},
++        Package () {"hisilicon,ccl-id", 0x03},
++      }
++    })
++
++  }
++  // L3T4 for S1_TB(DieID:7)
++  Device (L314) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x14) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x4000901C0000, // Min Base Address
++        0x4000901CFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB74")
++      {
++        836,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x07},
++        Package () {"hisilicon,ccl-id", 0x04},
++      }
++    })
++
++  }
++  // L3T5 for S1_TB(DieID:7)
++  Device (L315) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x15) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x4000901D0000, // Min Base Address
++        0x4000901DFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB75")
++      {
++        837,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x07},
++        Package () {"hisilicon,ccl-id", 0x05},
++      }
++    })
++
++  }
++
++  // DDRC0 for S1_TB(DieID:7)
++  Device (DDR8) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 8) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // DDRC address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x400094D20000, // Min Base Address
++        0x400094D2FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB78")
++      {
++        844,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x07},
++        Package () {"hisilicon,ch-id", 0x0},
++      }
++    })
++
++  }
++  // DDRC1 for S1_TB(DieID:7)
++  Device (DDR9) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 9) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // DDRC address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x400094D30000, // Min Base Address
++        0x400094D3FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB79")
++      {
++        845,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x07},
++        Package () {"hisilicon,ch-id", 0x1},
++      }
++    })
++
++  }
++  // DDRC2 for S1_TB(DieID:7)
++  Device (DDRA) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 0xA) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // DDRC address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x400094D40000, // Min Base Address
++        0x400094D4FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB7A")
++      {
++        846,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x07},
++        Package () {"hisilicon,ch-id", 0x2},
++      }
++    })
++
++  }
++  // DDRC3 for S1_TB(DieID:7)
++  Device (DDRB) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 0xB) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // DDRC address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x400094D50000, // Min Base Address
++        0x400094D5FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB7B")
++      {
++        847,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x07},
++        Package () {"hisilicon,ch-id", 0x3},
++      }
++    })
++
++  }
++
++  // HHA0 for S1_TB(DieID:7)
++  Device (HHA4) {
++    Name (_HID, "HISI0243")  // _HID: Hardware ID
++    Name (_UID, 4)  // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // HHA address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x400090120000, // Min Base Address
++        0x40009012FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB7C")
++      {
++        848,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x07}
++      }
++    })
++  }
++
++  // HHA1 for S1_TB(DieID:7)
++  Device (HHA5) {
++    Name (_HID, "HISI0243")  // _HID: Hardware ID
++    Name (_UID, 5)  // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // HHA address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x400090130000, // Min Base Address
++        0x40009013FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++    Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB7D")
++    {
++      849,
++    }
++  })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x07}
++      }
++    })
++  }
++
++  // L3T0 for S1_TA(DieID:5)
++  Device (L318) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x18) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x400098180000, // Min Base Address
++        0x40009818FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB50")
++      {
++        832,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x05},
++        Package () {"hisilicon,ccl-id", 0x00},
++      }
++    })
++
++  }
++  // L3T1 for S1_TA(DieID:5)
++  Device (L319) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x19) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x400098190000, // Min Base Address
++        0x40009819FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB51")
++      {
++        833,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x05},
++        Package () {"hisilicon,ccl-id", 0x01},
++      }
++    })
++
++  }
++
++  // L3T2 for S1_TA(DieID:5)
++  Device (L31A) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x1A) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x4000981A0000, // Min Base Address
++        0x4000981AFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB52")
++      {
++        834,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x05},
++        Package () {"hisilicon,ccl-id", 0x02},
++      }
++    })
++
++  }
++
++  // L3T3 for S1_TA(DieID:5)
++  Device (L31B) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x1B) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x4000981B0000, // Min Base Address
++        0x4000981BFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB53")
++      {
++        835,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x05},
++        Package () {"hisilicon,ccl-id", 0x03},
++      }
++    })
++
++  }
++  // L3T4 for S1_TA(DieID:5)
++  Device (L31C) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x1C) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x4000981C0000, // Min Base Address
++        0x4000981CFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB54")
++      {
++        836,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x05},
++        Package () {"hisilicon,ccl-id", 0x04},
++      }
++    })
++
++  }
++  // L3T5 for S1_TA(DieID:5)
++  Device (L31D) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x1D) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x4000981D0000, // Min Base Address
++        0x4000981DFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB55")
++      {
++        837,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x05},
++        Package () {"hisilicon,ccl-id", 0x05},
++      }
++    })
++
++  }
++
++  // DDRC0 for S1_TA(DieID:5)
++  Device (DDRC) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 0xC) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x40009CD20000, // Min Base Address
++        0x40009CD2FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB58")
++      {
++        844,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x05},
++        Package () {"hisilicon,ch-id", 0x0},
++      }
++    })
++
++  }
++  // DDRC1 for S1_TA(DieID:5)
++  Device (DDRD) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 0xD) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x40009CD30000, // Min Base Address
++        0x40009CD3FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB59")
++      {
++        845,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x05},
++        Package () {"hisilicon,ch-id", 0x1},
++      }
++    })
++
++  }
++  // DDRC2 for S1_TA(DieID:5)
++  Device (DDRE) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 0xE) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x40009CD40000, // Min Base Address
++        0x40009CD4FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB5A")
++      {
++        846,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x05},
++        Package () {"hisilicon,ch-id", 0x2},
++      }
++    })
++
++  }
++  // DDRC3 for S1_TA(DieID:5)
++  Device (DDRF) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 0xF) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x40009CD50000, // Min Base Address
++        0x40009CD5FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB5B")
++      {
++        847,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x05},
++        Package () {"hisilicon,ch-id", 0x3},
++      }
++    })
++  }
++
++    // HHA0 for S1_TA(DieID:5)
++  Device (HHA6) {
++    Name (_HID, "HISI0243")  // _HID: Hardware ID
++    Name (_UID, 6)  // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // HHA address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x400098120000, // Min Base Address
++        0x40009812FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB5C")
++      {
++        848,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x05}
++      }
++    })
++  }
++  // HHA1 for S0_TA(DieID:5)
++  Device (HHA7) {
++    Name (_HID, "HISI0243")  // _HID: Hardware ID
++    Name (_UID, 7)  // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // HHA address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x400098130000, // Min Base Address
++        0x40009813FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++    Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB5D")
++    {
++      849,
++    }
++  })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x05}
++      }
++    })
++  }
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/ipmi.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/ipmi.asl
+new file mode 100644
+index 0000000000..555fe39936
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/ipmi.asl
+@@ -0,0 +1,49 @@
++/** @file
++*
++*  Copyright (c) 2018 Hisilicon Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++//
++// LPC
++//
++
++Scope(_SB) {
++  Device (IPI0) {
++  Name (_HID, "IPI0001")
++  Name (_UID, 0)
++  Name (_STR, Unicode("IPMI_BT"))
++  Name(_CCA, 1)
++  //Name (_CID, "IPI0001")
++  Method (_IFT) {
++    Return (0x03)
++  }
++  Method (_SRV) {
++    Return (0x0200)   // IPMI Spec Revision 2.0
++  }
++  Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++    QWordMemory ( // BMC memory region
++      ResourceConsumer,
++      PosDecode,
++      MinFixed,
++      MaxFixed,
++      Cacheable,
++      ReadWrite,
++      0x0, // Granularity
++      0x3f00000e4, // Min Base Address
++      0x3f00000e7, // Max Base Address
++      0x0, // Translate
++      0x4 // Length
++    )
++    Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 484 }
++  })
++  }
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Facs.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Facs.aslc
+new file mode 100644
+index 0000000000..9e57936b85
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Facs.aslc
+@@ -0,0 +1,67 @@
++/** @file
++*  Firmware ACPI Control Structure (FACS)
++*
++*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2015, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++*
++**/
++
++#include <IndustryStandard/Acpi.h>
++
++EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = {
++  EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32  Signature
++  sizeof (EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE),  // UINT32  Length
++  0xA152,                                                 // UINT32  HardwareSignature
++  0,                                                      // UINT32  FirmwareWakingVector
++  0,                                                      // UINT32  GlobalLock
++  0,                                                      // UINT32  Flags
++  0,                                                      // UINT64  XFirmwareWakingVector
++  EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION,   // UINT8   Version;
++    { EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved0[0]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved0[1]
++      EFI_ACPI_RESERVED_BYTE },                           // UINT8   Reserved0[2]
++  0,                                                      // UINT32  OspmFlags  "Platform firmware must
++                                                          //                    initialize this field to zero."
++    { EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[0]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[1]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[2]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[3]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[4]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[5]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[6]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[7]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[8]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[9]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[10]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[11]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[12]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[13]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[14]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[15]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[16]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[17]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[18]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[19]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[20]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[21]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[22]
++      EFI_ACPI_RESERVED_BYTE },                           // UINT8   Reserved1[23]
++};
++
++//
++// Reference the table being generated to prevent the optimizer from removing the
++// data structure from the executable
++//
++VOID* CONST ReferenceAcpiTable = &Facs;
++
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Fadt.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Fadt.aslc
+new file mode 100644
+index 0000000000..e7ee6981ec
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Fadt.aslc
+@@ -0,0 +1,91 @@
++/** @file
++*  Fixed ACPI Description Table (FADT)
++*
++*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2015, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++*
++**/
++
++#include "Hi1620Platform.h"
++
++#include <Library/AcpiLib.h>
++#include <IndustryStandard/Acpi.h>
++
++EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
++  ARM_ACPI_HEADER (
++    EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
++    EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE,
++    EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
++  ),
++  0,                                                                        // UINT32     FirmwareCtrl
++  0,                                                                        // UINT32     Dsdt
++  EFI_ACPI_RESERVED_BYTE,                                                   // UINT8      Reserved0
++  EFI_ACPI_6_2_PM_PROFILE_UNSPECIFIED,                                      // UINT8      PreferredPmProfile
++  0,                                                                        // UINT16     SciInt
++  0,                                                                        // UINT32     SmiCmd
++  0,                                                                        // UINT8      AcpiEnable
++  0,                                                                        // UINT8      AcpiDisable
++  0,                                                                        // UINT8      S4BiosReq
++  0,                                                                        // UINT8      PstateCnt
++  0,                                                                        // UINT32     Pm1aEvtBlk
++  0,                                                                        // UINT32     Pm1bEvtBlk
++  0,                                                                        // UINT32     Pm1aCntBlk
++  0,                                                                        // UINT32     Pm1bCntBlk
++  0,                                                                        // UINT32     Pm2CntBlk
++  0,                                                                        // UINT32     PmTmrBlk
++  0,                                                                        // UINT32     Gpe0Blk
++  0,                                                                        // UINT32     Gpe1Blk
++  0,                                                                        // UINT8      Pm1EvtLen
++  0,                                                                        // UINT8      Pm1CntLen
++  0,                                                                        // UINT8      Pm2CntLen
++  0,                                                                        // UINT8      PmTmrLen
++  0,                                                                        // UINT8      Gpe0BlkLen
++  0,                                                                        // UINT8      Gpe1BlkLen
++  0,                                                                        // UINT8      Gpe1Base
++  0,                                                                        // UINT8      CstCnt
++  0,                                                                        // UINT16     PLvl2Lat
++  0,                                                                        // UINT16     PLvl3Lat
++  0,                                                                        // UINT16     FlushSize
++  0,                                                                        // UINT16     FlushStride
++  0,                                                                        // UINT8      DutyOffset
++  0,                                                                        // UINT8      DutyWidth
++  0,                                                                        // UINT8      DayAlrm
++  0,                                                                        // UINT8      MonAlrm
++  0,                                                                        // UINT8      Century
++  0,                                                                        // UINT16     IaPcBootArch
++  0,                                                                        // UINT8      Reserved1
++  EFI_ACPI_6_2_HW_REDUCED_ACPI | EFI_ACPI_6_2_LOW_POWER_S0_IDLE_CAPABLE,    // UINT32     Flags
++  NULL_GAS,                                                                 // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  ResetReg
++  0,                                                                        // UINT8      ResetValue
++  EFI_ACPI_6_2_ARM_PSCI_COMPLIANT,                                          // UINT16     ArmBootArchFlags
++  EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION,                 // UINT8      MinorRevision
++  0,                                                                        // UINT64     XFirmwareCtrl
++  0,                                                                        // UINT64     XDsdt
++  NULL_GAS,                                                                 // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XPm1aEvtBlk
++  NULL_GAS,                                                                 // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XPm1bEvtBlk
++  NULL_GAS,                                                                 // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XPm1aCntBlk
++  NULL_GAS,                                                                 // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XPm1bCntBlk
++  NULL_GAS,                                                                 // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XPm2CntBlk
++  NULL_GAS,                                                                 // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XPmTmrBlk
++  NULL_GAS,                                                                 // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XGpe0Blk
++  NULL_GAS,                                                                 // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XGpe1Blk
++  NULL_GAS,                                                                 // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  SleepControlReg
++  NULL_GAS                                                                 // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  SleepStatusReg
++};
++
++//
++// Reference the table being generated to prevent the optimizer from removing the
++// data structure from the executable
++//
++VOID* CONST ReferenceAcpiTable = &Fadt;
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Gtdt.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Gtdt.aslc
+new file mode 100644
+index 0000000000..45f5d20704
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Gtdt.aslc
+@@ -0,0 +1,86 @@
++/** @file
++*  Generic Timer Description Table (GTDT)
++*
++*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2015, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++*
++**/
++
++#include "Hi1620Platform.h"
++
++#include <Library/AcpiLib.h>
++#include <Library/PcdLib.h>
++#include <IndustryStandard/Acpi.h>
++
++#define GTDT_TIMER_EDGE_TRIGGERED   EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
++#define GTDT_TIMER_LEVEL_TRIGGERED  0
++#define GTDT_TIMER_ACTIVE_LOW       EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
++#define GTDT_TIMER_ACTIVE_HIGH      0
++#define SYSTEM_TIMER_BASE_ADDRESS     0xFFFFFFFFFFFFFFFF
++
++#define GTDT_GTIMER_FLAGS           (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
++
++#pragma pack (1)
++
++typedef struct {
++  EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE          Gtdt;
++  EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE     Watchdogs[HI1620_WATCHDOG_COUNT];
++} EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLES;
++
++#pragma pack ()
++
++EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
++  {
++    ARM_ACPI_HEADER(
++      EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
++      EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE,
++      EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
++    ),
++    SYSTEM_TIMER_BASE_ADDRESS,                    // UINT64  PhysicalAddress
++    0,                                            // UINT32  Reserved
++    FixedPcdGet32 (PcdArmArchTimerSecIntrNum),    // UINT32  SecurePL1TimerGSIV
++    GTDT_GTIMER_FLAGS,                            // UINT32  SecurePL1TimerFlags
++    FixedPcdGet32 (PcdArmArchTimerIntrNum),       // UINT32  NonSecurePL1TimerGSIV
++    GTDT_GTIMER_FLAGS,                            // UINT32  NonSecurePL1TimerFlags
++    FixedPcdGet32 (PcdArmArchTimerVirtIntrNum),   // UINT32  VirtualTimerGSIV
++    GTDT_GTIMER_FLAGS,                            // UINT32  VirtualTimerFlags
++    FixedPcdGet32 (PcdArmArchTimerHypIntrNum),    // UINT32  NonSecurePL2TimerGSIV
++    GTDT_GTIMER_FLAGS,                            // UINT32  NonSecurePL2TimerFlags
++    0xFFFFFFFFFFFFFFFF,                           // UINT64  CntReadBasePhysicalAddress
++#ifdef notyet
++    PV660_WATCHDOG_COUNT,                          // UINT32  PlatformTimerCount
++    sizeof (EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
++  },
++  {
++    {
++      EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG, sizeof(EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE),
++      EFI_ACPI_RESERVED_BYTE, 0, 0, 0, 0
++    },
++    {
++      EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG, sizeof(EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE),
++      EFI_ACPI_RESERVED_BYTE, 0, 0, 0, 0
++    }
++  }
++#else /* !notyet */
++  0, 0
++  }
++#endif
++  };
++
++//
++// Reference the table being generated to prevent the optimizer from removing the
++// data structure from the executable
++//
++VOID* CONST ReferenceAcpiTable = &Gtdt;
++
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc
+new file mode 100644
+index 0000000000..342ec33629
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc
+@@ -0,0 +1,86 @@
++/*
++ * Copyright (c) 2018 Linaro Limited
++ * Copyright (c) 2018 Hisilicon Limited
++ *
++ * All rights reserved. This program and the accompanying materials
++ * are made available under the terms of the BSD License which accompanies
++ * this distribution, and is available at
++ * http://opensource.org/licenses/bsd-license.php
++ *
++*/
++
++#include <IndustryStandard/Acpi.h>
++#include <IndustryStandard/DebugPort2Table.h>
++#include <Library/AcpiLib.h>
++#include <Library/PcdLib.h>
++#include "Hi1620Platform.h"
++
++#define NUMBER_DEBUG_DEVICE_INFO    1
++#define NUMBER_OF_GENERIC_ADDRESS   1
++#define NAMESPACE_STRING_SIZE       8
++#define UART_LENGTH                 0x1000
++
++#pragma pack(1)
++
++typedef struct {
++  EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT DdiHeader;
++  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE Address[NUMBER_OF_GENERIC_ADDRESS];
++  UINT32 AddressSize[NUMBER_OF_GENERIC_ADDRESS];
++  CHAR8  NamespaceString[NAMESPACE_STRING_SIZE];
++} EFI_ACPI_DBG2_DDI_STRUCT;
++
++typedef struct {
++  EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Desc;
++  EFI_ACPI_DBG2_DDI_STRUCT Ddi[NUMBER_DEBUG_DEVICE_INFO];
++} EFI_ACPI_DEBUG_PORT_2_TABLE;
++
++#pragma pack()
++
++EFI_ACPI_DEBUG_PORT_2_TABLE Dbg2 = {
++  {
++    ARM_ACPI_HEADER(
++      EFI_ACPI_6_1_DEBUG_PORT_2_TABLE_SIGNATURE,
++      EFI_ACPI_DEBUG_PORT_2_TABLE,
++      EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION
++      ),
++    OFFSET_OF(EFI_ACPI_DEBUG_PORT_2_TABLE, Ddi),
++    NUMBER_DEBUG_DEVICE_INFO
++  },
++  {
++    {
++      {
++        EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,
++        sizeof(EFI_ACPI_DBG2_DDI_STRUCT),
++        NUMBER_OF_GENERIC_ADDRESS,
++        NAMESPACE_STRING_SIZE,
++        OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, NamespaceString),
++        0,  //OemDataLength
++        0,  //OemDataOffset
++        EFI_ACPI_DBG2_PORT_TYPE_SERIAL,
++         EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART,
++        {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE},
++        OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, Address),
++        OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, AddressSize),
++      },
++      {
++        {
++          EFI_ACPI_6_1_SYSTEM_MEMORY,
++          32,
++          0,
++          EFI_ACPI_6_1_BYTE,
++          FixedPcdGet64 (PcdSerialDbgRegisterBase)
++        }
++      },
++      {
++        UART_LENGTH
++      },
++      "COM1"
++    }
++  }
++};
++
++//
++// Reference the table being generated to prevent the optimizer from removing the
++// data structure from the executable
++//
++VOID* CONST ReferenceAcpiTable = &Dbg2;
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl
+new file mode 100644
+index 0000000000..33b5d5250b
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl
+@@ -0,0 +1,1989 @@
++/*
++ * Intel ACPI Component Architecture
++ * iASL Compiler/Disassembler version 20151124-64
++ * Copyright (c) 2000 - 2015 Intel Corporation
++ *
++ * Template for [IORT] ACPI Table (static data table)
++ * Format: [ByteLength]  FieldName : HexFieldValue
++ */
++[0004]                          Signature : "IORT"    [IO Remapping Table]
++[0004]                       Table Length : 01c8
++[0001]                           Revision : 00
++[0001]                           Checksum : BC
++[0006]                             Oem ID : "HISI  "            // ?
++[0008]                       Oem Table ID : "HIP08   "          // ?
++[0004]                       Oem Revision : 00000000            // ?
++[0004]                    Asl Compiler ID : "INTL"
++[0004]              Asl Compiler Revision : 20150410
++
++[0004]                         Node Count : 00000005           // ITS, SMMU and RC
++[0004]                        Node Offset : 00000034           // ?
++[0004]                           Reserved : 00000000
++[0004]                   Optional Padding : 00 00 00 00
++
++/* 0x34 ITS, for PCIe */
++/* Here we use the P680/Hi1620 ACPI table which includes MADT table to help to debuge */
++[0001]                               Type : 00
++[0002]                             Length : 0018
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000000           // ?
++[0004]                     Mapping Offset : 00000000           // ?
++
++[0004]                           ItsCount : 00000001           // ?
++[0004]                        Identifiers : 00000000           // how to refer to MADT ?
++
++/* 0x4c SMMU for PCIe host bridge 0 and 1 */
++[0001]                               Type : 04
++[0002]                             Length : 0080
++[0001]                           Revision : 01
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000003
++[0004]                     Mapping Offset : 00000044
++
++[0008]                       Base Address : 148000000
++[0004]              Flags (decoded below) : 00000009
++                          COHACC Override : 1
++                            HTTU Override : 0
++                   Proximity Domain Valid : 1
++[0004]                           Reserved : 00000000
++[0008]                      VATOS Address : 0
++[0004]                              Model : 00000000
++[0004]                    Event Interrupt : 00000000
++[0004]                      PRI Interrupt : 00000000
++[0004]                     GERR Interrupt : 00000000
++[0004]                     Sync Interrupt : 00000000
++[0001]                   Proximity Domain : 01
++[0001]                           Reserved : 00
++[0002]                           Reserved : 0000
++[0004]             DeviceID mapping index : 00000002
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00004000
++[0004]                        Output Base : 00000000
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++[0004]                         Input base : 00007b00
++[0004]                           ID Count : 00000100
++[0004]                        Output Base : 00007b00
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++[0004]                         Input base : 00000000   //single mapping will ignore input base
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F01
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* 0xCC SMMU for PCIe host bridge 4 */
++[0001]                               Type : 04
++[0002]                             Length : 006C
++[0001]                           Revision : 01
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000044
++
++[0008]                       Base Address : 100000000
++[0004]              Flags (decoded below) : 00000009
++                          COHACC Override : 1
++                            HTTU Override : 0
++                   Proximity Domain Valid : 1
++[0004]                           Reserved : 00000000
++[0008]                      VATOS Address : 0
++[0004]                              Model : 00000000
++[0004]                    Event Interrupt : 00000000
++[0004]                      PRI Interrupt : 00000000
++[0004]                     GERR Interrupt : 00000000
++[0004]                     Sync Interrupt : 00000000
++[0001]                   Proximity Domain : 01
++[0001]                           Reserved : 00
++[0002]                           Reserved : 0000
++[0004]             DeviceID mapping index : 0001
++
++[0004]                         Input base : 00007c00
++[0004]                           ID Count : 00000200
++[0004]                        Output Base : 00007c00
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++[0004]                         Input base : 00000000   //single mapping will ignore input base
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F03
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* 0x138 */
++/* SMMU for PCIe host bridge 5 */
++[0001]                               Type : 04
++[0002]                             Length : 006C
++[0001]                           Revision : 01
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000044
++
++[0008]                       Base Address : 140000000
++[0004]              Flags (decoded below) : 00000009
++                          COHACC Override : 1
++                            HTTU Override : 0
++                   Proximity Domain Valid : 1
++[0004]                           Reserved : 00000000
++[0008]                      VATOS Address : 0
++[0004]                              Model : 00000000
++[0004]                    Event Interrupt : 00000000
++[0004]                      PRI Interrupt : 00000000
++[0004]                     GERR Interrupt : 00000000
++[0004]                     Sync Interrupt : 00000000
++[0001]                   Proximity Domain : 01
++[0001]                           Reserved : 00
++[0002]                           Reserved : 0000
++[0004]             DeviceID mapping index : 00000001
++
++[0004]                         Input base : 00007400
++[0004]                           ID Count : 00000300
++[0004]                        Output Base : 00007400
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++[0004]                         Input base : 00000000   //single mapping will ignore input base
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F04
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++// Here for Chip1 SMMU settings
++/* 0x1A4 SMMU for PCIe host bridge 6 and 7 */
++[0001]                               Type : 04
++[0002]                             Length : 0080
++[0001]                           Revision : 01
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000003
++[0004]                     Mapping Offset : 00000044
++
++[0008]                       Base Address : 400148000000
++[0004]              Flags (decoded below) : 00000009
++                          COHACC Override : 1
++                            HTTU Override : 0
++                   Proximity Domain Valid : 1
++[0004]                           Reserved : 00000000
++[0008]                      VATOS Address : 0
++[0004]                              Model : 00000000
++[0004]                    Event Interrupt : 00000000
++[0004]                      PRI Interrupt : 00000000
++[0004]                     GERR Interrupt : 00000000
++[0004]                     Sync Interrupt : 00000000
++[0001]                   Proximity Domain : 03
++[0001]                           Reserved : 00
++[0002]                           Reserved : 0000
++[0004]             DeviceID mapping index : 00000002
++
++[0004]                         Input base : 00008000
++[0004]                           ID Count : 00002000
++[0004]                        Output Base : 00008000
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++[0004]                         Input base : 0000bb00
++[0004]                           ID Count : 00000100
++[0004]                        Output Base : 0000bb00
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++[0004]                         Input base : 00000000   //single mapping will ignore input base
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF01
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* 0x224 SMMU for PCIe host bridge 10 */
++[0001]                               Type : 04
++[0002]                             Length : 006C
++[0001]                           Revision : 01
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000044
++
++[0008]                       Base Address : 400100000000
++[0004]              Flags (decoded below) : 00000009
++                          COHACC Override : 1
++                            HTTU Override : 0
++                   Proximity Domain Valid : 1
++[0004]                           Reserved : 00000000
++[0008]                      VATOS Address : 0
++[0004]                              Model : 00000000
++[0004]                    Event Interrupt : 00000000
++[0004]                      PRI Interrupt : 00000000
++[0004]                     GERR Interrupt : 00000000
++[0004]                     Sync Interrupt : 00000000
++[0001]                   Proximity Domain : 03
++[0001]                           Reserved : 00
++[0002]                           Reserved : 0000
++[0004]             DeviceID mapping index : 0001
++
++[0004]                         Input base : 0000BC00
++[0004]                           ID Count : 00000200
++[0004]                        Output Base : 0000BC00
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++[0004]                         Input base : 00000000   //single mapping will ignore input base
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF03
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* 0x290*/
++/* SMMU for PCIe host bridge 11 */
++[0001]                               Type : 04
++[0002]                             Length : 006C
++[0001]                           Revision : 01
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000044
++
++[0008]                       Base Address : 400140000000
++[0004]              Flags (decoded below) : 00000009
++                          COHACC Override : 1
++                            HTTU Override : 0
++                   Proximity Domain Valid : 1
++[0004]                           Reserved : 00000000
++[0008]                      VATOS Address : 0
++[0004]                              Model : 00000000
++[0004]                    Event Interrupt : 00000000
++[0004]                      PRI Interrupt : 00000000
++[0004]                     GERR Interrupt : 00000000
++[0004]                     Sync Interrupt : 00000000
++[0001]                   Proximity Domain : 03
++[0001]                           Reserved : 00
++[0002]                           Reserved : 0000
++[0004]             DeviceID mapping index : 00000001
++
++[0004]                         Input base : 0000B400
++[0004]                           ID Count : 00000300
++[0004]                        Output Base : 0000B400
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++[0004]                         Input base : 00000000   //single mapping will ignore input base
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF04
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/*0x2FC RC 0 */
++[0001]                               Type : 02
++[0002]                             Length : 00A0
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 0000000C
++[0004]                     Mapping Offset : 00000028
++
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000001
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0004]                      ATS Attribute : 00000000
++[0004]                 PCI Segment Number : 00000000           // should match with above MCFG
++
++/* BDF of pcie host 0 -> stream ID of pcie 0/1 SMMU */
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00004000          // the number of IDs in range
++[0004]                        Output Base : 00000000
++[0004]                   Output Reference : 0000004c
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++/* BDF of pcie host 1 -> stream ID of pcie 0/1 SMMU */
++[0004]                         Input base : 00007b00
++[0004]                           ID Count : 00000100          // the number of IDs in range
++[0004]                        Output Base : 00007b00
++[0004]                   Output Reference : 0000004c
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++/* host2 and host3 should no open smmu for chips smmu bug *
++/* BDF of pcie host 2 -> stream ID of pcie 0/1 ITS */
++[0004]                         Input base : 00007a00
++[0004]                           ID Count : 00000100          // the number of IDs in range
++[0004]                        Output Base : 00007a00
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++/* BDF of pcie host 3 -> stream ID of pcie 0/1 ITS */
++[0004]                         Input base : 00007800
++[0004]                           ID Count : 00000200          // the number of IDs in range
++[0004]                        Output Base : 00007800
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++/* BDF of pcie host 4 -> stream ID of pcie 4 SMMU */
++[0004]                         Input base : 00007c00
++[0004]                           ID Count : 00000200          // the number of IDs in range
++[0004]                        Output Base : 00007c00
++[0004]                   Output Reference : 000000cc
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++/* BDF of pcie host 5 -> stream ID of pcie 5 SMMU */
++[0004]                         Input base : 00007400
++[0004]                           ID Count : 00000300          // the number of IDs in range
++[0004]                        Output Base : 00007400
++[0004]                   Output Reference : 00000138
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++/* BDF of pcie host 6 -> stream ID of pcie 6/7 SMMU */
++[0004]                         Input base : 00008000
++[0004]                           ID Count : 00002000          // the number of IDs in range
++[0004]                        Output Base : 00008000
++[0004]                   Output Reference : 000001A4
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++/* BDF of pcie host 7 -> stream ID of pcie 6/7 SMMU */
++[0004]                         Input base : 0000BB00
++[0004]                           ID Count : 00000100          // the number of IDs in range
++[0004]                        Output Base : 0000BB00
++[0004]                   Output Reference : 000001A4
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++/* host8 and host9 should no open smmu for chips smmu bug *
++/* BDF of pcie host 8 -> stream ID of pcie ITS */
++[0004]                         Input base : 0000BA00
++[0004]                           ID Count : 00000100          // the number of IDs in range
++[0004]                        Output Base : 0000BA00
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++/* BDF of pcie host 9 -> stream ID of pcie 0/1 ITS */
++[0004]                         Input base : 0000B800
++[0004]                           ID Count : 00000200          // the number of IDs in range
++[0004]                        Output Base : 0000B800
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++/* BDF of pcie host 10 -> stream ID of pcie 10 SMMU */
++[0004]                         Input base : 0000BC00
++[0004]                           ID Count : 00000200          // the number of IDs in range
++[0004]                        Output Base : 0000BC00
++[0004]                   Output Reference : 00000224
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++/* BDF of pcie host 11 -> stream ID of pcie 11 SMMU */
++[0004]                         Input base : 0000B400
++[0004]                           ID Count : 00000300          // the number of IDs in range
++[0004]                        Output Base : 0000B400
++[0004]                   Output Reference : 00000290
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-L3T0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB30"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FD1 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-L3T1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB31"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FD2 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-L3T2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB32"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FD3 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-L3T3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB33"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FD4 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-L3T4, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB34"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FD5 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-L3T5, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB35"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FD6 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-DDRC0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB38"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FDD // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-DDRC1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB39"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FDE // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-DDRC2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB3A"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FDF // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-DDRC3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB3B"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FC7 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-HHA0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB3C"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FC8 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-HHA1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB3D"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FC9 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-L3T0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB10"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F51 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-L3T1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB11"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F52 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-L3T2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB12"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F53 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-L3T3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB13"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F54 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-L3T4, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB14"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F55 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-L3T5, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB15"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F56 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-DDRC0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB18"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F5D // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-DDRC1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB19"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F5E // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-DDRC2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB1A"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F5F // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-DDRC3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB1B"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F47 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-HHA0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB1C"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F48 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-HHA1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB1D"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F49 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-L3T0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB70"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFD1 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-L3T1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB71"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFD2 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-L3T2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB72"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFD3 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-L3T3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB73"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFD4 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-L3T4, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB74"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFD5 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-L3T5, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB75"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFD6 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-DDRC0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB78"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFDD // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-DDRC1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB79"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFDE // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-DDRC2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB7A"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFDF // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-DDRC3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB7B"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFC7 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-HHA0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB7C"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFC8 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-HHA1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB7D"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFC9 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-L3T0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB50"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF51 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-L3T1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB51"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF52 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-L3T2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB52"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF53 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-L3T3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB53"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF54 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-L3T4, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB54"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF55 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-L3T5, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB55"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF56 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-DDRC0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB58"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF5D // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-DDRC1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB59"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF5E // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-DDRC2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB5A"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF5F // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-DDRC3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB5B"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF47 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-HHA0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB5C"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF48 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-HHA1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB5D"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF49 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++
++[320h 0800   1]                         Type : 01
++[321h 0801   2]                       Length : 0054
++[323h 0803   1]                     Revision : 00
++[324h 0804   4]                     Reserved : 00000000
++[328h 0808   4]                Mapping Count : 00000001
++[32Ch 0812   4]               Mapping Offset : 00000040
++
++[330h 0816   4]                   Node Flags : 00000000
++[334h 0820   8]            Memory Properties : [IORT Memory Access Properties]
++[334h 0820   4]              Cache Coherency : 00000000
++[338h 0824   1]        Hints (decoded below) : 00
++                                   Transient : 0
++                              Write Allocate : 0
++                               Read Allocate : 0
++                                    Override : 0
++[339h 0825   2]                     Reserved : 0000
++[33Bh 0827   1] Memory Flags (decoded below) : 00
++                                   Coherency : 0
++                            Device Attribute : 0
++[33Ch 0828   1]            Memory Size Limit : 00
++[33Dh 0829  11]                  Device Name : "\_SB_.SEC0"
++[348h 0840  24]                      Padding : \
++    00 00 00 00 00 00 00 00 01 00 00 00 80 00 04 00 \
++    4C 00 00 00 01 00 00 00
++
++[34Ch 0844   4]                   Input base : 00000000
++[350h 0848   4]                     ID Count : 00000001
++[354h 0852   4]                  Output Base : 00000100
++[358h 0856   4]             Output Reference : 00000100
++[35Ch 0860   4]        Flags (decoded below) : 00000001
++                              Single Mapping : 1
++/* RDE device report++.*/
++[320h 0800   1]                         Type : 01
++[321h 0801   2]                       Length : 0054
++[323h 0803   1]                     Revision : 00
++[324h 0804   4]                     Reserved : 00000000
++[328h 0808   4]                Mapping Count : 00000001
++[32Ch 0812   4]               Mapping Offset : 00000040
++
++[330h 0816   4]                   Node Flags : 00000000
++[334h 0820   8]            Memory Properties : [IORT Memory Access Properties]
++[334h 0820   4]              Cache Coherency : 00000000
++[338h 0824   1]        Hints (decoded below) : 00
++                                   Transient : 0
++                              Write Allocate : 0
++                               Read Allocate : 0
++                                    Override : 0
++[339h 0825   2]                     Reserved : 0000
++[33Bh 0827   1] Memory Flags (decoded below) : 00
++                                   Coherency : 0
++                            Device Attribute : 0
++[33Ch 0828   1]            Memory Size Limit : 00
++[33Dh 0829  11]                  Device Name : "\_SB_.RDE0"
++[348h 0840  24]                      Padding : \
++    00 00 00 00 00 00 00 00 01 00 00 00 80 00 04 00 \
++    4C 00 00 00 01 00 00 00
++
++[34Ch 0844   4]                   Input base : 00000000
++[350h 0848   4]                     ID Count : 00000001
++[354h 0852   4]                  Output Base : 00007f13
++[358h 0856   4]             Output Reference : 00000034
++[35Ch 0860   4]        Flags (decoded below) : 00000001
++                              Single Mapping : 1
++
++/* mbi-gen for MCTP, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MBI4"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F18 // MCTP device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl
+new file mode 100644
+index 0000000000..63d11b83eb
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl
+@@ -0,0 +1,1736 @@
++/*
++ * Intel ACPI Component Architecture
++ * iASL Compiler/Disassembler version 20151124-64
++ * Copyright (c) 2000 - 2015 Intel Corporation
++ *
++ * Template for [IORT] ACPI Table (static data table)
++ * Format: [ByteLength]  FieldName : HexFieldValue
++ */
++[0004]                          Signature : "IORT"    [IO Remapping Table]
++[0004]                       Table Length : 01c8
++[0001]                           Revision : 00
++[0001]                           Checksum : BC
++[0006]                             Oem ID : "HISI  "            // ?
++[0008]                       Oem Table ID : "HIP08   "          // ?
++[0004]                       Oem Revision : 00000000            // ?
++[0004]                    Asl Compiler ID : "INTL"
++[0004]              Asl Compiler Revision : 20150410
++
++[0004]                         Node Count : 00000005           // ITS, SMMU and RC
++[0004]                        Node Offset : 00000034           // ?
++[0004]                           Reserved : 00000000
++[0004]                   Optional Padding : 00 00 00 00
++
++/* 0x34 ITS, for PCIe */
++/* Here we use the P680/Hi1620 ACPI table which includes MADT table to help to debuge */
++[0001]                               Type : 00
++[0002]                             Length : 0018
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000000           // ?
++[0004]                     Mapping Offset : 00000000           // ?
++
++[0004]                           ItsCount : 00000001           // ?
++[0004]                        Identifiers : 00000000           // how to refer to MADT ?
++
++/*0x4c RC 0 */
++[0001]                               Type : 02
++[0002]                             Length : 00A0
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 0000000C
++[0004]                     Mapping Offset : 00000028
++
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000001
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0004]                      ATS Attribute : 00000000
++[0004]                 PCI Segment Number : 00000000           // should match with above MCFG
++
++/* BDF of pcie host 0 -> stream ID of pcie 0/1 SMMU */
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00004000          // the number of IDs in range
++[0004]                        Output Base : 00000000
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 0
++
++/* BDF of pcie host 1 -> stream ID of pcie 0/1 SMMU */
++[0004]                         Input base : 00007b00
++[0004]                           ID Count : 00000100          // the number of IDs in range
++[0004]                        Output Base : 00007b00
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 0
++
++/* BDF of pcie host 2 -> stream ID of pcie 0/1 ITS */
++[0004]                         Input base : 00007a00
++[0004]                           ID Count : 00000100          // the number of IDs in range
++[0004]                        Output Base : 00007a00
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 0
++
++/* BDF of pcie host 3 -> stream ID of pcie 0/1 ITS */
++[0004]                         Input base : 00007800
++[0004]                           ID Count : 00000200          // the number of IDs in range
++[0004]                        Output Base : 00007800
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 0
++
++/* BDF of pcie host 4 -> stream ID of pcie 4 SMMU */
++[0004]                         Input base : 00007c00
++[0004]                           ID Count : 00000200          // the number of IDs in range
++[0004]                        Output Base : 00007c00
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 0
++
++/* BDF of pcie host 5 -> stream ID of pcie 5 SMMU */
++[0004]                         Input base : 00007400
++[0004]                           ID Count : 00000300          // the number of IDs in range
++[0004]                        Output Base : 00007400
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 0
++
++/* BDF of pcie host 6 -> stream ID of pcie 6/7 SMMU */
++[0004]                         Input base : 00008000
++[0004]                           ID Count : 00002000          // the number of IDs in range
++[0004]                        Output Base : 00008000
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 0
++
++/* BDF of pcie host 7 -> stream ID of pcie 6/7 SMMU */
++[0004]                         Input base : 0000BB00
++[0004]                           ID Count : 00000100          // the number of IDs in range
++[0004]                        Output Base : 0000BB00
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 0
++
++/* BDF of pcie host 8 -> stream ID of pcie ITS */
++[0004]                         Input base : 0000BA00
++[0004]                           ID Count : 00000100          // the number of IDs in range
++[0004]                        Output Base : 0000BA00
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 0
++
++/* BDF of pcie host 9 -> stream ID of pcie 0/1 ITS */
++[0004]                         Input base : 0000B800
++[0004]                           ID Count : 00000200          // the number of IDs in range
++[0004]                        Output Base : 0000B800
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 0
++
++/* BDF of pcie host 10 -> stream ID of pcie 10 SMMU */
++[0004]                         Input base : 0000BC00
++[0004]                           ID Count : 00000200          // the number of IDs in range
++[0004]                        Output Base : 0000BC00
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 0
++
++/* BDF of pcie host 11 -> stream ID of pcie 11 SMMU */
++[0004]                         Input base : 0000B400
++[0004]                           ID Count : 00000300          // the number of IDs in range
++[0004]                        Output Base : 0000B400
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 0
++
++/* mbi-gen for S0-TB-L3T0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB30"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FD1 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-L3T1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB31"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FD2 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-L3T2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB32"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FD3 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-L3T3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB33"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FD4 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-L3T4, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB34"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FD5 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-L3T5, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB35"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FD6 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-DDRC0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB38"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FDD // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-DDRC1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB39"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FDE // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-DDRC2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB3A"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FDF // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-DDRC3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB3B"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FC7 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-HHA0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB3C"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FC8 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-HHA1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB3D"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FC9 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-L3T0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB10"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F51 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-L3T1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB11"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F52 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-L3T2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB12"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F53 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-L3T3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB13"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F54 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-L3T4, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB14"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F55 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-L3T5, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB15"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F56 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-DDRC0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB18"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F5D // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-DDRC1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB19"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F5E // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-DDRC2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB1A"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F5F // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-DDRC3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB1B"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F47 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-HHA0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB1C"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F48 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-HHA1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB1D"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F49 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-L3T0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB70"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFD1 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-L3T1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB71"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFD2 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-L3T2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB72"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFD3 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-L3T3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB73"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFD4 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-L3T4, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB74"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFD5 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-L3T5, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB75"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFD6 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-DDRC0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB78"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFDD // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-DDRC1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB79"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFDE // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-DDRC2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB7A"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFDF // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-DDRC3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB7B"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFC7 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-HHA0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB7C"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFC8 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-HHA1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB7D"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFC9 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-L3T0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB50"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF51 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-L3T1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB51"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF52 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-L3T2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB52"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF53 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-L3T3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB53"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF54 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-L3T4, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB54"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF55 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-L3T5, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB55"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF56 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-DDRC0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB58"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF5D // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-DDRC1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB59"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF5E // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-DDRC2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB5A"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF5F // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-DDRC3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB5B"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF47 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-HHA0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB5C"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF48 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-HHA1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB5D"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF49 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++
++[320h 0800   1]                         Type : 01
++[321h 0801   2]                       Length : 0054
++[323h 0803   1]                     Revision : 00
++[324h 0804   4]                     Reserved : 00000000
++[328h 0808   4]                Mapping Count : 00000001
++[32Ch 0812   4]               Mapping Offset : 00000040
++
++[330h 0816   4]                   Node Flags : 00000000
++[334h 0820   8]            Memory Properties : [IORT Memory Access Properties]
++[334h 0820   4]              Cache Coherency : 00000000
++[338h 0824   1]        Hints (decoded below) : 00
++                                   Transient : 0
++                              Write Allocate : 0
++                               Read Allocate : 0
++                                    Override : 0
++[339h 0825   2]                     Reserved : 0000
++[33Bh 0827   1] Memory Flags (decoded below) : 00
++                                   Coherency : 0
++                            Device Attribute : 0
++[33Ch 0828   1]            Memory Size L