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[81.169.180.215]) by mx.google.com with ESMTP id b11-v6si6372813edd.211.2018.08.21.10.30.35; Tue, 21 Aug 2018 10:30:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=dF7sIobK; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id D9AC6C21E1A; Tue, 21 Aug 2018 17:30:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 343DFC21E2B; Tue, 21 Aug 2018 17:30:13 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 17D87C21E13; Tue, 21 Aug 2018 17:30:01 +0000 (UTC) Received: from mail-pf1-f196.google.com (mail-pf1-f196.google.com [209.85.210.196]) by lists.denx.de (Postfix) with ESMTPS id 2CA6DC21E42 for ; Tue, 21 Aug 2018 17:29:57 +0000 (UTC) Received: by mail-pf1-f196.google.com with SMTP id e13-v6so8817363pff.7 for ; Tue, 21 Aug 2018 10:29:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NJ26gG0pI+NU7iUcPOUL33gXedBc82ATjhlG6bT1npQ=; b=dF7sIobK3t3BXXFT0LNrPPxY9K6iLIW5XWwTwdmTE7Ct5bW9esaueRUJEvlBHFtwD7 4IaSqFV+JrrTgbEEZVO+1cDyY1s0gim6ukMCjsRecTZzVKGcRdDqUmj31+/N2hy58Ifq cxz/eQwMFg6g6kO749Q5CVRR5CR5R7Evo8oS4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NJ26gG0pI+NU7iUcPOUL33gXedBc82ATjhlG6bT1npQ=; b=F/Gp+5gqyLzg0mPI8P4cfK55vtc5gr+LCZ2+OOD2Z0/Z4s+K6OsImp/cVXiDd+QgZ0 +TNXRcf1zwFPp5f6If1Tmh0mVVRSo4Ei8DwmpdA7NZ4cYFPyRmfYJX9hyIPYQ74IXfEi KUXr+gWPgTjd+S6jtyloA5Pnk+Hw7PO1OBdzPnDUZmJGi16S+Fwcqu0w2LqpUaafHXR1 /Hpjagum7Rx9WsBTg+P9fPeHd9ao88dk16vgg+q89JUdwFpv4R4bky/Up5VQDhQivYyY v2IgfX1Fo2rcVWJ+Vxro7at+AOJU/ALil2ktdn/6C9x3dud1giVlHqV/5tB7A8Q5w9yj RLSg== X-Gm-Message-State: AOUpUlGFpNfsSbm6PI6pqqZa32p2lRoNbEB6dWoCwAByrLwChWhtu3qy 4PXxnXWTzqfqxaCUfZ1RUrPO X-Received: by 2002:a62:4255:: with SMTP id p82-v6mr54250830pfa.238.1534872595687; Tue, 21 Aug 2018 10:29:55 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:6287:cd45:ccd1:6e1b:c3e9:6a94]) by smtp.gmail.com with ESMTPSA id v19-v6sm31021965pgn.94.2018.08.21.10.29.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Aug 2018 10:29:55 -0700 (PDT) From: Manivannan Sadhasivam To: sjg@chromium.org, philipp.tomsich@theobroma-systems.com Date: Tue, 21 Aug 2018 22:58:16 +0530 Message-Id: <20180821172817.26463-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180821172817.26463-1-manivannan.sadhasivam@linaro.org> References: <20180821172817.26463-1-manivannan.sadhasivam@linaro.org> Cc: tom@vamrs.com, amit.kucheria@linaro.org, dev@vamrs.com, u-boot@lists.denx.de, Manivannan Sadhasivam , stephen@vamrs.com Subject: [U-Boot] [PATCH v2 1/2] arm: dts: Add Rock960 devicetree support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add devicetree support for Vamrs Limited Rock960. This board is one of the 96Boards Consumer Edition platform. Signed-off-by: Manivannan Sadhasivam --- Changes in v2: * Added missing DTB entry in arch/arm/dts/Makefile arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-rock960.dts | 348 ++++++++++++++++++++++++++++++++ 2 files changed, 349 insertions(+) create mode 100644 arch/arm/dts/rk3399-rock960.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ebfa2272627..9b891826b73 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3399-puma-ddr1333.dtb \ rk3399-puma-ddr1600.dtb \ rk3399-puma-ddr1866.dtb \ + rk3399-rock960.dtb \ rv1108-evb.dtb dtb-$(CONFIG_ARCH_MESON) += \ meson-gxbb-nanopi-k2.dtb \ diff --git a/arch/arm/dts/rk3399-rock960.dts b/arch/arm/dts/rk3399-rock960.dts new file mode 100644 index 00000000000..8662548e642 --- /dev/null +++ b/arch/arm/dts/rk3399-rock960.dts @@ -0,0 +1,348 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Manivannan Sadhasivam + */ + +/dts-v1/; +#include +#include +#include "rk3399.dtsi" +#include "rk3399-sdram-lpddr3-4GB-1600.dtsi" + +/ { + model = "Vamrs Limited Rock960 96Board"; + compatible = "rockchip,rk3399-rock960", "rockchip,rk3399"; + + chosen { + stdout-path = &uart2; + u-boot,spl-boot-order = \ + &sdhci, &sdmmc; + }; + + vccsys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vccsys"; + regulator-boot-on; + regulator-always-on; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_host0: vcc5v0-host0-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host0"; + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + }; + + vcc5v0_host1: vcc5v0-host1-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host1"; + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + }; + + vcc5v0_host2: vcc5v0-host2-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host2"; + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + }; + + vbus_typec: vbus-typec-regulator { + compatible = "regulator-fixed"; + regulator-name = "vbus_typec"; + gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-init-microvolt = <900000>; + }; +}; + +&emmc_phy { + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +&sdmmc { + u-boot,dm-pre-reloc; + bus-width = <4>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <100>; + u-boot,dm-pre-reloc; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "rtc_clko_soc", "rtc_clko_wifi"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc3v3_sys>; + vcc13-supply = <&vcc5v0_sys>; + vcc14-supply = <&vcc5v0_sys>; + vddio-supply = <&vcc_1v8>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_hdmi: LDO_REG2 { + regulator-name = "vcca1v8_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8: LDO_REG3 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca1v8_mipi: LDO_REG5 { + regulator-name = "vcca1v8_mipi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca0v9_hdmi: LDO_REG7 { + regulator-name = "vcca0v9_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <0>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 21 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +};