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[209.132.180.67]) by mx.google.com with ESMTP id c5-v6si6263210pgk.327.2018.08.24.02.21.26; Fri, 24 Aug 2018 02:21:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eaSFFO0r; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726770AbeHXMzL (ORCPT + 5 others); Fri, 24 Aug 2018 08:55:11 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:40875 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726407AbeHXMzK (ORCPT ); Fri, 24 Aug 2018 08:55:10 -0400 Received: by mail-pl1-f195.google.com with SMTP id s17-v6so848838plp.7 for ; Fri, 24 Aug 2018 02:21:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VLyWTs4wkn6Lk1EZkxQq2kCYTxna3ww596giwJ8qsjk=; b=eaSFFO0rjDeVblmfXrJh6DRbfNO94vDFPn62rsymhsBfMK7eMwJ4Mtzd7Qut8sn/c/ gtwc6jmiRkAe3iYjMptFUqsw7KpmBZOR31Fc8GBX4AVxuAYUJjKUF85eHtb3yD/io+4V H9D+YMhP+kY4utkm8/zLIc5B3CYzdl3VXlfMA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VLyWTs4wkn6Lk1EZkxQq2kCYTxna3ww596giwJ8qsjk=; b=WoH4s3cuzuXZWUdnncP5hiGg2+o20B2aSW18A5x16aV3A/t6ek3K3nb5g9SXqbk/S2 Qjr1GsXDzZbISA6+QbT546VckvSdkz1uITaJ5bp82l2dJetvuhtfavY0OUo6mqDBbz0+ GxsM2dIuFjU2NztbVU5+Usd1BHPxi8ZW0sYt2bzB7bowxxbFLmiy8HWY18Tw91dkn6gn L1GGdKP7PgRPOJgm3yfMhBMBy33hqPyNOLFEx8FogBNNWq3aON9xKmYvI125ofpctyUn W90F1eCMx9enIUeCwV2DWwPNEg4GdpZPB4JpUW4hWb2NDL4zbfiDlJ4MbwoKEGlLvhnn cp+w== X-Gm-Message-State: APzg51AEd1hMouuL8TV2Uro8RFsjy18SIbm0je5mWUMOFnxnXsXB7wdf f5FIR7+KZ8y30o+pIo6d+6kA7w== X-Received: by 2002:a17:902:4324:: with SMTP id i33-v6mr865592pld.43.1535102485071; Fri, 24 Aug 2018 02:21:25 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id g6-v6sm9520314pfb.11.2018.08.24.02.21.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 24 Aug 2018 02:21:24 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V6 3/9] mmc: sdhci: Change SDMA address register for v4 mode Date: Fri, 24 Aug 2018 17:20:22 +0800 Message-Id: <1535102428-20332-4-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535102428-20332-1-git-send-email-zhang.chunyan@linaro.org> References: <1535102428-20332-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org According to the SD host controller specification version 4.10, when Host Version 4 is enabled, SDMA uses ADMA System Address register (05Fh-058h) instead of using SDMA System Address register to support both 32-bit and 64-bit addressing. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index a50842c..df283ca 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -727,7 +727,7 @@ static void sdhci_adma_table_post(struct sdhci_host *host, } } -static u32 sdhci_sdma_address(struct sdhci_host *host) +static dma_addr_t sdhci_sdma_address(struct sdhci_host *host) { if (host->bounce_buffer) return host->bounce_addr; @@ -735,6 +735,17 @@ static u32 sdhci_sdma_address(struct sdhci_host *host) return sg_dma_address(host->data->sg); } +static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr) +{ + if (host->v4_mode) { + sdhci_writel(host, addr, SDHCI_ADMA_ADDRESS); + if (host->flags & SDHCI_USE_64_BIT_DMA) + sdhci_writel(host, (u64)addr >> 32, SDHCI_ADMA_ADDRESS_HI); + } else { + sdhci_writel(host, addr, SDHCI_DMA_ADDRESS); + } +} + static unsigned int sdhci_target_timeout(struct sdhci_host *host, struct mmc_command *cmd, struct mmc_data *data) @@ -994,8 +1005,7 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) SDHCI_ADMA_ADDRESS_HI); } else { WARN_ON(sg_cnt != 1); - sdhci_writel(host, sdhci_sdma_address(host), - SDHCI_DMA_ADDRESS); + sdhci_set_sdma_addr(host, sdhci_sdma_address(host)); } } @@ -2823,7 +2833,7 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) * some controllers are faulty, don't trust them. */ if (intmask & SDHCI_INT_DMA_END) { - u32 dmastart, dmanow; + dma_addr_t dmastart, dmanow; dmastart = sdhci_sdma_address(host); dmanow = dmastart + host->data->bytes_xfered; @@ -2831,12 +2841,12 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) * Force update to the next DMA block boundary. */ dmanow = (dmanow & - ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + + ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + SDHCI_DEFAULT_BOUNDARY_SIZE; host->data->bytes_xfered = dmanow - dmastart; - DBG("DMA base 0x%08x, transferred 0x%06x bytes, next 0x%08x\n", - dmastart, host->data->bytes_xfered, dmanow); - sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); + DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n", + &dmastart, host->data->bytes_xfered, &dmanow); + sdhci_set_sdma_addr(host, dmanow); } if (intmask & SDHCI_INT_DATA_END) { @@ -3583,8 +3593,8 @@ int sdhci_setup_host(struct sdhci_host *host) } } - /* SDMA does not support 64-bit DMA */ - if (host->flags & SDHCI_USE_64_BIT_DMA) + /* SDMA does not support 64-bit DMA if v4 mode not set */ + if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode) host->flags &= ~SDHCI_USE_SDMA; if (host->flags & SDHCI_USE_ADMA) {