diff mbox series

[V7,3/9] mmc: sdhci: Change SDMA address register for v4 mode

Message ID 1535526184-32718-4-git-send-email-zhang.chunyan@linaro.org
State Accepted
Commit 917a0c52d6c3b47c071fa868e39689301aa9bc23
Headers show
Series mmc: add support for sdhci 4.0 | expand

Commit Message

Chunyan Zhang Aug. 29, 2018, 7:02 a.m. UTC 
According to the SD host controller specification version 4.10, when
Host Version 4 is enabled, SDMA uses ADMA System Address register
(05Fh-058h) instead of using SDMA System Address register to
support both 32-bit and 64-bit addressing.

Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>

---
 drivers/mmc/host/sdhci.c | 30 ++++++++++++++++++++----------
 1 file changed, 20 insertions(+), 10 deletions(-)

-- 
2.7.4

Comments

Adrian Hunter Aug. 29, 2018, 10:44 a.m. UTC | #1 
On 29/08/18 10:02, Chunyan Zhang wrote:
> According to the SD host controller specification version 4.10, when

> Host Version 4 is enabled, SDMA uses ADMA System Address register

> (05Fh-058h) instead of using SDMA System Address register to

> support both 32-bit and 64-bit addressing.

> 

> Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>


Acked-by: Adrian Hunter <adrian.hunter@intel.com>


> ---

>  drivers/mmc/host/sdhci.c | 30 ++++++++++++++++++++----------

>  1 file changed, 20 insertions(+), 10 deletions(-)

> 

> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c

> index 0c61105..6fb70da 100644

> --- a/drivers/mmc/host/sdhci.c

> +++ b/drivers/mmc/host/sdhci.c

> @@ -727,7 +727,7 @@ static void sdhci_adma_table_post(struct sdhci_host *host,

>  	}

>  }

>  

> -static u32 sdhci_sdma_address(struct sdhci_host *host)

> +static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)

>  {

>  	if (host->bounce_buffer)

>  		return host->bounce_addr;

> @@ -735,6 +735,17 @@ static u32 sdhci_sdma_address(struct sdhci_host *host)

>  		return sg_dma_address(host->data->sg);

>  }

>  

> +static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)

> +{

> +	if (host->v4_mode) {

> +		sdhci_writel(host, addr, SDHCI_ADMA_ADDRESS);

> +		if (host->flags & SDHCI_USE_64_BIT_DMA)

> +			sdhci_writel(host, (u64)addr >> 32, SDHCI_ADMA_ADDRESS_HI);

> +	} else {

> +		sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);

> +	}

> +}

> +

>  static unsigned int sdhci_target_timeout(struct sdhci_host *host,

>  					 struct mmc_command *cmd,

>  					 struct mmc_data *data)

> @@ -994,8 +1005,7 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)

>  					     SDHCI_ADMA_ADDRESS_HI);

>  		} else {

>  			WARN_ON(sg_cnt != 1);

> -			sdhci_writel(host, sdhci_sdma_address(host),

> -				     SDHCI_DMA_ADDRESS);

> +			sdhci_set_sdma_addr(host, sdhci_sdma_address(host));

>  		}

>  	}

>  

> @@ -2830,7 +2840,7 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)

>  		 * some controllers are faulty, don't trust them.

>  		 */

>  		if (intmask & SDHCI_INT_DMA_END) {

> -			u32 dmastart, dmanow;

> +			dma_addr_t dmastart, dmanow;

>  

>  			dmastart = sdhci_sdma_address(host);

>  			dmanow = dmastart + host->data->bytes_xfered;

> @@ -2838,12 +2848,12 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)

>  			 * Force update to the next DMA block boundary.

>  			 */

>  			dmanow = (dmanow &

> -				~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +

> +				~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +

>  				SDHCI_DEFAULT_BOUNDARY_SIZE;

>  			host->data->bytes_xfered = dmanow - dmastart;

> -			DBG("DMA base 0x%08x, transferred 0x%06x bytes, next 0x%08x\n",

> -			    dmastart, host->data->bytes_xfered, dmanow);

> -			sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);

> +			DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n",

> +			    &dmastart, host->data->bytes_xfered, &dmanow);

> +			sdhci_set_sdma_addr(host, dmanow);

>  		}

>  

>  		if (intmask & SDHCI_INT_DATA_END) {

> @@ -3590,8 +3600,8 @@ int sdhci_setup_host(struct sdhci_host *host)

>  		}

>  	}

>  

> -	/* SDMA does not support 64-bit DMA */

> -	if (host->flags & SDHCI_USE_64_BIT_DMA)

> +	/* SDMA does not support 64-bit DMA if v4 mode not set */

> +	if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)

>  		host->flags &= ~SDHCI_USE_SDMA;

>  

>  	if (host->flags & SDHCI_USE_ADMA) {

>
diff mbox series

Patch

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 0c61105..6fb70da 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -727,7 +727,7 @@  static void sdhci_adma_table_post(struct sdhci_host *host,
 	}
 }
 
-static u32 sdhci_sdma_address(struct sdhci_host *host)
+static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
 {
 	if (host->bounce_buffer)
 		return host->bounce_addr;
@@ -735,6 +735,17 @@  static u32 sdhci_sdma_address(struct sdhci_host *host)
 		return sg_dma_address(host->data->sg);
 }
 
+static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
+{
+	if (host->v4_mode) {
+		sdhci_writel(host, addr, SDHCI_ADMA_ADDRESS);
+		if (host->flags & SDHCI_USE_64_BIT_DMA)
+			sdhci_writel(host, (u64)addr >> 32, SDHCI_ADMA_ADDRESS_HI);
+	} else {
+		sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
+	}
+}
+
 static unsigned int sdhci_target_timeout(struct sdhci_host *host,
 					 struct mmc_command *cmd,
 					 struct mmc_data *data)
@@ -994,8 +1005,7 @@  static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 					     SDHCI_ADMA_ADDRESS_HI);
 		} else {
 			WARN_ON(sg_cnt != 1);
-			sdhci_writel(host, sdhci_sdma_address(host),
-				     SDHCI_DMA_ADDRESS);
+			sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
 		}
 	}
 
@@ -2830,7 +2840,7 @@  static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
 		 * some controllers are faulty, don't trust them.
 		 */
 		if (intmask & SDHCI_INT_DMA_END) {
-			u32 dmastart, dmanow;
+			dma_addr_t dmastart, dmanow;
 
 			dmastart = sdhci_sdma_address(host);
 			dmanow = dmastart + host->data->bytes_xfered;
@@ -2838,12 +2848,12 @@  static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
 			 * Force update to the next DMA block boundary.
 			 */
 			dmanow = (dmanow &
-				~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
+				~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
 				SDHCI_DEFAULT_BOUNDARY_SIZE;
 			host->data->bytes_xfered = dmanow - dmastart;
-			DBG("DMA base 0x%08x, transferred 0x%06x bytes, next 0x%08x\n",
-			    dmastart, host->data->bytes_xfered, dmanow);
-			sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
+			DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n",
+			    &dmastart, host->data->bytes_xfered, &dmanow);
+			sdhci_set_sdma_addr(host, dmanow);
 		}
 
 		if (intmask & SDHCI_INT_DATA_END) {
@@ -3590,8 +3600,8 @@  int sdhci_setup_host(struct sdhci_host *host)
 		}
 	}
 
-	/* SDMA does not support 64-bit DMA */
-	if (host->flags & SDHCI_USE_64_BIT_DMA)
+	/* SDMA does not support 64-bit DMA if v4 mode not set */
+	if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
 		host->flags &= ~SDHCI_USE_SDMA;
 
 	if (host->flags & SDHCI_USE_ADMA) {