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Wed, 29 Aug 2018 15:51:02 +0000 (GMT) X-AuditID: cbfec7f2-5e3ff70000001159-e4-5b86c0e6736e Received: from eusync4.samsung.com ( [203.254.199.214]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 33.37.04284.6E0C68B5; Wed, 29 Aug 2018 16:51:02 +0100 (BST) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0PE800FCUC0UPL60@eusync4.samsung.com>; Wed, 29 Aug 2018 16:51:02 +0100 (BST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH 09/10] clk: samsung: exynos4: Use generic helper for handling suspend/resume Date: Wed, 29 Aug 2018 17:50:45 +0200 Message-id: <20180829155046.29359-10-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-reply-to: <20180829155046.29359-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrEIsWRmVeSWpSXmKPExsWy7djPc7rPDrRFG6w5qW2xccZ6VovrX56z Wpw/v4Hd4mPPPVaLGef3MVmsPXKX3aL96UtmB3aPTas62Tz6tqxi9Pi8SS6AOYrLJiU1J7Ms tUjfLoEr4/LrXuaCi0YVM48+ZWlg/KLZxcjJISFgIrGv6TZ7FyMXh5DACkaJZ5vb2SCcz4wS txddYoep6lr7nAUisYxR4vuVS1BVDUwSk5dtZAGpYhMwlOh628UGYosIOEh8/vSaEaSIWeAx o8TWk1+ZQRLCAnES9/p3gNksAqoSs99tAVvBK2An0b94BiPEOnmJ1RsOgNVwAsVfHO9lBRkk IfCVVWLupA9sEEUuEiu//YBqEJZ4dXwL1K0yEp0dB5kgGpoZJdpnzGKHcHqAzpizA6rbWuLw 8YusIDazAJ/EpG3TgdZxAMV5JTrahCBKPCSunbvFBPHnREaJ612fGCcwSi5gZFjFKJ5aWpyb nlpsmJdarlecmFtcmpeul5yfu4kRGHOn/x3/tIPx66WkQ4wCHIxKPLwas9uihVgTy4orcw8x SnAwK4nw7l0IFOJNSaysSi3Kjy8qzUktPsQozcGiJM7Lp5UWLSSQnliSmp2aWpBaBJNl4uCU amBcv1MtWu3l/693hObr5R/iS8l3k+YN7DoYc3ixId+RCoNpzfFpjBU+Rz7sb/zHPSVELLHG 48vbCm+ZE/3bzfcs97zp+e5P+3v/aYv2/o+sKjy+QCoztpHB+sumh/vWTTO4mnz6RvkR141W VdN0Gze1LQw7HXwpuy77s9b8tiTF8mqNmbdXiDcrsRRnJBpqMRcVJwIAucb3mbUCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrHJMWRmVeSWpSXmKPExsVy+t/xa7rPDrRFG8zewmuxccZ6VovrX56z Wpw/v4Hd4mPPPVaLGef3MVmsPXKX3aL96UtmB3aPTas62Tz6tqxi9Pi8SS6AOYrLJiU1J7Ms tUjfLoEr4/LrXuaCi0YVM48+ZWlg/KLZxcjJISFgItG19jlLFyMXh5DAEkaJda8Ps0I4TUwS O+efZgapYhMwlOh628UGYosIOEh8/vSaEaSIWeAxo8S5xRtYQRLCAnESTR3PwIpYBFQlZr/b wg5i8wrYSfQvnsEIsU5eYvWGA2BDOYHiL473gvUKCdhKLLzznXECI88CRoZVjCKppcW56bnF hnrFibnFpXnpesn5uZsYgaGy7djPzTsYL20MPsQowMGoxMN7YUZbtBBrYllxZe4hRgkOZiUR 3r0LgUK8KYmVValF+fFFpTmpxYcYpTlYlMR5zxtURgkJpCeWpGanphakFsFkmTg4pRoYi6bU 2YXvmL92S8nk809PMEW8mbqg7mDLdz9DF3aPE3c4P/xpk6zjrW9lTWDr2uyotihHMXDHvv0W Qc6r+73z2YtPSH/bfTJmo8STmKi+p9Wm+9Usl1dyMf5NUJtQqmLFqyvV5xt75Uhkt/ykysQd G7jvsB57fm4RT+/VqdebGuazysfOr3qvxFKckWioxVxUnAgALkgscxECAAA= X-CMS-MailID: 20180829155102eucas1p2a4b1c554623ff97a23f85f26a6b537e2 X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20180829155102eucas1p2a4b1c554623ff97a23f85f26a6b537e2 References: <20180829155046.29359-1-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Replace common suspend/resume handling code by generic helper. Handling of PLLs is a bit different in generic code, as they are handled in the same way as other clock registers. Such approach was already used on later Exynos SoCs and worked fine. Tests have shown that it works also on Exynos4 SoCs and significantly simplifies the code. Signed-off-by: Marek Szyprowski --- drivers/clk/samsung/clk-exynos4.c | 147 ++++-------------------------- 1 file changed, 16 insertions(+), 131 deletions(-) -- 2.17.1 diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 0421960eb963..d3bd9ffd8a09 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -16,7 +16,6 @@ #include #include #include -#include #include "clk.h" #include "clk-cpu.h" @@ -157,14 +156,6 @@ enum exynos4_plls { static void __iomem *reg_base; static enum exynos4_soc exynos4_soc; -/* - * Support for CMU save/restore across system suspends - */ -#ifdef CONFIG_PM_SLEEP -static struct samsung_clk_reg_dump *exynos4_save_common; -static struct samsung_clk_reg_dump *exynos4_save_soc; -static struct samsung_clk_reg_dump *exynos4_save_pll; - /* * list of controller registers to be saved and restored during a * suspend/resume cycle. @@ -192,7 +183,7 @@ static const unsigned long exynos4x12_clk_save[] __initconst = { E4X12_PWR_CTRL2, }; -static const unsigned long exynos4_clk_pll_regs[] __initconst = { +static const unsigned long exynos4_clk_regs[] __initconst = { EPLL_LOCK, VPLL_LOCK, EPLL_CON0, @@ -201,9 +192,6 @@ static const unsigned long exynos4_clk_pll_regs[] __initconst = { VPLL_CON0, VPLL_CON1, VPLL_CON2, -}; - -static const unsigned long exynos4_clk_regs[] __initconst = { SRC_LEFTBUS, DIV_LEFTBUS, GATE_IP_LEFTBUS, @@ -276,6 +264,8 @@ static const unsigned long exynos4_clk_regs[] __initconst = { }; static const struct samsung_clk_reg_dump src_mask_suspend[] = { + { .offset = VPLL_CON0, .value = 0x80600302, }, + { .offset = EPLL_CON0, .value = 0x806F0302, }, { .offset = SRC_MASK_TOP, .value = 0x00000001, }, { .offset = SRC_MASK_CAM, .value = 0x11111111, }, { .offset = SRC_MASK_TV, .value = 0x00000111, }, @@ -291,123 +281,6 @@ static const struct samsung_clk_reg_dump src_mask_suspend_e4210[] = { { .offset = E4210_SRC_MASK_LCD1, .value = 0x00001111, }, }; -#define PLL_ENABLED (1 << 31) -#define PLL_LOCKED (1 << 29) - -static void exynos4_clk_enable_pll(u32 reg) -{ - u32 pll_con = readl(reg_base + reg); - pll_con |= PLL_ENABLED; - writel(pll_con, reg_base + reg); - - while (!(pll_con & PLL_LOCKED)) { - cpu_relax(); - pll_con = readl(reg_base + reg); - } -} - -static void exynos4_clk_wait_for_pll(u32 reg) -{ - u32 pll_con; - - pll_con = readl(reg_base + reg); - if (!(pll_con & PLL_ENABLED)) - return; - - while (!(pll_con & PLL_LOCKED)) { - cpu_relax(); - pll_con = readl(reg_base + reg); - } -} - -static int exynos4_clk_suspend(void) -{ - samsung_clk_save(reg_base, exynos4_save_common, - ARRAY_SIZE(exynos4_clk_regs)); - samsung_clk_save(reg_base, exynos4_save_pll, - ARRAY_SIZE(exynos4_clk_pll_regs)); - - exynos4_clk_enable_pll(EPLL_CON0); - exynos4_clk_enable_pll(VPLL_CON0); - - if (exynos4_soc == EXYNOS4210) { - samsung_clk_save(reg_base, exynos4_save_soc, - ARRAY_SIZE(exynos4210_clk_save)); - samsung_clk_restore(reg_base, src_mask_suspend_e4210, - ARRAY_SIZE(src_mask_suspend_e4210)); - } else { - samsung_clk_save(reg_base, exynos4_save_soc, - ARRAY_SIZE(exynos4x12_clk_save)); - } - - samsung_clk_restore(reg_base, src_mask_suspend, - ARRAY_SIZE(src_mask_suspend)); - - return 0; -} - -static void exynos4_clk_resume(void) -{ - samsung_clk_restore(reg_base, exynos4_save_pll, - ARRAY_SIZE(exynos4_clk_pll_regs)); - - exynos4_clk_wait_for_pll(EPLL_CON0); - exynos4_clk_wait_for_pll(VPLL_CON0); - - samsung_clk_restore(reg_base, exynos4_save_common, - ARRAY_SIZE(exynos4_clk_regs)); - - if (exynos4_soc == EXYNOS4210) - samsung_clk_restore(reg_base, exynos4_save_soc, - ARRAY_SIZE(exynos4210_clk_save)); - else - samsung_clk_restore(reg_base, exynos4_save_soc, - ARRAY_SIZE(exynos4x12_clk_save)); -} - -static struct syscore_ops exynos4_clk_syscore_ops = { - .suspend = exynos4_clk_suspend, - .resume = exynos4_clk_resume, -}; - -static void __init exynos4_clk_sleep_init(void) -{ - exynos4_save_common = samsung_clk_alloc_reg_dump(exynos4_clk_regs, - ARRAY_SIZE(exynos4_clk_regs)); - if (!exynos4_save_common) - goto err_warn; - - if (exynos4_soc == EXYNOS4210) - exynos4_save_soc = samsung_clk_alloc_reg_dump( - exynos4210_clk_save, - ARRAY_SIZE(exynos4210_clk_save)); - else - exynos4_save_soc = samsung_clk_alloc_reg_dump( - exynos4x12_clk_save, - ARRAY_SIZE(exynos4x12_clk_save)); - if (!exynos4_save_soc) - goto err_common; - - exynos4_save_pll = samsung_clk_alloc_reg_dump(exynos4_clk_pll_regs, - ARRAY_SIZE(exynos4_clk_pll_regs)); - if (!exynos4_save_pll) - goto err_soc; - - register_syscore_ops(&exynos4_clk_syscore_ops); - return; - -err_soc: - kfree(exynos4_save_soc); -err_common: - kfree(exynos4_save_common); -err_warn: - pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", - __func__); -} -#else -static void __init exynos4_clk_sleep_init(void) {} -#endif - /* list of all parent clock list */ PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", }; @@ -1532,7 +1405,19 @@ static void __init exynos4_clk_init(struct device_node *np, if (soc == EXYNOS4X12) exynos4x12_core_down_clock(); - exynos4_clk_sleep_init(); + + samsung_clk_sleep_init2(reg_base, exynos4_clk_regs, + ARRAY_SIZE(exynos4_clk_regs), + src_mask_suspend, + ARRAY_SIZE(src_mask_suspend)); + if (exynos4_soc == EXYNOS4210) + samsung_clk_sleep_init2(reg_base, exynos4210_clk_save, + ARRAY_SIZE(exynos4210_clk_save), + src_mask_suspend_e4210, + ARRAY_SIZE(src_mask_suspend_e4210)); + else + samsung_clk_sleep_init(reg_base, exynos4x12_clk_save, + ARRAY_SIZE(exynos4x12_clk_save)); samsung_clk_of_add_provider(np, ctx);