[edk2,edk2-platforms,v5,02/28] Silicon/Hisilicon/D0x: Move RAS macro to PlatformArch.h

Message ID 20180831132710.23055-3-ming.huang@linaro.org
State New
Headers show
Series
  • Upload for D06 platform
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Commit Message

Ming Huang Aug. 31, 2018, 1:26 p.m.
From: Sun Yuanchen <sunyuanchen@huawei.com>


Move some RAS macros definition to PlatformArch.h for
unifying D0x

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>

Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

---
 Silicon/Hisilicon/Hi1610/Include/PlatformArch.h |  9 +++++++--
 Silicon/Hisilicon/Hi1616/Include/PlatformArch.h | 12 ++++++++++++
 2 files changed, 19 insertions(+), 2 deletions(-)

-- 
2.18.0

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Patch

diff --git a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
index 2ff076901e..f39ae0748c 100644
--- a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
+++ b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
@@ -1,7 +1,7 @@ 
 /** @file
 *
-*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*  Copyright (c) 2015 - 2018, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015 - 2018, Linaro Limited. All rights reserved.
 *
 *  This program and the accompanying materials
 *  are licensed and made available under the terms and conditions of the BSD License
@@ -32,6 +32,11 @@ 
 
 #define S1_BASE               0x40000000000
 
+#define RASC_BASE                (0x5000)
+/* configuration register for Rank statistical information */
+#define RASC_CFG_INFOIDX_REG     (RASC_BASE + 0x5C)
+/* configuration register for Sparing level */
+#define RASC_CFG_SPLVL_REG       (RASC_BASE + 0xB8)
 
 //
 // ACPI table information used to initialize tables.
diff --git a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
index 60a60593be..e02e4bdabd 100644
--- a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
+++ b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
@@ -30,6 +30,18 @@ 
 // Max NUMA node number for each node type
 #define MAX_NUM_PER_TYPE 8
 
+#define RASC_BASE                (0x5000)
+/* configuration register for Rank statistical information */
+#define RASC_CFG_INFOIDX_REG     (RASC_BASE + 0x5C)
+/* configuration register for Sparing level */
+#define RASC_CFG_SPLVL_REG       (RASC_BASE + 0xB8)
+
+// for acpi
+#define NODE_IN_SOCKET                                  2
+#define CORE_NUM_PER_SOCKET                             32
+#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT        10
+#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT       8
+
 #define S1_BASE               0x40000000000
 
 //