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[192.237.175.120]) by mx.google.com with ESMTPS id r6-v6si11541813ioa.14.2018.09.03.07.55.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Sep 2018 07:55:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1fwqE8-0000Yh-WE; Mon, 03 Sep 2018 14:53:16 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1fwqE7-0000YP-Dj for xen-devel@lists.xen.org; Mon, 03 Sep 2018 14:53:15 +0000 X-Inumbo-ID: 31b9b2df-af89-11e8-a6a9-d7ebe60f679a Received: from huawei.com (unknown [185.176.76.210]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTPS id 31b9b2df-af89-11e8-a6a9-d7ebe60f679a; Mon, 03 Sep 2018 14:54:01 +0000 (UTC) Received: from lhreml703-cah.china.huawei.com (unknown [172.18.7.107]) by Forcepoint Email with ESMTP id 0F5EBF12F4F9B; Mon, 3 Sep 2018 15:53:11 +0100 (IST) Received: from FRAEMA701-CHM.china.huawei.com (10.206.14.50) by lhreml703-cah.china.huawei.com (10.201.108.44) with Microsoft SMTP Server (TLS) id 14.3.399.0; Mon, 3 Sep 2018 15:53:12 +0100 Received: from FRAEML521-MBX.china.huawei.com ([169.254.1.206]) by FRAEMA701-CHM.china.huawei.com ([10.206.14.50]) with mapi id 14.03.0415.000; Mon, 3 Sep 2018 16:53:05 +0200 From: Shameerali Kolothum Thodi To: "xen-devel@lists.xen.org" Thread-Topic: Xen Dom0 boot failure on platform that supports ARM GICv4 Thread-Index: AdRDlNxJ7qw54CgwTcaZd33ww5YvtQ== Date: Mon, 3 Sep 2018 14:53:05 +0000 Message-ID: <5FC3163CFD30C246ABAA99954A238FA83877FE25@FRAEML521-MBX.china.huawei.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.202.227.237] MIME-Version: 1.0 X-CFilter-Loop: Reflected Subject: [Xen-devel] Xen Dom0 boot failure on platform that supports ARM GICv4 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: "julien.grall@arm.com" , "sstabellini@kernel.org" , Linuxarm Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Hi, I am trying to boot xen(stable-4.11) on one of our ARM64 boards which has support for GICv4. But dom0(kernel 4.18) boot fails with the below trap, XEN) ............done. (XEN) Std. Loglevel: All (XEN) Guest Loglevel: All (XEN) *** Serial input -> DOM0 (type 'CTRL-a' three times to switch input to Xen) (XEN) Freed 304kB init memory. (XEN) traps.c:2007:d0v0 HSR=0x93800004 pc=0xffff00000841af04 gva=0xffff00000b10ffe8 gpa=0x004000aa10ffe8 After a bit of debugging, it looks like, the GICR size used in vgic_v3_domain_init() is GICv4 GICR size(256K) and this upsets the first_cpu calculations. Since dom0 gicv3 is also an emulated one, I think the size should be restricted to use the GICv3 GICR size(128K). I have made the below changes and is able to boot dom0 now. But not sure, this is the right approach to fix the issue. Please let me know your thoughts. Thanks, Shameer ---->8------------- Reported-by: Shameerali Kolothum Thodi Signed-off-by: Julien Grall diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index b2ed0f8..bf028cc 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1783,7 +1783,8 @@ static int __init gicv3_init(void) reg = readl_relaxed(GICD + GICD_TYPER); intid_bits = GICD_TYPE_ID_BITS(reg); - vgic_v3_setup_hw(dbase, gicv3.rdist_count, gicv3.rdist_regions, intid_bits); + vgic_v3_setup_hw(dbase, gicv3.rdist_count, gicv3.rdist_regions, + intid_bits, gic_dist_supports_dvis()); gicv3_init_v2(); spin_lock_init(&gicv3.lock); diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 4b42739..0f53d88 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -59,18 +59,21 @@ static struct { unsigned int nr_rdist_regions; const struct rdist_region *regions; unsigned int intid_bits; /* Number of interrupt ID bits */ + bool dvis; } vgic_v3_hw; void vgic_v3_setup_hw(paddr_t dbase, unsigned int nr_rdist_regions, const struct rdist_region *regions, - unsigned int intid_bits) + unsigned int intid_bits, + bool dvis) { vgic_v3_hw.enabled = true; vgic_v3_hw.dbase = dbase; vgic_v3_hw.nr_rdist_regions = nr_rdist_regions; vgic_v3_hw.regions = regions; vgic_v3_hw.intid_bits = intid_bits; + vgic_v3_hw.dvis = dvis; } static struct vcpu *vgic_v3_irouter_to_vcpu(struct domain *d, uint64_t irouter) @@ -1673,6 +1676,9 @@ static int vgic_v3_domain_init(struct domain *d) { paddr_t size = vgic_v3_hw.regions[i].size; + if (vgic_v3_hw.dvis && (size == GICV4_GICR_SIZE)) + size = GICV3_GICR_SIZE; + d->arch.vgic.rdist_regions[i].base = vgic_v3_hw.regions[i].base; d->arch.vgic.rdist_regions[i].size = size; @@ -1680,6 +1686,7 @@ static int vgic_v3_domain_init(struct domain *d) d->arch.vgic.rdist_regions[i].first_cpu = first_cpu; first_cpu += size / GICV3_GICR_SIZE; + } d->arch.vgic.intid_bits = vgic_v3_hw.intid_bits; diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index a35449b..dabd5f6 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -979,7 +979,8 @@ unsigned int vgic_max_vcpus(const struct domain *d) void vgic_v3_setup_hw(paddr_t dbase, unsigned int nr_rdist_regions, const struct rdist_region *regions, - unsigned int intid_bits) + unsigned int intid_bits, + bool dvis) { panic("New VGIC implementation does not yet support GICv3."); } diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3_defs.h index 10a2aee..de1facf 100644 --- a/xen/include/asm-arm/gic_v3_defs.h +++ b/xen/include/asm-arm/gic_v3_defs.h @@ -73,6 +73,8 @@ /* Two pages for the RD_base and SGI_base register frame. */ #define GICV3_GICR_SIZE (2 * SZ_64K) +#define GICV4_GICR_SIZE (4 * SZ_64K) + #define GICR_CTLR (0x0000) #define GICR_IIDR (0x0004) #define GICR_TYPER (0x0008) diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 2a58ea3..3890ad8 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -364,7 +364,8 @@ struct rdist_region; void vgic_v3_setup_hw(paddr_t dbase, unsigned int nr_rdist_regions, const struct rdist_region *regions, - unsigned int intid_bits); + unsigned int intid_bits, + bool dvis); #endif #endif /* __ASM_ARM_VGIC_H__ */