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Fri, 14 Sep 2018 06:55:14 +0000 (GMT) X-AuditID: cbfec7f4-835ff700000010c6-12-5b9b5b526c40 Received: from eusync4.samsung.com ( [203.254.199.214]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 1E.59.04128.25B5B9B5; Fri, 14 Sep 2018 07:55:14 +0100 (BST) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0PF100CE09VXUJ70@eusync4.samsung.com>; Fri, 14 Sep 2018 07:55:14 +0100 (BST) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Sylwester Nawrocki Subject: [PATCH] ARM: dts: exynos: Correct audio subsystem parent clock on Peach Chromebooks Date: Fri, 14 Sep 2018 08:55:03 +0200 Message-id: <20180914065503.21874-1-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupmkeLIzCtJLcpLzFFi42LZduznOd3g6NnRBmfuMllsnLGe1eL8+Q3s FjPO72OyWHvkLrtF+9OXzA6sHptWdbJ59G1ZxejxeZNcAHMUl01Kak5mWWqRvl0CV0bzqd/M BTe4K/Y8PMXWwNjO1cXIySEhYCJx4fZ3li5GLg4hgRWMEg+ud7BDOJ8ZJeadXcMKU3V5zjM2 iMQyRom7Oy8zQzgNTBK75/awgVSxCRhKdL3tArNFBFQlPrctABvFLLAbaNS0qewgCWGBOIlL t1ewgNgsQEVz/28Da+AVsJW49GUnE8Q6eYnVGw6AbZAQuMgqsevZFKg7XCTWX7kPVSQs8er4 FnYIW0bi8uRuFoiGZkaJ9hmz2CGcHkaJrXN2sEFUWUscPn4RbBKzAJ/EpG3TgVZwAMV5JTra hCBKPCTurj8Mdp2QQKzEu1l3WSYwSixgZFjFKJ5aWpybnlpslJdarlecmFtcmpeul5yfu4kR GEWn/x3/soNx15+kQ4wCHIxKPLwOz2dFC7EmlhVX5h5ilOBgVhLhXR8KFOJNSaysSi3Kjy8q zUktPsQozcGiJM7Lp5UWLSSQnliSmp2aWpBaBJNl4uCUamA0/heyfFbZuX83gp4nv4kSFtBJ y5SqPKYiO4OnPYDjRIAqa6/nMh+u8H0PNRkyLindOmhhbS1yWfpTwlGpKvmF0w8f3rjnUAzj vY4Ax+M3Ktfc6vm83KYhMPVci/Tr3W0G3bLXHCdZB54osFu4oKqh2iFKPseTI3s2l0rEC9dP EstmvRfSL1RiKc5INNRiLipOBADW5GbangIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrDJMWRmVeSWpSXmKPExsVy+t/xa7pB0bOjDdZP4LbYOGM9q8X58xvY LWac38dksfbIXXaL9qcvmR1YPTat6mTz6NuyitHj8ya5AOYoLpuU1JzMstQifbsErozmU7+Z C25wV+x5eIqtgbGdq4uRk0NCwETi8pxnbF2MXBxCAksYJS5+PcoC4TQxSWx5NJ0ZpIpNwFCi 620XG4gtIqAq8bltATtIEbPAXkaJs9fbmUASwgJxEpdur2ABsVmAiub+3wbWwCtgK3Hpy04m iHXyEqs3HGCewMi1gJFhFaNIamlxbnpusZFecWJucWleul5yfu4mRqCftx37uWUHY9e74EOM AhyMSjy8Ds9nRQuxJpYVV+YeYpTgYFYS4V0fChTiTUmsrEotyo8vKs1JLT7EKM3BoiTOe96g MkpIID2xJDU7NbUgtQgmy8TBKdXAWFu0bTej9KzLhptUrF8dk3/wMOKZ6s6WhZmb1PJuFLxS jzgVYftGY0J94iFNBdatczgDd87bl7pyZgVTqu/F3yv9PWdZLP98ZJKY6f9nv7ZL9bq89nue cOiB6Yy2L3Linz7Ehq7my77o+y93inyhj8yq4x57tn9bySHZcPHTRO+Ls98KzGiZbaLEUpyR aKjFXFScCADCJ0Vg7wEAAA== X-CMS-MailID: 20180914065514eucas1p10efa595bd4ed3a24075838093f22c8f8 X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20180914065514eucas1p10efa595bd4ed3a24075838093f22c8f8 References: Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The proper parent clock for audio subsystem for Exynos5420 and Exynos5800 SoCs is CLK_MAU_EPLL. This fixes following warning: clk: failed to reparent mout_audss to fout_epll: -22 Fixes: ed7d1307077e: ARM: dts: exynos: Enable HDMI audio support on Peach Pit Fixes: bae0f445c1e7: ARM: dts: exynos: Enable HDMI audio support on Peach Pi Signed-off-by: Marek Szyprowski --- arch/arm/boot/dts/exynos5420-peach-pit.dts | 2 +- arch/arm/boot/dts/exynos5800-peach-pi.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 4ebb37043223..f78db6809cca 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -153,7 +153,7 @@ &clock_audss { assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>; - assigned-clock-parents = <&clock CLK_FOUT_EPLL>; + assigned-clock-parents = <&clock CLK_MAU_EPLL>; }; &cpu0 { diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 7ada8b53ea31..e0f470fe54c8 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -153,7 +153,7 @@ &clock_audss { assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>; - assigned-clock-parents = <&clock CLK_FOUT_EPLL>; + assigned-clock-parents = <&clock CLK_MAU_EPLL>; }; &cpu0 {