From patchwork Wed Sep 19 17:29:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Salil Mehta X-Patchwork-Id: 147033 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp986693ljw; Wed, 19 Sep 2018 10:31:11 -0700 (PDT) X-Google-Smtp-Source: ANB0VdbS6s0sPtFrGv3YuXha5qx+elMpJs05uwMnqNoCfqMvj6up+bTllZEzDqYLdlPoSXAsKXqs X-Received: by 2002:a65:5c83:: with SMTP id a3-v6mr33850338pgt.164.1537378270983; Wed, 19 Sep 2018 10:31:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537378270; cv=none; d=google.com; s=arc-20160816; b=EWvVFIRFjUsyeYV44s36d9GRgEMw/fW/+p3RLLKqYLuN5bp+29DHAGriWV+sFzmljc k0wyfDfvfnb74d78ipFIrrPNKmzLpyxRO6Q+VOHDp0sjmD9jlz3LW35wApTBc2Fr9eho lONi1ppoD+tY9a0r1Hs2me8CiW2CvrIVObbh98c7Dok2qlQ9a5uwL/DOKsykdf9+3b9f d0pOwiATc5w99Tcs5qUo2TQXK7P5+8uieTrtZr2wDLKFQxc2y0bAYZEZg5zPQAQG0pP3 rif8WMnHz94xRnPQR0PmV6PqOht02F2gz7OIxeGM6R4ynArHkgLYDS9ckCslW5wj31zt 8KAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=Sne03c2Q6EgsbD/+oNnqsXXD81K0xzJyJSrQtBMK1is=; b=LdZ1SlWj0TUGFboikMDD5PDok3hmzx5wrqk1MJ7bak8TDezgsaTvtwlDfs/AJnFrxN 80Eb5Mbbff2rBL1boIylG+GA5PnC2c9E4civhJyAiIKt3IMhtIlszu0DWyuXENQBWMDn ooYlfCLk11goukqKn2+xSr/WNPYiFNUKxhM46Q0WWc9QJTHhTk3B/t7PmjqsTucwSVqp 4QVdSF2of2qGfQGFplMn1xVMQMcbaFGq/nuEY3Th6611cxmZNZrNv3ZezSk0hNo8neuF czP+PsuQgyorF+kCSAEOHiaH/PFM1oUnfU3vJoZTUdMq+yVGQptQAsctb2dgHpn4O7N6 Ffzw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k3-v6si21143200pld.6.2018.09.19.10.31.10; Wed, 19 Sep 2018 10:31:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733142AbeISXKE (ORCPT + 10 others); Wed, 19 Sep 2018 19:10:04 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:12206 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1733104AbeISXKE (ORCPT ); Wed, 19 Sep 2018 19:10:04 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 0A155DE362B08; Thu, 20 Sep 2018 01:31:03 +0800 (CST) Received: from S00293818-DELL1.china.huawei.com (10.202.226.54) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.399.0; Thu, 20 Sep 2018 01:30:56 +0800 From: Salil Mehta To: CC: , , , , , , Subject: [PATCH net-next 01/12] net: hns3: Add default irq affinity Date: Wed, 19 Sep 2018 18:29:47 +0100 Message-ID: <20180919172958.12992-2-salil.mehta@huawei.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20180919172958.12992-1-salil.mehta@huawei.com> References: <20180919172958.12992-1-salil.mehta@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.226.54] X-CFilter-Loop: Reflected Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Peng Li All irq will float to cpu0 if do not set irq affinity. This patch adds default irq affinity in hns3 driver, users can also change the irq affinity in OS. Signed-off-by: Peng Li Signed-off-by: Salil Mehta --- drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 49 +++++++++++++++++++++++++ drivers/net/ethernet/hisilicon/hns3/hns3_enet.h | 2 + 2 files changed, 51 insertions(+) -- 2.7.4 diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c index 75e8ee9..052b7fb 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c @@ -66,6 +66,23 @@ static irqreturn_t hns3_irq_handle(int irq, void *vector) return IRQ_HANDLED; } +/* This callback function is used to set affinity changes to the irq affinity + * masks when the irq_set_affinity_notifier function is used. + */ +static void hns3_nic_irq_affinity_notify(struct irq_affinity_notify *notify, + const cpumask_t *mask) +{ + struct hns3_enet_tqp_vector *tqp_vectors = + container_of(notify, struct hns3_enet_tqp_vector, + affinity_notify); + + tqp_vectors->affinity_mask = *mask; +} + +static void hns3_nic_irq_affinity_release(struct kref *ref) +{ +} + static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) { struct hns3_enet_tqp_vector *tqp_vectors; @@ -77,6 +94,10 @@ static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) continue; + /* clear the affinity notifier and affinity mask */ + irq_set_affinity_notifier(tqp_vectors->vector_irq, NULL); + irq_set_affinity_hint(tqp_vectors->vector_irq, NULL); + /* release the irq resource */ free_irq(tqp_vectors->vector_irq, tqp_vectors); tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; @@ -127,6 +148,15 @@ static int hns3_nic_init_irq(struct hns3_nic_priv *priv) return ret; } + tqp_vectors->affinity_notify.notify = + hns3_nic_irq_affinity_notify; + tqp_vectors->affinity_notify.release = + hns3_nic_irq_affinity_release; + irq_set_affinity_notifier(tqp_vectors->vector_irq, + &tqp_vectors->affinity_notify); + irq_set_affinity_hint(tqp_vectors->vector_irq, + &tqp_vectors->affinity_mask); + tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; } @@ -2640,6 +2670,23 @@ static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, group->count++; } +static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv) +{ + struct pci_dev *pdev = priv->ae_handle->pdev; + struct hns3_enet_tqp_vector *tqp_vector; + int num_vectors = priv->vector_num; + int numa_node; + int vector_i; + + numa_node = dev_to_node(&pdev->dev); + + for (vector_i = 0; vector_i < num_vectors; vector_i++) { + tqp_vector = &priv->tqp_vector[vector_i]; + cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node), + &tqp_vector->affinity_mask); + } +} + static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) { struct hnae3_ring_chain_node vector_ring_chain; @@ -2648,6 +2695,8 @@ static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) int ret = 0; u16 i; + hns3_nic_set_cpumask(priv); + for (i = 0; i < priv->vector_num; i++) { tqp_vector = &priv->tqp_vector[i]; hns3_vector_gl_rl_init_hw(tqp_vector, priv); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h index cb450d7..31fa21f 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h @@ -491,7 +491,9 @@ struct hns3_enet_tqp_vector { struct hns3_enet_ring_group rx_group; struct hns3_enet_ring_group tx_group; + cpumask_t affinity_mask; u16 num_tqps; /* total number of tqps in TQP vector */ + struct irq_affinity_notify affinity_notify; char name[HNAE3_INT_NAME_LEN];