clk: samsung: exynos5420: Enable PERIS clocks for suspend

Message ID 20180924110120.21319-1-m.szyprowski@samsung.com
State New
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Series
  • clk: samsung: exynos5420: Enable PERIS clocks for suspend
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Commit Message

Marek Szyprowski Sept. 24, 2018, 11:01 a.m.
Ensure that clocks for core SoC modules (including TZPC0..9 modules)
are enabled for suspend/resume cycle. This fixes suspend/resume
support on Exynos5422-based Odroid XU3/XU4 boards.

Suggested-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

---
 drivers/clk/samsung/clk-exynos5420.c | 1 +
 1 file changed, 1 insertion(+)

-- 
2.17.1

Comments

Sylwester Nawrocki Oct. 3, 2018, 8:44 p.m. | #1
On 09/24/2018 01:01 PM, Marek Szyprowski wrote:
> Ensure that clocks for core SoC modules (including TZPC0..9 modules)

> are enabled for suspend/resume cycle. This fixes suspend/resume

> support on Exynos5422-based Odroid XU3/XU4 boards.

> 

> Suggested-by: Joonyoung Shim <jy0922.shim@samsung.com>

> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>


Patch applied, thanks.

Patch

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index a2d6e7f4bcd3..34cce3c5898f 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -276,6 +276,7 @@  static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
 	{ .offset = GATE_BUS_TOP,		.value = 0xffffffff, },
 	{ .offset = GATE_BUS_DISP1,		.value = 0xffffffff, },
 	{ .offset = GATE_IP_PERIC,		.value = 0xffffffff, },
+	{ .offset = GATE_IP_PERIS,		.value = 0xffffffff, },
 };
 
 /* list of all parent clocks */