| Message ID | 20181003180711.19335-5-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | softfloat: Fix division | expand |
On Wed, Oct 03, 2018 at 01:07:11PM -0500, Richard Henderson wrote: > The ISA has a 128/64-bit division instruction, though it assumes the > low 64-bits of the numerator are 0, and so requires a bit more fixup > than a full 128-bit division insn. > > Cc: qemu-ppc@nongnu.org > Cc: Alexander Graf <agraf@suse.de> > Cc: David Gibson <david@gibson.dropbear.id.au> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> > --- > include/fpu/softfloat-macros.h | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h > index e702607b43..001bf4f23c 100644 > --- a/include/fpu/softfloat-macros.h > +++ b/include/fpu/softfloat-macros.h > @@ -632,6 +632,22 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1, > asm("dlgr %0, %1" : "+r"(n) : "r"(d)); > *r = n >> 64; > return n; > +#elif defined(_ARCH_PPC64) > + /* From Power ISA 3.0B, programming note for divdeu. */ > + uint64_t q1, q2, Q, r1, r2, R; > + asm("divdeu %0,%2,%4; divdu %1,%3,%4" > + : "=&r"(q1), "=r"(q2) > + : "r"(n1), "r"(n0), "r"(d)); > + r1 = -(q1 * d); /* low part of (n1<<64) - (q1 * d) */ > + r2 = n0 - (q2 * d); > + Q = q1 + q2; > + R = r2 + r1; > + if (R < r2 || R >= d) { /* overflow implies R > d */ > + Q += 1; > + R -= d; > + } > + *r = R; > + return Q; > #else > uint64_t d0, d1, q0, q1, r1, r0, m; > -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson
diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h index e702607b43..001bf4f23c 100644 --- a/include/fpu/softfloat-macros.h +++ b/include/fpu/softfloat-macros.h @@ -632,6 +632,22 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1, asm("dlgr %0, %1" : "+r"(n) : "r"(d)); *r = n >> 64; return n; +#elif defined(_ARCH_PPC64) + /* From Power ISA 3.0B, programming note for divdeu. */ + uint64_t q1, q2, Q, r1, r2, R; + asm("divdeu %0,%2,%4; divdu %1,%3,%4" + : "=&r"(q1), "=r"(q2) + : "r"(n1), "r"(n0), "r"(d)); + r1 = -(q1 * d); /* low part of (n1<<64) - (q1 * d) */ + r2 = n0 - (q2 * d); + Q = q1 + q2; + R = r2 + r1; + if (R < r2 || R >= d) { /* overflow implies R > d */ + Q += 1; + R -= d; + } + *r = R; + return Q; #else uint64_t d0, d1, q0, q1, r1, r0, m;
The ISA has a 128/64-bit division instruction, though it assumes the low 64-bits of the numerator are 0, and so requires a bit more fixup than a full 128-bit division insn. Cc: qemu-ppc@nongnu.org Cc: Alexander Graf <agraf@suse.de> Cc: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- include/fpu/softfloat-macros.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.17.1