diff mbox series

[ARM/FDPIC,v3,12/21,ARM] FDPIC: Restore r9 after we call __aeabi_read_tp

Message ID 20181011133518.17258-13-christophe.lyon@st.com
State New
Headers show
Series FDPIC ABI for ARM | expand

Commit Message

Christophe Lyon Oct. 11, 2018, 1:34 p.m. UTC 
We call __aeabi_read_tp() to get the thread pointer. Since this is a
function call, we have to restore the FDPIC register afterwards.

2018-XX-XX  Christophe Lyon  <christophe.lyon@st.com>
	Mickaël Guêné <mickael.guene@st.com>

	gcc/
	* config/arm/arm.c (arm_load_tp): Add FDPIC support.
	* config/arm/arm.md (load_tp_soft_fdpic): New pattern.
	(load_tp_soft): Disable in FDPIC mode.

Change-Id: I0a2e3466c9afb869ad8e844083ad178de014658e

-- 
2.6.3

Comments

Christophe Lyon Oct. 19, 2018, 1:42 p.m. UTC | #1 
On 11/10/2018 15:34, Christophe Lyon wrote:
> We call __aeabi_read_tp() to get the thread pointer. Since this is a

> function call, we have to restore the FDPIC register afterwards.

> 

> 2018-XX-XX  Christophe Lyon  <christophe.lyon@st.com>

> 	Mickaël Guêné <mickael.guene@st.com>

> 

> 	gcc/

> 	* config/arm/arm.c (arm_load_tp): Add FDPIC support.

> 	* config/arm/arm.md (load_tp_soft_fdpic): New pattern.

> 	(load_tp_soft): Disable in FDPIC mode.

> 

> Change-Id: I0a2e3466c9afb869ad8e844083ad178de014658e

> 

> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c

> index d7b7d99..d3a60cb 100644

> --- a/gcc/config/arm/arm.c

> +++ b/gcc/config/arm/arm.c

> @@ -8646,7 +8646,25 @@ arm_load_tp (rtx target)

>   

>         rtx tmp;

>   

> -      emit_insn (gen_load_tp_soft ());

> +      if (TARGET_FDPIC)

> +	{

> +	  rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (3));

> +

> +	  emit_insn (gen_load_tp_soft_fdpic ());

> +

> +	  /* Restore r9.  */

> +	  XVECEXP (par, 0, 0)

> +	    = gen_rtx_UNSPEC (VOIDmode,

> +			      gen_rtvec (2, gen_rtx_REG (Pmode, FDPIC_REGNUM),

> +					 get_hard_reg_initial_val (Pmode, FDPIC_REGNUM)),

> +			      UNSPEC_PIC_RESTORE);

> +	  XVECEXP (par, 0, 1) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, FDPIC_REGNUM));

> +	  XVECEXP (par, 0, 2)

> +	    = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, FDPIC_REGNUM));


There is the same problem here as in patch 04/21, fixed in follow-up version.

> +	  emit_insn (par);

> +	}

> +      else

> +	emit_insn (gen_load_tp_soft ());

>   

>         tmp = gen_rtx_REG (SImode, R0_REGNUM);

>         emit_move_insn (target, tmp);

> diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md

> index 09a0701..6fea087 100644

> --- a/gcc/config/arm/arm.md

> +++ b/gcc/config/arm/arm.md

> @@ -11485,12 +11485,25 @@

>   )

>   

>   ;; Doesn't clobber R1-R3.  Must use r0 for the first operand.

> +(define_insn "load_tp_soft_fdpic"

> +  [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS))

> +   (clobber (reg:SI 9))

> +   (clobber (reg:SI LR_REGNUM))

> +   (clobber (reg:SI IP_REGNUM))

> +   (clobber (reg:CC CC_REGNUM))]

> +  "TARGET_SOFT_TP && TARGET_FDPIC"

> +  "bl\\t__aeabi_read_tp\\t@ load_tp_soft"

> +  [(set_attr "conds" "clob")

> +   (set_attr "type" "branch")]

> +)

> +

> +;; Doesn't clobber R1-R3.  Must use r0 for the first operand.

>   (define_insn "load_tp_soft"

>     [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS))

>      (clobber (reg:SI LR_REGNUM))

>      (clobber (reg:SI IP_REGNUM))

>      (clobber (reg:CC CC_REGNUM))]

> -  "TARGET_SOFT_TP"

> +  "TARGET_SOFT_TP && !TARGET_FDPIC"

>     "bl\\t__aeabi_read_tp\\t@ load_tp_soft"

>     [(set_attr "conds" "clob")

>      (set_attr "type" "branch")]

>
diff mbox series

Patch

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index d7b7d99..d3a60cb 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -8646,7 +8646,25 @@  arm_load_tp (rtx target)
 
       rtx tmp;
 
-      emit_insn (gen_load_tp_soft ());
+      if (TARGET_FDPIC)
+	{
+	  rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (3));
+
+	  emit_insn (gen_load_tp_soft_fdpic ());
+
+	  /* Restore r9.  */
+	  XVECEXP (par, 0, 0)
+	    = gen_rtx_UNSPEC (VOIDmode,
+			      gen_rtvec (2, gen_rtx_REG (Pmode, FDPIC_REGNUM),
+					 get_hard_reg_initial_val (Pmode, FDPIC_REGNUM)),
+			      UNSPEC_PIC_RESTORE);
+	  XVECEXP (par, 0, 1) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, FDPIC_REGNUM));
+	  XVECEXP (par, 0, 2)
+	    = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, FDPIC_REGNUM));
+	  emit_insn (par);
+	}
+      else
+	emit_insn (gen_load_tp_soft ());
 
       tmp = gen_rtx_REG (SImode, R0_REGNUM);
       emit_move_insn (target, tmp);
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 09a0701..6fea087 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -11485,12 +11485,25 @@ 
 )
 
 ;; Doesn't clobber R1-R3.  Must use r0 for the first operand.
+(define_insn "load_tp_soft_fdpic"
+  [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS))
+   (clobber (reg:SI 9))
+   (clobber (reg:SI LR_REGNUM))
+   (clobber (reg:SI IP_REGNUM))
+   (clobber (reg:CC CC_REGNUM))]
+  "TARGET_SOFT_TP && TARGET_FDPIC"
+  "bl\\t__aeabi_read_tp\\t@ load_tp_soft"
+  [(set_attr "conds" "clob")
+   (set_attr "type" "branch")]
+)
+
+;; Doesn't clobber R1-R3.  Must use r0 for the first operand.
 (define_insn "load_tp_soft"
   [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS))
    (clobber (reg:SI LR_REGNUM))
    (clobber (reg:SI IP_REGNUM))
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_SOFT_TP"
+  "TARGET_SOFT_TP && !TARGET_FDPIC"
   "bl\\t__aeabi_read_tp\\t@ load_tp_soft"
   [(set_attr "conds" "clob")
    (set_attr "type" "branch")]