From patchwork Thu Oct 11 18:23:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 148665 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp2455081lji; Thu, 11 Oct 2018 11:24:21 -0700 (PDT) X-Google-Smtp-Source: ACcGV61L87Lrrj3IlYZsqjPli/KikVZpEFh5yfKSF+c2EF8TRlmcH+V5YxVohk+bCYZ5Vz40kWVC X-Received: by 2002:a63:5353:: with SMTP id t19-v6mr2341538pgl.199.1539282261120; Thu, 11 Oct 2018 11:24:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539282261; cv=none; d=google.com; s=arc-20160816; b=0uQYUKTCfkh46e4+eHu55jN6owzk17XMeBn7T1uPe4Cdvmh8plseK+IleIe8RrrxKk +kCfa1dYnZOGMfvErgIoUMxyzlib6fue5NkDweR3LHDeYFQuUr5s2f0jdlwAqjDatHjC CkF8jtsEOeB0PklubXOFr/GEbhrqUMQnwab0zSO+QRHqb0l/0a9gDamsACkaDlYP50oU BAjD00L6ggT/m4kWVDw2TmLIht+n19i9mBxIRgrvUBI69kjhdvOmzRqtRmAmPCvxC+Bx L0DXrgVCfNHLi1V0Plg8AWF8hCufZvdjHF3ZJutMCPAA2zFgX9RGoqMFOBI8mLGL9eNQ hYBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=message-id:date:subject:to:from:dkim-signature:delivered-to:sender :list-help:list-post:list-archive:list-subscribe:list-unsubscribe :list-id:precedence:mailing-list:dkim-signature:domainkey-signature; bh=FQ1Cz+MjHrscDEkApq4UUnSvjIqC1bp2aXJDgJilGkI=; b=BoJQsajIyuLw42kZWZyLVB3lsJRlafYGLUtCuCw7etPTcWesCtNBkF6NLW8eCUdicB Dnfy7YsaR1UsLaTdJ8hOViPPR5WCn4Sr48yg02q+I5VEuXNliIKDWlaaPzoobIAnq/AT /typdOYdTN04Il2XKy+tBwjqZsyAi75ZCY+SEDnTuI4ESXb8pZxxMmWqvOX4F3wsq++u /K44X4K7gmJmoW9jJxzJJsgZHBY3HXeqVh2tWzD2QdMF7u5ycULIla/sJrKN10Qqdaf5 S5lSZD1cp9lXExBt/1Vnq3If4ze8bhN0jIPeTFnOqQNV0qXzakfS/cElH4brZwDdRudg KiVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=f8bhffGF; dkim=pass header.i=@linaro.org header.s=google header.b=IpsVjX07; spf=pass (google.com: domain of libc-alpha-return-96378-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="libc-alpha-return-96378-patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id k12-v6si27689543pls.426.2018.10.11.11.24.20 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Oct 2018 11:24:21 -0700 (PDT) Received-SPF: pass (google.com: domain of libc-alpha-return-96378-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=f8bhffGF; dkim=pass header.i=@linaro.org header.s=google header.b=IpsVjX07; spf=pass (google.com: domain of libc-alpha-return-96378-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="libc-alpha-return-96378-patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id; q=dns; s= default; b=mikfDt044aI5TMG1QZHYEVVMsXy0MP7M/v/b7K+nIKtcQ5Ih2Hi8v 17RvAY3cSnJoKlGHphUhuxWdb4N9pQJpB3LtTRcGYo5nAgXDN4loK4ZBS25+J+Re 9DHbBcTGi6Jj9dckEHKxR38rkp7jHYJ8ggYIqSvFup68dy/Osg+eds= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id; s=default; bh=h7jhr5uAJuDO3YcBYnEbi+b4osc=; b=f8bhffGFvdxRb9iTbDDW1/EEN/P8 3kppzRvWOquRuThILKBhCvC7LeH0592/XYDsL9bNs56cxWnsIcocCoHIIlMQInJn awJYaYEiejjBeUehI8mpkHnKc3CG2gDxvqHyIOjU8Mjy6pbp+nW0qR14YrmIyOWV /KgnMwHfpXjxo3s= Received: (qmail 26407 invoked by alias); 11 Oct 2018 18:24:11 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 26274 invoked by uid 89); 11 Oct 2018 18:24:01 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=H*p:D*org X-HELO: mail-qt1-f195.google.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id; bh=FQ1Cz+MjHrscDEkApq4UUnSvjIqC1bp2aXJDgJilGkI=; b=IpsVjX07yOkvg6aQEViDEPAelY2AZWeXobzfAtCTUK8QYxi5x0vuFKaP//H22z/mev JNpBfFcX9qgHjTFR/2RxAg4c3YjaAOypiuZox/yRfFJeetkwhFyvJBnwB9FyNwWzL1AO CUBKGzIkRJWllF4AvK/BLwXLRO/Yib3UX3yKw= Return-Path: From: Adhemerval Zanella To: libc-alpha@sourceware.org Subject: [PATCH] x86: Fix Haswell strong flags (BZ#23709) Date: Thu, 11 Oct 2018 15:23:52 -0300 Message-Id: <20181011182352.25394-1-adhemerval.zanella@linaro.org> Th commit 'Disable TSX on some Haswell processors.' (2702856bf4) changed the default flags for Haswell models. Previously, new models were handled by the default switch path, which assumed a Core i3/i5/i7 if AVX is available. After the patch, Haswell models (0x3f, 0x3c, 0x45, 0x46) do not set the flags Fast_Rep_String, Fast_Unaligned_Load, Fast_Unaligned_Copy, and Prefer_PMINUB_for_stringop (only the TSX one). This patch fixes it by disentangle the TSX flag handling from the memory optimization ones. The strstr case cited on patch now selects the __strstr_sse2_unaligned as expected for the Haswell cpu. Checked on x86_64-linux-gnu. [BZ #23709] * sysdeps/x86/cpu-features.c (init_cpu_features): Set TSX bits independently of other flags. --- ChangeLog | 6 ++++++ sysdeps/x86/cpu-features.c | 6 ++++++ 2 files changed, 12 insertions(+) -- 2.17.1 diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index f4e0f5a2ed..80b3054cf8 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -316,7 +316,13 @@ init_cpu_features (struct cpu_features *cpu_features) | bit_arch_Fast_Unaligned_Copy | bit_arch_Prefer_PMINUB_for_stringop); break; + } + /* Disable TSX on some Haswell processors to avoid TSX on kernels that + weren't updated with the latest microcode package (which disables + broken feature by default). */ + switch (model) + { case 0x3f: /* Xeon E7 v3 with stepping >= 4 has working TSX. */ if (stepping >= 4)