From patchwork Tue Oct 16 12:49:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 148937 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp5045984lji; Tue, 16 Oct 2018 05:51:29 -0700 (PDT) X-Google-Smtp-Source: ACcGV638CeeDGd131WW+gwn8sbG6DpxhoUApgUptePQ5Rl9wAqQkkTcsEq6EBe+qxuwqevoudQVr X-Received: by 2002:a62:61c7:: with SMTP id v190-v6mr20965813pfb.232.1539694289559; Tue, 16 Oct 2018 05:51:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539694289; cv=none; d=google.com; s=arc-20160816; b=PQYLDWz8h+mPba4inQS3hFVrbRNwp8nrAAFh2+A6hl/2wd7ejOZzQ2adByHu405SH8 2CAFwPeJW9/GUdeKOcDvhUCkJGw7Lzyo2C2D0KFHBve6di9AAJ5/bTCiRAPY/etZ2MDp BiVaeXonVCDXfi0a5GCYdHHG/HWVI9/+Q/MeLyDvzJPjxZfGpoix71wUwnKk5v+8xJ/R FLs+k68RAJVjwVtpMSswSJ2Di3tbGiGqJyhjv2TTGwzZNobEfNgLgcoppagqfqt99izY Q1ImCN65oXRmc1xfGFS6+sZ3Fbb6KzqMEojPWehoFquAwudpsomnN6UpV9p5pzzoMdU5 FOkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=R9GebcV+xqYgjiUFltQRB95RMNSvKtHO21g2/GDZW+U=; b=x1vJ4JO3ybqkOBxXram6Pf/chzhlzUiFvXdt3yCONQheLgq8mRiw2Kz+gOX9ZmTyTh l4cYqmDSS6GDglKs/PC1RH5tN0rNmZbO+BjcToq1AjwyZKPCXeSZyDSD9Vkp1T9CiTJ5 Xwpxx9NLpAVlOTQRaVfOUQ7zqrzoUGq0zP6ZrOJZemWPMr1Q0a7vJO0fvMWkM0bzmMus piuQaoriI50zY3msiUVEA/Qr0J+ohpvkFe27h6O8QaUlEizf6SR5pwNyEHKii2pe8nae VUL+P8R+oCYpa3UxDbBTkPJ+AxU+EXpUVBLGFEqD5i7sDOKu3AmK+o0jxPA1fjR3OUCE dg+w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w4-v6si13647905pll.214.2018.10.16.05.51.29; Tue, 16 Oct 2018 05:51:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727233AbeJPUls (ORCPT + 9 others); Tue, 16 Oct 2018 16:41:48 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:13665 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727210AbeJPUls (ORCPT ); Tue, 16 Oct 2018 16:41:48 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 040CB712C460B; Tue, 16 Oct 2018 20:51:19 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.399.0; Tue, 16 Oct 2018 20:51:13 +0800 From: Shameer Kolothum To: , , CC: , , , , , , , , , , , Subject: [PATCH v4 3/4] perf/smmuv3: Add MSI irq support Date: Tue, 16 Oct 2018 13:49:19 +0100 Message-ID: <20181016124920.24708-4-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20181016124920.24708-1-shameerali.kolothum.thodi@huawei.com> References: <20181016124920.24708-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org This adds support for MSI-based counter overflow interrupt. Signed-off-by: Shameer Kolothum --- drivers/perf/arm_smmuv3_pmu.c | 58 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) -- 2.7.4 diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c index e30b939..d927ef8 100644 --- a/drivers/perf/arm_smmuv3_pmu.c +++ b/drivers/perf/arm_smmuv3_pmu.c @@ -68,6 +68,7 @@ #define SMMU_PMCG_OVSSET0 0xCC0 #define SMMU_PMCG_CFGR 0xE00 #define SMMU_PMCG_CFGR_RELOC_CTRS BIT(20) +#define SMMU_PMCG_CFGR_MSI BIT(21) #define SMMU_PMCG_CFGR_SID_FILTER_TYPE BIT(23) #define SMMU_PMCG_CFGR_SIZE_MASK GENMASK(13, 8) #define SMMU_PMCG_CFGR_NCTR_MASK GENMASK(5, 0) @@ -78,6 +79,12 @@ #define SMMU_PMCG_IRQ_CTRL 0xE50 #define SMMU_PMCG_IRQ_CTRL_IRQEN BIT(0) #define SMMU_PMCG_IRQ_CFG0 0xE58 +#define SMMU_PMCG_IRQ_CFG1 0xE60 +#define SMMU_PMCG_IRQ_CFG2 0xE64 + +/* MSI config fields */ +#define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2) +#define MSI_CFG2_MEMATTR_DEVICE_nGnRE 0x1 #define SMMU_DEFAULT_FILTER_SPAN 1 #define SMMU_DEFAULT_FILTER_STREAM_ID GENMASK(31, 0) @@ -587,11 +594,62 @@ static irqreturn_t smmu_pmu_handle_irq(int irq_num, void *data) return IRQ_HANDLED; } +static void smmu_pmu_free_msis(void *data) +{ + struct device *dev = data; + + platform_msi_domain_free_irqs(dev); +} + +static void smmu_pmu_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) +{ + phys_addr_t doorbell; + struct device *dev = msi_desc_to_dev(desc); + struct smmu_pmu *pmu = dev_get_drvdata(dev); + + doorbell = (((u64)msg->address_hi) << 32) | msg->address_lo; + doorbell &= MSI_CFG0_ADDR_MASK; + + writeq_relaxed(doorbell, pmu->reg_base + SMMU_PMCG_IRQ_CFG0); + writel_relaxed(msg->data, pmu->reg_base + SMMU_PMCG_IRQ_CFG1); + writel_relaxed(MSI_CFG2_MEMATTR_DEVICE_nGnRE, + pmu->reg_base + SMMU_PMCG_IRQ_CFG2); +} + +static void smmu_pmu_setup_msi(struct smmu_pmu *pmu) +{ + struct msi_desc *desc; + struct device *dev = pmu->dev; + int ret; + + /* Clear MSI address reg */ + writeq_relaxed(0, pmu->reg_base + SMMU_PMCG_IRQ_CFG0); + + /* MSI supported or not */ + if (!(readl(pmu->reg_base + SMMU_PMCG_CFGR) & SMMU_PMCG_CFGR_MSI)) + return; + + ret = platform_msi_domain_alloc_irqs(dev, 1, smmu_pmu_write_msi_msg); + if (ret) { + dev_warn(dev, "failed to allocate MSIs\n"); + return; + } + + desc = first_msi_entry(dev); + if (desc) + pmu->irq = desc->irq; + + /* Add callback to free MSIs on teardown */ + devm_add_action(dev, smmu_pmu_free_msis, dev); +} + static int smmu_pmu_setup_irq(struct smmu_pmu *pmu) { unsigned long flags = IRQF_NOBALANCING | IRQF_SHARED | IRQF_NO_THREAD; int irq, ret = -ENXIO; + smmu_pmu_setup_msi(pmu); + irq = pmu->irq; if (irq) ret = devm_request_irq(pmu->dev, irq, smmu_pmu_handle_irq,